Summary

For GL devices, the drive currents of the devices with various PMA conditions would not vary a lot. They were almost the same. The other side, the leakage currents and

For GF devices, the drive currents of the devices with various thicknesses of capping layer were different. The other side, the leakage currents would be decreased by the capping layer. The threshold voltages of the devices with various thicknesses of capping layer were related to the Dit and the oxygen vacancies in the gate dielectric. The thicker capping layer would induce much Dit in gate dielectric, thus there was the larger threshold voltage shift. With the deposition of the capping layer, the oxygen in the gate dielectric would be pulled into the capping layer, which caused more oxygen vacancies in the gate dielectric. Therefore, the threshold voltage would decrease while the thickness of the capping layer increased. That effect was obvious for the devices with the LaO deposition than the AlO ones.

The flat-band voltages both of the NMOS and PMOS devices without PMA condition were the smallest. The normalized C-V curves both of the NMOS and PMOS devices were almost overlapped, which means the Dit of the devices would not vary a lot with various PMA conditions. The C-V curves of the GF devices almost revealed the same trend to the GL devices, but the slopes of the curves in accumulation region were different.

The Dit of the GF devices would change with various deposition thicknesses. The thicker capping layer would induce much Dit in gate dielectric, because more cycles of deposition would induce more oxygen to release from high-k dielectric and thus result in more oxygen vacancies, which would cause flat-band voltage shift. Thus there was the larger threshold voltage shift with much Dit in gate dielectric. Besides, The Dit of the GL devices would not vary a lot according to the accumulation region of the C-V curves.

Table 3.1 Various factors of the 12 inch wafers

Various factors of the 12 inch wafers

Without Post Metallization Annealing Condition

With 400^oC Annealing and Oxygen Post Treatment

With 400^oC Annealing and Nitrogen Post Treatment

With 450^oC Annealing and Oxygen Post Treatment

Gate Last

With 450^oC Annealing and Nitrogen Post Treatment

Without Lanthanum Oxide Post Treatment

With Lanthanum Oxide 15C Post Treatment

LaO

With Lanthanum Oxide 30C Post Treatment

Without Aluminum Oxide Post Treatment

With Aluminum Oxide 6C Post Treatment

Gate First

AlO

With Aluminum Oxide 11C Post Treatment

Table 3.2 Experiment methods and parameters setup

Device

Characteristics

Measured Type

Parameter Setup

Vth, Sub-Threshold

Swing (SS), ID, Gm

ID-VG VG = -05 ~ 1.5 V (Sweeep Mode) VD = 0.05 ~ 1.5 V (Step Mode) VS = VB = 0 V (Common Mode) (For NMOS. Add minus if PMOS) Drive Current (ID) ID-VD VG = Vth + 1 V (Constant Mode) (For NMOS. Add minus if PMOS) Capacitance,

Equivalent Oxide Thickness (EOT)

C-V Frequency = 1 MHz

VG range depends on the curve shape (Sweeep Mode)

ICP, Interface Trap Pulse Period = 1μsec

Vbase range depends on the curve shape Reliability Constant

Voltage Stress

Room Temperature

VG = Vstress (Constant Mode)

VD = VS = VB = 0 V (Common Mode)

(a)

(b)

Figure 3.1 Structure of the (a) gate last and (b) gate first devices

Source Drain

Silicon Substrate IL

Two Metals HK Gate Oxide

Source Drain IL

HK Gate Oxide LaO or AlO

TiN

Silicon Substrate

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Without PMA

With 400^oC O₂ PMA With 400^oC N

2 PMA W = 10 um

L = 1 um

Both NMOS & PMOS

(a)

Without LaO LaO15C LaO30C Without AlO AlO6C AlO11C

W = 10 um L = 1 um

(b)

0.0 0.5 1.0 1.5

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

NMOS W = 10 um L = 1 um

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

I

G

(A )

V

G

(V)

(c)

Figure 3.3 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate last NMOS devices with various PMA conditions

-1.5 -1.0 -0.5 0.0

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

PMOS W = 10 um L = 1 um

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

I

G

(A)

V

G

(V)

(c)

Figure 3.4 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate last PMOS devices with various PMA conditions

0.3

W=10um L=1um

V

t

(vol ts)

W=10um L=1um

V

t

(volts)

(b)

0.0 0.5 1.0 1.5

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

No LaO LaO15C LaO30C

NMOS W = 10 um L = 1 um

I

G

(A )

V

_G

(Volts)

(c)

Figure 3.6 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate first NMOS devices with various thicknesses of capping layer

-1.5 -1.0 -0.5 0.0

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

No AlO AlO6C AlO11C PMOS

W = 10 um L = 1 um

I

G

(A )

V

_G

(Volts)

(c)

Figure 3.7 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate first PMOS devices with various thicknesses of capping layer

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

LaO30C LaO15C

Without LaO

NMOS

W=10um L=1um

V

t

(v olts)

(a)

-0.7 -0.6 -0.5 -0.4 -0.3

AlO11C AlO6C

Without AlO PMOS

W=10um L=1um

V

t

(vo lts)

(b)

Figure 3.8 The threshold voltages both of the gate first

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0

0.5 1.0 1.5 2.0

f = 1MHz NMOS

W = 10 um L = 1 um

V

G

(Volts)

C (pF)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(a)

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0

0.5 1.0 1.5 2.0

f = 1MHz PMOS W = 10 um L = 1 um

V

G

(Volts)

C (pF)

400C O2 PMA 450C O2 PMA 400C N2 PMA 450C N2 PMA

No PMA

(b)

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0.0

0.5 1.0 1.5 2.0

f = 1MHz NMOS

W = 10 um L = 1 um

V

G

-V

FB

(Volts)

C ( pF)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(a)

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0

0.5 1.0 1.5 2.0

f = 1MHz PMOS W = 10 um L = 1 um

V

G

-V

FB

(Volts)

C ( pF)

400C O2 PMA 450C O2 PMA 400C N2 PMA 450C N2 PMA

No PMA

(b)

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0.0

0.5 1.0 1.5 2.0 2.5 3.0

f = 1MHz NMOS

W = 10 um L = 1 um

V

G

(Volts)

C ( pF)

No LaO LaO15C LaO30C

(a)

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0

0.5 1.0 1.5 2.0 2.5 3.0

f = 1MHz PMOS

W = 10 um L = 1 um

V (Volts)

C (pF)

No ALO AlO6C AlO11C

(b)

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5

-2.0 -1.5 -1.0 -0.5 0.0 0.5 -0.05

0.00 0.05 0.10 0.15 0.20

f = 1MHz NMOS W = 10 um L = 1 um

V (Volts) I

CP

(uA)

No LaO LaO15C LaO30C

(a)

-2.0 -1.5 -1.0 -0.5 0.0 0.5

-0.05 0.00 0.05 0.10 0.15 0.20

f = 1MHz PMOS W = 10 um L = 1 um

V (Volts) I

CP

(uA)

No ALO AlO6C AlO11C

(b)

Chapter 4

Reliability of High-k/Metal Gate Devices with Various Post Treatments

4.1 Methods of the Measured Work

After the basic measured work, stress steps could be executed. The stress step should be executed after the other measured steps to realize the reliability of the samples.

The stress treatment would cause more defects thus increase the leakage current, and the device was not in fresh condition anymore. The setup of the stress measurements were shown earlier in Table 3.2.

In order to extract the reliability of the devices, stress steps were added among every time I-V measuring. If necessary, C-V and Charge Pumping measuring could be added in the same condition. The way of stress is providing a constant voltage for gate terminal while the other terminals were grounded. The constant voltage was chosen from Vth and then added a constant value, like 1 or 1.5 V. That voltage was higher than used to be applied for basic characteristics measuring.

During a stress, ICS auto-measurement would extract I-V every period. That data was useful to realize the variation of the device. In this work, at first, a device would be measured for basic characteristics in fresh condition, and then it was provided with five time stresses. After every time stress, the device would be measured for basic characteristics again.

In addition, more precise details were shown in Table 4.1. The purpose of the stress was that used to realize the degradation during the stress process. Higher gate voltage would induce more defects and accelerate destruction of the device. This degradation could be taken to determine and estimate the extent of destruction that a device could resist, and how long the device could be used.

4.2 Experimental Results and Discussion

In this section, it was focused on the results of gate last devices. According to Chapter 3, these 12 inch wafers of GL process were manufactured with various post metallization annealing (PMA) treatments. The PMA treatments were fabricated with oxygen or nitrogen, and the annealing temperatures were 400^oC or 450^oC, respectively.

These factors constituted various treatments of the PMA conditions.

4.2.1 Reliability of the Gate Last Devices

For the GL devices with various PMA conditions, Figure 4.1 shows the IDVD curves after stress treatments for the NMOS devices, as well as the IDVG curves and the IGVG

curves were shown in Figure 4.2 and Figure 4.3. The constant voltage stress which applied to the devices was Vt + 1.5 V. It was found that there was the degradation of the drive currents after the stress work. The best reliability of all samples was the devices with oxygen treatments, and the worst one was the devices with nitrogen treatments.

The reason might that the bonding energy between silicon and oxygen would be stronger than the silicon and nitrogen one in the gate dielectric, thus the bonding with nitrogen would be easier to be broken than the oxygen one and then produced more traps in the gate dielectric, even more than the one without PMA condition. Besides, it was found that the stressing effect of the devices with oxygen treatments would be sensitive to the annealing temperature.

According to Figure 4.2 and Figure 4.3, the threshold voltages of the devices with nitrogen treatments and without PMA condition were shift after the stresses, while the one with oxygen treatments was not varied a lot. The degradation of Dit and the bulk traps of the device with PMA conditions were reduced. Figure 4.4 shows the ID degradation and the Vt variation of these gate last NMOS devices. It was found that the devices with the oxygen treatments would be improved the most.

For the PMOS ones of GL, Figure 4.5 shows the IDVD curves of the PMOS devices after stress treatments, while the IDVG and the IGVG curves were shown in Figure 4.6 and Figure 4.7. The constant voltage stress which applied to the devices was Vt - 1.2 V. The drive currents degradation of the devices with PMA conditions was reduced. The

one.

As the above-mentioned, ID degradation and the Vt variation were used to determine the reliability of the devices. To compare with the results of which were shown in Figure 4.4 and Figure 4.8, there were the other four stress voltages with the same operation steps.

For NMOS, there were the results with Vt + 2 V and Vt + 1.2 V shown in Figure 4.9 and Figure 4.10, respectively. For PMOS, there were the results with Vt - 1 V and Vt – 0.7 V shown in Figure 4.11 and Figure 4.12, respectively. Therefore, the stress results both of NMOS and PMOS were shown with three various stress voltage, respectively.

According to Figure 3.2, it was found that the drain currents of NMOS would be higher than the ones of PMOS. Thus, the three stress voltages of the PMOS were not as high as the NMOS to avoid the devices breakdown.

Figure 4.13 shows the Vt shift of the GL devices after the various constant voltage stresses. Both NMOS and PMOS results were shown with three stress voltages. It was found that the threshold voltage of the device with the oxygen treatments was the highest than the other ones. The reason might that the oxygen vacancies in the gate dielectric were filled up with the oxygen treatments. That effect was not obvious for the nitrogen treatments. Thus the threshold voltage of the devices with the oxygen treatments was highest and with the least variation after the stress. Besides, the stressing effects of the devices with oxygen treatments were sensitive to the annealing temperature, as well as the nitrogen ones were not sensitive so much.

The threshold voltage variations of the NMOS devices were larger than the ones of the PMOS devices. Especially the threshold voltage variation of the NMOS device with nitrogen treatments was the largest one. The weaker bonding energy between silicon and nitrogen caused that the bond with nitrogen would be easier to be broken than the oxygen one. Thus there were more traps in the gate dielectric with the nitrogen treatment than the oxygen one. Those traps would capture the carriers, and thus the threshold voltage variation of the NMOS device with nitrogen treatments would be the largest one.

Finally, the results of the ID degradation and the Vt variation with the three stress voltage were compared together. They were shown in Figure 4.14 and Figure 4.15 for NMOS and PMOS, respectively. The results were based on logarithmic y-axis and they

4.3 Summary

It was found that there was the degradation of the drive currents after the stress work. For NMOS, The best reliability of all samples was the devices with oxygen treatments, and the worst one was the devices with nitrogen treatments, even worse than the one without PMA condition. In other side, for PMOS, the devices with nitrogen treatments were batter than the one without PMA condition, and not worse than the oxygen ones so much. The reason might that the carriers in NMOS and PMOS devices are electrons and holes, respectively. The mass and the mobility of electrons and holes are different, thus the transmitted principle of them were different and caused different results.

Besides, the same constant voltage might induce different degradation to NMOS and PMOS. That would also cause different results.

As the above-mentioned, the devices with the oxygen treatments would be improved the most both of NMOS and PMOS. The degradation of drive currents, Dit and the bulk traps of the devices with the oxygen treatments were reduced.

Furthermore, the bonding energy between silicon and oxygen would be stronger than the silicon and nitrogen one in the gate dielectric, thus the bonding with nitrogen would be easier to be broken than the oxygen one and then produced more traps in the gate dielectric, even more than the one without PMA condition for NMOS. Besides, it was found that the stressing effect of the devices with oxygen treatments would be sensitive to the annealing temperature. While the annealing temperature was increased, the threshold voltage would increase obviously.

It was found that the threshold voltages of the devices with nitrogen treatments and without PMA condition were shift after the stresses, while the one with oxygen treatments was not varied a lot. The threshold voltage of the device with the oxygen treatments was the highest than the other ones. The reason might that the oxygen vacancies in the gate dielectric were filled up with the oxygen treatments. That effect was not obvious for the nitrogen treatments. Thus the threshold voltage of the devices with the oxygen treatments was highest and with the least variation after the stress. Besides, the stressing effects of the devices with oxygen treatments were sensitive to the annealing temperature, as well

nitrogen treatments was the largest one. The weaker bonding energy between silicon and nitrogen induced that the bond with nitrogen would be easier to be broken than the oxygen one. Thus there were more traps in the gate dielectric with the nitrogen treatment than the oxygen one. Those traps would capture the carriers, and thus the threshold voltage variation of the NMOS device with nitrogen treatments would be the largest one.

It was matched that the best reliability of all samples was the devices with oxygen treatments, and the higher stress voltage would cause the much ID degradation and Vt

variation.

Eventually, Figure 4.16 shows the energy bands of various states, which were accumulation, depletion and weak inversion, strong inversion before tunneling occurs and tunneling Occurs. They were matched to the above-mentioned results.

Table 4.1 Stress experiment setting flow chart

No

Yes

Measure ID-VG, ID-VD and IG-VG at room temperature and fresh condition

Stress condition setting

Measure ID-VG, ID-VD and IG-VG

after every time stress

Whether all stress measurements are

accomplished

After all stress measurements are accomplished, measure final time ID-VG, ID-VD and IG-VG

ICS auto-measurement

If necessary, measure Charge Pumping and C-V at the same condition, and also does the following steps

Start

Finish

0.0 0.5 1.0 1.5

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress NMOS

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress NMOS

W: 10 um L: 1 um

0.0 0.5 1.0 1.5

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress NMOS

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress NMOS

W: 10 um L: 1 um

0.0 0.5 1.0 1.5 0.0

0.5 1.0 1.5

2.0 450^oC N₂ PMA

V_G = V_t + 1 Vstress= V

t+1.5 V

I

D

(m A/um )

V

_D

(Volts)

Fresh

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress NMOS

W: 10 um L: 1 um

(e)

Figure 4.1 I

DVD curves of the NMOS devices which (a) without PMA, (b) with 400^oC O2, (c) with 400^oC N2, (d) with 450^oC O2 and

(e) with 450^oC N2 conditions after the stresses

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress No PMA

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

400^oC O₂ PMA

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

400^oC N₂ PMA

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

450^oC O

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

Fresh

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

450^oC N₂ PMA V_stress= V_t+1.5 V

NMOS W: 10 um L: 1 um

I

D

( A /um )

V

G

(Volts)

(e)

Figure 4.2 I

DVG curves of the NMOS devices which (a) without PMA, (b) with 400^oC O2, (c) with 400^oC N2, (d) with 450^oC O2 and

(e) with 450^oC N2 conditions after the stresses

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

No PMA

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

400^oC O₂ PMA

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

400^oC N₂ PMA

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

450^oC O₂ PMA

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

Fresh

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

450^oC N₂ PMA V_stress= V_t+1.5 V NMOS

W: 10 um L: 1 um

I

G

(A/um)

V

_G

(Volts)

(e)

Figure 4.3 I

GVG curves of the NMOS devices which (a) without PMA, (b) with 400^oC O2, (c) with 400^oC N2, (d) with 450^oC O2 and

(e) with 450^oC N2 conditions after the stresses

0 5 10 15 0

5 10 15

20 NMOS

W=10um L=1um Vstress= V

t+1.5 V

I

D

De gradation (%)

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(a)

0 5 10 15

0 5 10 15 20 25 30

NMOS

W=10um L=1um V_stress= V_t+1.5 V

V

t

vari a ti on (%)

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(b)

-1.5 -1.0 -0.5 0.0 0.0

0.5

No PMA

V_G = V_t - 1 Vstress= V

t-1.2 V

I

D

(m A/um )

V

_D

(Volts)

Fresh

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

PMOS W: 10 um L: 1 um

(a)

-1.5 -1.0 -0.5 0.0

0.0 0.5

400C O₂ PMA

V_G = V_t - 1 V_stress= V_t-1.2 V

I

D

(mA /um)

V

D

(Volts)

Fresh

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

PMOS W: 10 um L: 1 um

-1.5 -1.0 -0.5 0.0

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

PMOS

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

PMOS W: 10 um L: 1 um

-1.5 -1.0 -0.5 0.0 0.0

0.5

450C N

2 PMA

V_G = V_t - 1 Vstress= V

t-1.2 V

I

D

(m A/um )

V

_D

(Volts)

Fresh

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

PMOS W: 10 um L: 1 um

(e)

Figure 4.5 I

DVD curves of the PMOS devices which (a) without PMA, (b) with 400^oC O2, (c) with 400^oC N2, (d) with 450^oC O2 and

(e) with 450^oC N2 conditions after the stresses

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

No PMA

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

400C O₂ PMA

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

400C N₂ PMA

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

450C O₂ PMA

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

Fresh

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

450C N₂ PMA V_stress= V_t-1.2 V PMOS

W: 10 um L: 1 um

I

D

(A/ u m)

V

G

(Volts)

(e)

Figure 4.6 I

DVG curves of the PMOS devices which (a) without PMA, (b) with 400^oC O2, (c) with 400^oC N2, (d) with 450^oC O2 and

(e) with 450^oC N2 conditions after the stresses

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress No PMA

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

400C O₂ PMA

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

400C N₂ PMA

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

450C O₂ PMA

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

Fresh

After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress

450C N₂ PMA V_stress= V_t-1.2 V

PMOS W: 10 um L: 1 um

I

G

(A/um)

V

G

(Volts)

(e)

Figure 4.7 I

GVG curves of the PMOS devices which (a) without PMA, (b) with 400^oC O2, (c) with 400^oC N2, (d) with 450^oC O2 and

(e) with 450^oC N2 conditions after the stresses

0 5 10 15 0

5 10 15 20 25

PMOS

W=10um L=1um Vstress= V

t-1.2 V

I

D

Deg rad atio n (%)

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(a)

0 5 10 15

0 5

PMOS

W=10um L=1um V_stress= V_t-1.2 V

V

t

vari ati o n (%)

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(b)

0 5 10 15

W=10um L=1um Vstress= V

t+2 V

I

D

Degradation (%)

Stress Time (minutes)

No PMA

W=10um L=1um V_stress= V_t+2 V

V

t

variation (%)

Stress Time (minutes)

No PMA

0 5 10 15 0

5 10

NMOS

W=10um L=1um Vstress= V

t+1.2 V

I

D

D e gr ada tion (% )

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(a)

0 5 10 15

0 5 10 15 20

NMOS

W=10um L=1um V_stress= V_t+1.2 V

V

t

v a ria tion (%)

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(b)

0 5 10 15 0

5 10 15

PMOS

W=10um L=1um Vstress= V

t-1 V

I

D

Degradatio n (%)

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(a)

0 5 10 15

0 5 10

PMOS

W=10um L=1um V_stress= V_t-1 V

V

t

v a ria tion (% )

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(b)

0 5 10 15 -1

0 1 2 3

PMOS

W=10um L=1um Vstress= V

t-0.7 V

I

D

Degradation (%)

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(a)

0 5 10 15

-1 0 1 2 3

PMOS

W=10um L=1um V_stress= V_t-0.7 V

V

t

variation (% )

Stress Time (minutes)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(b)

0.3

W=10um L=1um V_stress= V_t+1.5 V

V

t

(volts)

Fresh

After 5 time stress

(a)

W=10um L=1um V_stress= V_t-1.2 V

V

t

(v olts )

Fresh

After 5 time stress

(b)

0.1 1 10 100

NMOS

W=10um L=1um (After 5 time stress) No PMA

400C O2 PMA 450C O2 PMA 400C N2 PMA 450C N2 PMA

+2.0V +1.5V

+1.2V I

d

Degr adation (%)

(a)

0.1 1 10 100 1000

NMOS

W=10um L=1um (After 5 time stress) No PMA

400C O2 PMA 450C O2 PMA 400C N2 PMA 450C N2 PMA

+2.0V +1.5V

+1.2V V

t

va ria tion (%)

(b)

Figure 4.14 (a) I

D degradation and (b) Vt variation of the gate last

0.1 1 10 100

PMOS

W=10um L=1um (After 5 time stress) No PMA

400C O2 PMA 450C O2 PMA 400C N2 PMA 450C N2 PMA

-1.2V -1.0V

-0.7V I

d

Degra d a ti on (% )

(a)

0.1 1 10

PMOS

W=10um L=1um (After 5 time stress) No PMA

400C O2 PMA 450C O2 PMA 400C N2 PMA 450C N2 PMA

-1.2V -1.0V

-0.7V V

t

vari ati o n (%)

(b)

Figure 4.15 (a) I

degradation and (b) V variation of the gate last

(a) Gate

HfO2

I.L.

Si

Before Stress

Gate

HfO2

I.L.

Si

After Stress

Accumulation

Gate HfO2

I.L.

Si

Before Stress After Stress

Depletion and Weak Inversion

HfO2

Gate

Si

I.L.

(c)

Gate HfO2

I.L.

Si

Before Stress After Stress

Tunneling Occurs

HfO2

Gate

Si

I.L.

Gate HfO2

I.L.

Si

Before Stress After Stress

Strong Inversion before Tunneling

HfO2

Gate

Si

I.L.

Chapter 5

Conclusions and Future Work

5.1 Conclusions

Both PMA conditions and the deposition with LaO or AlO of capping layer could

Both PMA conditions and the deposition with LaO or AlO of capping layer could

在文檔中 針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討 (頁 32-0)