針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討

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(1)國立高雄大學電機工程學系 (研究所-微電子組) 碩士論文. 針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討 The Study of High-k/Metal Gate CMOSFET with Various Post Treatments. 研究生：鄭濟允撰指導教授：葉文冠中華民國一百年七月.

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(3) Acknowledgement. 本論文能夠順利完成首先要感謝我的指導教授，葉文冠博士。葉教授在我碩士就學期間指導了研究方向，以及實驗的流程，使本論文的實驗能夠順利進行；甚至還帶領我到 TSMC 體驗業界生活，開拓我的人生視野。再來要感謝實驗室的合作夥伴，高師大電子系的楊教授，楊宜霖博士。楊教授除了在實驗上協助理論分析，在我撰寫論文期間也分享了撰寫經驗，並協助校訂專業理論內容。有了楊教授的指導，讓本論文更加完善。另外也要感謝實驗室的成員們，在我兩年的碩士生涯中為實驗室帶來朝氣與歡笑，增添色彩。還要感謝 UMC 合作提供的 12 吋 wafer，有了這幾批精良的成品，才有後來的實驗成果。最後要感謝我的父母弟弟家人朋友們，因為有他們陪伴我成長，才有今天的我，尤其是我的父母，教導我為人處世、養育供給我讀到研究所，我的心裡滿懷感恩。. I.

(4) 針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討指導教授：葉文冠博士國立高雄大學電機工程學所學生：鄭濟允國立高雄大學電機工程學所摘要在本論文的研究中，我們量測了 Gate Last 和 Gate First 的元件。對 Gate Last 來說，高介電值金屬閘極元件在經過熱退火製程之後，氧和氮會擴散到高介電值金屬閘極元件之中。元件的臨界電壓在 PMA 處理之後將會有所改變。其中摻雜氧的 PMA 製程最能夠改善元件的操作電流衰退、介面陷阱密度和本體缺陷等問題。對 Gate First 元件來說，不同程度的沉積會形成不同厚度的覆蓋層。這些沉積的覆蓋層可以改善漏電流的問題，但是越厚的覆蓋層會造成閘極介電層之中有更多的介面陷阱和氧空缺，進而造成更大的臨界電壓偏移。所以沉積的氧化層厚度應該要謹慎的選擇一個適當的量。 Gate First 製程在業界的發展比 Gate Last 製程早而且成熟，這使得 Gate First 製程有個好處，就是在積體電路設計和製程上不需改變太多步驟即可作業，例如 32 奈米和 28 奈米製程就是如此。但最大的關鍵在於，進入 28 奈米世代之後，Gate Last 製程的元件電性將會比 Gate First 製程優良。. 關鍵字：高介電值金屬閘極、Gate Last、Gate First、PMA、介面陷阱密度、閘極引發汲極漏電流、覆蓋層. II.

(5) The Study of High-k/Metal Gate CMOSFET with Various Post Treatments Advisor: Dr. (Professor) Wen-Kuan Yeh Institute of Electrical Engineering National University of Kaohsiung Student: Chi-Yun Cheng Institute of Electrical Engineering National University of Kaohsiung ABSTRACT In this study, there were both experimental measurements of gate last and gate first devices. For gate last ones, the oxygen and nitrogen were shown to diffuse through the TiN layer in the high-k/metal gate devices during PMA. The threshold voltages of the devices changed with various PMA conditions. The degradation of drive currents, Dit and the bulk traps of the devices were improved the most with the oxygen treatments. For gate first devices, the various cycles of deposition would form various thicknesses of the capping layer. The deposition of capping layer could improve the leakage problems, but thicker capping layer of the gate first devices would induce more Dit and oxygen vacancies in gate dielectric, thus causing larger threshold voltage shift. The deposition cycles of capping layer should be chosen carefully. Gate first process was developed into manufacturing earlier than gate last. The fact leads to one of the advantages is that the integrated circuits design would not have to be changed so much for gate first, like 32nm or 28nm process. But an important point is that the GL devices will have better characteristics than the GF ones while the fabrication process beyond 28nm technology node.. Keywords: High-k/Metal Gate, Gate Last, Gate First, PMA, Dit, GIDL, Capping layer. III.

(6) Contents Acknowledgement ………………………………………………………………….....I Abstract (Chinese) …………………………………………………………………...II Abstract (English) ………………………….……………………………………….III Contents ……………………………………………………………………………..IV List of Figures ……………………………………………………………………....VI List of Tables ………………………………………………………………………..IX Chapter 1 1.1 1.2 1.3. Introduction ……………………………………………………………1. Development of High-k/Metal Gate ……………………………………….1 Gate First and Gate Last …………………………………………………...1 Structure of this Thesis …………………………………………………….2. Chapter 2. Experimental Methods and Basic Concepts …………………………6. 2.1. Experimental Methods …………………………………………………….6 2.1.1 Preparative Work with the Instruments …………………………….6 2.1.2 Performance of the Experiments …………………………………...6 2.2 Basic Concepts of the Devices …………………………………………….7 2.2.1 SILC (Stress-Induced Leakage Current) …………………………...7 2.2.2 SCE (Short-Channel Effects) ………………………………………7 2.2.3 DIBL (Drain-Induced Barrier Lowering) …………………………..7 2.2.4 GIDL (Gate-Induced Drain Leakage) ……………………………...8 2.2.5 HCE (Hot-Carrier Effect) …………………………………………..8 2.2.6 Dit (Interface Trap Density) ………………………………………...8 2.3 Introduction of the Measured Modes ……………………………………...9 2.3.1 I-V Measurement …………………………………………………...9 2.3.2 C-V Measurement ………………………………………………….9 2.3.3 Principle of Charge Pumping ……………………………………..10 Chapter 3. 3.1. Basic Characteristics of High-k/Metal Gate Devices with Various Post Treatments ………………………………………………………18. About the Experiments Working …………………………………………18 3.1.1 The Wafers for the Measured Work ………………………………....18 3.1.2 Setting for ICS ……………………………………………………....19 IV.

(7) 3.2. Experimental Results and Discussion ……………………………………19 3.2.1 I-V …………………………………………………………………..19 3.2.2 C-V ………………………………………………………………….21 3.2.3 Charge Pumping …………………………………………………….21 3.3 Summary …………………………………………………………………21 Chapter 4. Reliability of High-k/Metal Gate Devices with Various Post Treatments ……………………………………………………………42. 4.1 4.2. Methods of the Measured Work ………………………………….............42 Experimental Results and Discussion …………………………………....43 4.2.1 Reliability of the Gate Last Devices ………………………………..43 4.3 Summary …………………………………………………………………45. Chapter 5 5.1 5.2. Conclusions and Future Work ………………………………………77. Conclusions ………………………………………………………………77 Future work …………................................................................................79. Reference …………...................................................................................................81 Appendix …………....................................................................................................84. V.

(8) List of Figures Chapter 1 Introduction Figure 1.1 The threshold voltage mismatch of the devices from Intel ………………3 Figure 1.2 The TEM images of (a) HKMG gate stack (b) HKMG NMOS and PMOS transistors from Intel …………………………………………………………………4 Figure 1.3 Simple structures both of GF and GL from IMEC ……………………….5 Chapter 2 Experimental Methods and Instruments Figure 2.1 The instruments in the laboratory ………………………………………11 Figure 2.2 The 12 inch wafer for the measured experiments ………………………12 Figure 2.3 Probe Station ……………………………………………………………12 Figure 2.4 Agilent HP 4156A (Semiconductor Parameter Analyzer) ……………...13 Figure 2.5 Agilent HP 4284A (Precision LCR Meter) ……………………………..13 Figure 2.6 Agilent HP 81110A (165/330 MHz Pulse/Pattern Generator) ………….14 Figure 2.7 Agilent E5250A (Low-leakage Switch Mainframe) ……………………14 Figure 2.8 Agilent ICS (Interactive Characterization Software) …………………...15 Figure 2.9 Origin …………………………………………………………………...15 Figure 2.10 The diagram of SILC ………………………………………………….16 Figure 2.11 The diagram of HCE …………………………………………………..16 Figure 2.12 The typical Charge Pumping measured system chart …………………17 Chapter 3 Basic Characteristics of HK/MG Devices with Various Post Treatments Figure 3.1 Structure of the (a) gate last and (b) gate first devices ………………….25 Figure 3.2 IDVD curves of the (a) gate last and (b) gate first devices ………………26 Figure 3.3 (a) IDVD (b) IDVG and (c) IGVG curves of the gate last NMOS devices with various PMA conditions …………………………………………………………….28 Figure 3.4 (a) IDVD (b) IDVG and (c) IGVG curves of the gate last PMOS devices with various PMA conditions …………………………………………………………….30 Figure 3.5 The threshold voltages both of the gate last (a) NMOS and (b) PMOS devices ………………………………………………………………………………31 Figure 3.6 (a) IDVD (b) IDVG and (c) IGVG curves of the gate first NMOS devices with various thicknesses of capping layer ………………………………………………..33 Figure 3.7 (a) IDVD (b) IDVG and (c) IGVG curves of the gate first PMOS devices with various thicknesses of capping layer ………………………………………………..35 Figure 3.8 The threshold voltages both of the gate first (a) NMOS and (b) PMOS devices ………………………………………………………………………………36 Figure 3.9 C-V curves of the gate last (a) NMOS and (b) PMOS devices with various VI.

(9) PMA conditions …………………………………………………………………......37 Figure 3.10 Normalized C-V curves of the gate last (a) NMOS and (b) PMOS devices with various PMA conditions ……………………………………………………….38 Figure 3.11 C-V curves of the gate first (a) NMOS and (b) PMOS devices with various thicknesses of capping layer ………………………………………………………...39 Figure 3.12 Normalized C-V curves of the gate first (a) NMOS and (b) PMOS devices with various thicknesses of capping layer …………………………………………..40 Figure 3.13 ICP curves of the gate first (a) NMOS and (b) PMOS devices with various thicknesses of capping layer ………………………………………………………...41 Chapter 4 Reliability of HK/MG Devices with Various Post Treatments Figure 4.1 IDVD curves of the NMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses ………………………………………………………....................................50 Figure 4.2 IDVG curves of the NMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses ………………………………………………………....................................53 Figure 4.3 IGVG curves of the NMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses ………………………………………………………....................................56 Figure 4.4 (a) ID degradation and (b) Vt variation of the gate last NMOS devices after the constant voltage stress which was Vt + 1.5 V ………….......................................57 Figure 4.5 IDVD curves of the PMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses ……………………………………………………….....................................60 Figure 4.6 IDVG curves of the PMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses ……………………………………………………….....................................63 Figure 4.7 IGVG curves of the PMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses ……………………………………………………….....................................66 Figure 4.8 (a) ID degradation and (b) Vt variation of the gate last PMOS devices after the constant voltage stress which was Vt - 1.2 V …………........................................67 Figure 4.9 (a) ID degradation and (b) Vt variation of the gate last NMOS devices after the constant voltage stress which was Vt + 2 V …………...........................................68 Figure 4.10 (a) ID degradation and (b) Vt variation of the gate last NMOS devices after the constant voltage stress which was Vt + 1.2 V …………........................................69 Figure 4.11 (a) ID degradation and (b) Vt variation of the gate last PMOS devices after VII.

(10) the constant voltage stress which was Vt - 1 V …………...........................................70 Figure 4.12 (a) ID degradation and (b) Vt variation of the gate last PMOS devices after the constant voltage stress which was Vt – 0.7 V …………........................................71 Figure 4.13 Vt shift both of the gate last (a) NMOS and (b) PMOS devices after the constant voltage stress …………..................................................................................72 Figure 4.14 (a) ID degradation and (b) Vt variation of the gate last NMOS devices after various constant voltage stresses ………….................................................................73 Figure 4.15 (a) ID degradation and (b) Vt variation of the gate last PMOS devices after various constant voltage stresses ………….................................................................74 Figure 4.16 The energy band states of (a) Accumulation, (b) Depletion and Weak Inversion, (c) Strong Inversion before Tunneling Occurs and (d)Tunneling Occurs ……………………………………………………………………………......76 Chapter 5 Conclusions and Future Work Figure 5.1 Comparison with the various structures of the devices …………………..80 Figure 5.2 Structure of FinFET …………....................................................................80. VIII.

(11) List of Tables Table 1.1 The comparison between HKMG and SiON for 28 nm process from TSMC…………………………………………………………………………………3 Table 3.1 Various factors of the 12 inch wafers …………………………………….23 Table 3.2 Experiment methods and parameters setup ………………………………24 Table 4.1 Stress experiment setting flow chart ……………………………………...47. IX.

(12) Chapter 1 Introduction. 1.1 Development of High-k/Metal Gate Scaling for MOSFET is an important technological task. Recently, high-k/metal gate is necessary for the fabrication process beyond 28nm technology node. Comparing with the traditional silicon oxide gate dielectric, the devices with high-k/metal gate (HKMG) material could be scaled more than the ones with silicon oxide. Table 1.1 shows the comparison between HKMG and silicon oxide for 28 nm fabrication process from TSMC [1]. With high-k/metal gate process, dielectric layer thickness could increase without decreasing gate-substrate equivalent capacitance, and gate leakage density would be reduced with thinner equivalent oxide thickness (EOT) [2]. Therefore, there would be higher drive currents at the same Ioff with lower DIBL. For example, Figure 1.1 shows the threshold voltage mismatch of the devices from Intel. The threshold voltage mismatch of the device increases as the device dimensions shrink. By adopting high-k/metal gate, the trend is reversed, as well as the poly-silicon depletion and the threshold voltage pinning problems are eliminated [3]. That is why the devices with high-k/metal gate could be scaled more than the devices with silicon oxide material. Figure 1.2 shows the TEM image of high-k/metal gate stack and transistors from Intel [4].. 1.2 Gate First and Gate Last Two main process technologies, which are gate first (GF) and gate last (GL), were utilized for the fabrication of high-k/metal gate. Figure 1.3 shows the simple structures of GF and GL high-k/metal gate devices which were proposed by IMEC [5]. There are several advantages and disadvantages for both GF and GL fabrication processes. For the gate first device, high temperature annealing process would induce gate defect, and thus result the threshold voltage shift and consequently cause the chip failed. For the gate last one, that problem could be avoided, so the Vt and work function of the gate last 1.

(13) devices could be controlled superiorly. On the other sides, gate first tech was developed earlier than gate last. The fact leads to one of the advantages is that the integrated circuits design would not have to be changed so much for gate first, like 32nm or 28nm process. One of the problems of gate first is threshold voltage shift. Capping layer is used to reduce threshold voltage for gate first process, but that would induce gate defect and thus degrade the device performance. There appeared more side effects, like short channel effect (SCE) becomes obvious, and product yield cutting down. Gate last process could overcome these problems such as high temperature impact, and improve the device performance, although the integrated circuits of gate last is harder to design than gate first [3][4]. According to some heavyweight companies said (like TSMC and Intel), gate last process is better than gate first while devices are scaling more and more, especially beyond 28 nm node. The reasons are described above.. 1.3 Structure of this Thesis The devices which based on gate last fabrication process and the ones based on gate first were both measured in the experimental work. In chapter 2, how the instruments were used to accomplish the measured experiments is introduced. The comment about the basic concepts of the devices and measurement will also appear in this chapter. In chapter 3, it is an introduction about the basic characteristics, and the results of the measured data are displayed. Eventually, there are discussion and summary with these results. There are the same procedures in chapter 4 like chapter 3, but the point is the reliability for the results with some stress measured experiments, and it is focused on the results of gate last process. Finally, there are some conclusions about all these experiments in chapter 5, and some future work will also be referred to. Several results of this study were also announced to SNDT 2011 (Symposium on Nano Device Technology) at NDL (National Nano Device Laboratories), Hsinchu, Taiwan. The paper was entitled “The Improvement of Reliability of 28nm High-k/Metal Gate Device with Various PMA Conditions.” That paper was also attached in the appendix of final part of this thesis. 2.

(14) Table 1.1 The comparison between HKMG and SiON for 28 nm process from TSMC [1]. Figure 1.1 The threshold voltage mismatch of the devices from Intel [3]. 3.

(15) (a). (b) Figure 1.2 The TEM images of (a) HKMG gate stack (b) HKMG NMOS and PMOS transistors from Intel [4]. 4.

(16) Figure 1.3 Simple structures both of GF and GL from IMEC [5]. 5.

(17) Chapter 2 Experimental Methods and Basic Concepts. 2.1 Experimental Methods In this study, the instruments in the laboratory shown in Figure 2.1 were used to accomplish all the measured experiments. The devices which base on the 12 inch wafers shown in Figure 2.2 were used to do the measured work.. 2.1.1 Preparative Work with the Instruments In these measured experiments, at first, the probe station shown in Figure 2.3 was used to contact the wafer, and then there became a circuit between the devices and the probe station with four-point probe. In Figure 2.7, there is an E5250A (Low-leakage Switch Mainframe) which was used to connect the probe station and the other instruments. The E5250A was used to switch measured modes in these experiments. Figure 2.4 shows the HP 4156A (Semiconductor Parameter Analyzer) which was used to measure I-V curve, as well as the HP 4284A (Precision LCR Meter) shown in Figure 2.5 for C-V curve measurement. In Figure 2.6, HP 81110A (165/330 MHz Pulse/Pattern Generator) was used to measure the data about Charge Pumping. These instruments are the main machines in the measured experiments.. 2.1.2 Performance of the Experiments As soon as all instruments were ready, measured work could be started with ICS (Interactive Characterization Software) shown in Figure 2.8. ICS was the software which was used to control HP 4156A, HP 4284A and HP 81110A for different measuring types. The details about setting parameters will be introduced later in chapter 3. In Figure 2.9, after measured work, the data were drawn with the software, which is named Origin. These results of I-V, C-V and Charge Pumping were used to analyze and explore for the study.. 6.

(18) 2.2 Basic Concepts of the Devices In the experimental work, the characteristics of devices are affected by many factors. In order to research successfully, realization of some basic concepts is necessary. The following paragraphs are some useful items.. 2.2.1 SILC (Stress-Induced Leakage Current) Stress-induced leakage current (SILC) is the current which occur in gate layer while the device is applied to the constant voltage or current stress. While the oxide thickness become thinner more and more, SILC is an important problem and the reliability of the device would be varied. Thus, SILC is used to characterize the degradation of ultra-thin gate oxides and to predict their breakdown and lifetime, as it is generally believed that SILC is induced by defects generated in gate oxides [6]. Figure 2.10 shows the diagram of SILC.. 2.2.2 SCE (Short-Channel Effects) The short-channel effects on threshold voltage become significant while the channel length becomes less than approximately 2 um. As the channel length reduces, the charge in the channel region which controlled by the gate would decrease. While the drain voltage increases, the reverse-biased space charge region at the drain would extend into the channel area. Therefore, the bulk charge which controlled by the gate would decrease. These results induced the threshold voltage of the nMOSFET shifts in the negative direction [7]. In other word, SCE induced threshold voltage roll-off. SCE would also cause DIBL, and higher leakage currents while the device cut-off. Therefore, even the gate voltage is be grounded, there are leakage currents flow through the source and the drain [8].. 2.2.3 DIBL (Drain-Induced Barrier Lowering) When the drain voltage of the short-channel device increases from the linear region toward the saturation region, the device threshold voltage would roll-off becomes larger. That would induce the threshold voltage decreased further with increasing drain 7.

(19) voltage in the short-channel device. This phenomenon is called DIBL [7].. 2.2.4 GIDL (Gate-Induced Drain Leakage) While the gate terminal is provided an enough big voltage, the high electric field in depletion region would induce the band to band tunneling leakage in the drain region underneath the gate. That is called GIDL current. When a high electric field is applied to a p-n junction in the reverse direction, the valence electron could make a transition from the valence band to the conduction band. The process that the electron penetrate through the energy band-gap is called tunneling effect [7].. 2.2.5 HCE (Hot-Carrier Effect) Considering the tunneling effect, as the electric field in the drain junction space charge region increases, electron-hole pairs could be generated by impact ionization. The generated electrons tend to be swept to the drain and generated holes swept into the substrate of the device. Some of the electrons generated in the space charge region are attracted to the oxide due to the electric field induced by a gate voltage. Figure 2.11 shows the diagram of HCE. HCE would induce the substrate currents increased, and the drain currents could not saturate in saturation region. The drain currents would increase when the drain voltage increase. As the serious condition, punch trough would occur with more leakage currents [8].. 2.2.6 Dit (Interface Trap Density) Dit is the density of the interface. In addition, Nit is the interface trap numbers. They mean the trapped charge condition in the interface layer. The traps would capture the carriers and thus affect the characteristics of the device. The Dit is calculated by Dit = (ICP/qAfΔE), where ICP is the measured Charge Pumping currents, q is the fundamental electronic charge, A is the area, f is the frequency, and ΔE is the difference between the inversion Fermi level and the accumulation Fermi level [9].. 8.

(20) 2.3 Introduction of the Measured Modes In order to perform the measured experiments successfully, not only the measured steps but also the principles of the measurement should be realized. That would be helpful in the study. The following are some items about that.. 2.3.1 I-V Measurement It is three types, IDVD, IDVG and IGVG, of I-V measurements. There are the figures of the I-V curves shown in Chapter 3 and Chapter 4. In IDVD measured work, ID versus VD curves could be extracted. That could be used to decide the characteristics while the device was operating. For the drawing of IDVG and IGVG figures, the original data would be added modulus and then transferred into logarithm type. For IDVG curve, threshold voltage of the device could be extracted, and the sub-threshold swing (SS) could be determined. For IGVG curve, leakage currents flowed through the gate layer could be observed. These I-V curves composed to characteristics of the device.. 2.3.2 C-V Measurement As the C-V measured experiments, the results of C-V curves would include accumulation, depletion, weak inversion and strong inversion. During the accumulation region, the carriers would accumulate at the interface between Si and gate dielectric. The capacitance value would be determined by almost only by the Cox since the CSD is very high. In accumulation region, the capacitance value would decrease while the carriers accumulate more and more. When the gate voltage is higher than the flat-band voltage, the device would go into depletion and weak inversion region. At this time, the CSD would become smaller so that the capacitance value would be determined by both the Cox and the CSD. Therefore, the capacitance value would approach to a saturation state with the high frequency. With the low frequency, when the gate voltage is higher than the threshold voltage, bigger voltage would lead to the holes at the gate layer go through interface and combine with the electrons at the interface. That would cause the CSD become higher so that the capacitance value would back to be determined by almost only by the Cox. That is called strong inversion [8]. 9.

(21) In this study, the C-V measurement was provided with the voltage of substrate, not gate. Thus, The C-V data should be added a minus to the voltage value. There are the figures of the C-V curves shown in Chapter 3 and Chapter 4.. 2.3.3 Principle of Charge Pumping There is the typical Charge Pumping measured system chart shown in Figure 2.12. As the figure showing, the source and drain (S/D) of the device are connected together with a variable voltage source. The channel would be conducted while the device is applied to a high voltage pulse and achieves inversion region. Therefore, the charges in the source and drain region could move through the channel, and they are liable to be captured by the traps in the surface. The channel would return to depletion while the device is applied to a low voltage pulse, and the mobile charge would come back to the S/D terminals. The charges which are captured by the traps could not come back to the S/D region. They would have recombination with the majority carriers from the substrate and then increase the currents in substrate. This phenomenon is called Charge Pumping [10]. By exploring the currents (ICP) from Charge Pumping measurement, Dit and the defect of the device could be estimated.. 10.

(22) Figure 2.1 The instruments in the laboratory. 11.

(23) Figure 2.2 The 12 inch wafer for the measured experiments. Figure 2.3 Probe Station. 12.

(24) Figure 2.4 Agilent HP 4156A (Semiconductor Parameter Analyzer). Figure 2.5 Agilent HP 4284A (Precision LCR Meter). 13.

(25) Figure 2.6 Agilent HP 81110A (165/330 MHz Pulse/Pattern Generator). Figure 2.7 Agilent E5250A (Low-leakage Switch Mainframe). 14.

(26) Figure 2.8 Agilent ICS (Interactive Characterization Software). Figure 2.9 Origin. 15.

(27) Figure 2.10 The diagram of SILC [6]. Figure 2.11 The diagram of HCE [8]. 16.

(28) Figure 2.12 The typical Charge Pumping measured system chart [10]. 17.

(29) Chapter 3 Basic Characteristics of High-k/Metal Gate Devices with Various Post Treatments. 3.1 About the Experiments Working As the beginning for the experiments, it is necessary to realize the composition of the devices. Various post treatments induced various structures and measured results for the devices. In order to work the experiments successfully, the setting for the software is very important. The following are comments about both devices forming and software setting.. 3.1.1 The Wafers for the Measured Work The devices which based on GL and GF process were both measured in the experimental work. For these 12 inch wafers, it were focused on results of the gate last process, and then compared to results of the gate first process. For GL process, these 12 inch wafers were manufactured with various post metallization annealing (PMA) treatments. The PMA treatments were fabricated with oxygen or nitrogen, and the annealing temperatures were 400oC or 450oC, respectively. These factors constituted various treatments of the PMA conditions. First, there was a wafer without any post metallization annealing. Second, there was a wafer with 400oC annealing and oxygen post treatment, and another one with nitrogen post treatments at the same annealing temperature. Third, there was a wafer with 450oC annealing and oxygen post treatment, and another one with nitrogen post treatment at the same temperature, respectively. For GF process, those 12 inch wafers were manufactured with the capping layer of the lanthanum oxide (LaO) and aluminum oxide (AlO) for NMOS and PMOS, respectively. The various cycles of deposition would cause various thicknesses of the capping layer. The purpose of the deposition of capping layer is to tune the threshold voltage. There were various deposition thicknesses both of the LaO and AlO which cause the various threshold voltage effects of the devices. The thicker capping layer 18.

(30) would induce much Dit in gate dielectric, thus there was the larger threshold voltage shift. Titanium nitride (TiN) was used as the gate electrodes for both GL and GF process devices. These various factors of the 12 inch wafers were listed in Table 3.1, and the simple structure both of the GL and GF devices were shown in Figure 3.1.. 3.1.2 Setting for ICS After the preparation for the instruments which were mentioned in chapter 2, ICS used to measure I-V, C-V, and Charge Pumping. For I-V measuring, the terminals of source and body would be grounded. Gate and drain would be provided with the voltage in sweep mode or step mode. The mode selecting depends on IDVG or IDVD measuring. C-V and Charge Pumping settings were similar to I-V, and both of their VG range selecting depends on the curve shape. The frequency would also affect the curves. To describe accurately, the detailed setting appeared in Table 3.2. It also shows the stress details for reliability which will be discussed in chapter 4.. 3.2 Experimental Results and Discussion It was found that the characteristics of nMOSFETs and pMOSFETs were not symmetrical. Figure 3.2 shows the IDVD curves both of GL and GF devices. No matter GL or GF devices, the currents of PMOS were smaller than NMOS ones. The key factor was that the carrier of NMOS devices was electron, and the carrier of PMOS was holes. Their operational principles were different. Therefore, the results of NMOS and PMOS should be discussed respectively. The experimental results would be discussed later.. 3.2.1 I-V Currents versus voltage curves of the gate last NMOS devices were shown in Figure 3.3. For the normalized IDVD curves, VG was set as (Vt + 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. The purpose was eliminating the effect of threshold voltage. It was found that IDVD curves with various PMA conditions were closed. The largest difference of the drain currents at saturation region of all the samples was less than 0.15mA. They were not varied a lot. It was found that the GIDL of the device without 19.

(31) PMA condition would be highest than the others according to the figure of normalized IDVG curves. The leakage currents in gate layer would reveal the same trend according to the figure of IGVG curves. The gate leakage currents of the device without PMA condition would be also the highest one. Figure 3.4 shows the I-V curves of the gate last PMOS devices. For the normalized IDVD curves, VG was set as (Vt – 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. They revealed the same trend to NOMS. The drain currents at saturation region with various post treatments were almost the same. The gate leakage currents of the device without PMA condition would be the highest one. It was found that the gate leakage currents would be decreased by PMA post treatments. The threshold voltages of the devices with various PMA conditions were different shown in Figure 3.5. It was related to the Dit and the oxygen vacancies in the gate dielectric. They would be discussed later in chapter 4. I-V curves of the gate first NMOS devices were shown in Figure 3.6. For the normalized IDVD curves, VG was set as (Vt + 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. The purpose was eliminating the effect of threshold voltage. The IDVD curves with various thicknesses of capping layer were different. The differences of the drain currents at saturation region were under 0.1 mA, but the GF drive currents were smaller than GL ones. The GL drive currents were about 8 times of the GF ones, according to Figure 3.2. Therefore the differences of drive currents could not be ignored for GF devices. The leakage currents in gate layer of the device without LaO capping layer was the highest one, as well as the other ones decreased with capping layer increased due to the thicker dielectric thickness. Figure 3.7 shows the I-V curves of the gate first PMOS devices. For the normalized IDVD curves, VG was set as (Vt – 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. They revealed the same trend to NMOS. The threshold voltages of the devices with various thicknesses of capping layer were different which were shown in Figure 3.8. The oxygen in the gate dielectric would be pulled into the capping layer, which caused the more oxygen vacancies in the gate dielectric. Therefore, the threshold voltage would decrease while the thickness of the capping layer increased. That effect was obvious for the devices with the LaO deposition than the AlO ones.. 20.

(32) 3.2.2 C-V Figure 3.9 shows the capacitance versus voltage curves of the GL devices. In order to eliminate the effect of flat-band voltage, the normalized C-V curves were shown in Figure 3.10. The flat-band voltages both of the NMOS and PMOS devices without PMA condition were the smallest. The normalized C-V curves both of the NMOS and PMOS devices were almost overlapped, which means the Dit of the devices would not vary a lot with various PMA conditions. Figure 3.11 shows the C-V curves of the GF devices, and the normalized C-V curves of the ones were shown in Figure 3.12. They almost revealed the same trend to the GL devices, but the slopes of the curves in accumulation region were different. All the C-V curves were measured with 1MHz frequency.. 3.2.3 Charge Pumping Figure 3.13 shows the charge pumping curves of the gate first devices. The Dit of the PMOS devices was higher than NMOS ones. Comparing to the normalized C-V curves shown in Figure 3.12, the slope of the accumulation region of the C-V curves would correspond to the Dit of the Charge Pumping. The Dit of the GF devices would change with various deposition thicknesses. The thicker capping layer would induce much Dit in gate dielectric, because more cycles of deposition would induce more oxygen to release from high-k dielectric and thus result in more oxygen vacancies, which would cause flat-band voltage shift. Thus there was the larger threshold voltage shift with much Dit in gate dielectric. The Dit of the GL devices would not vary a lot according to the accumulation region of the C-V curves shown in Figure 3.10.. 3.3 Summary For GL devices, the drive currents of the devices with various PMA conditions would not vary a lot. They were almost the same. The other side, the leakage currents and GIDL would be decreased by PMA post treatments. The threshold voltages of the devices with various PMA conditions were related to the Dit and the oxygen vacancies in the gate dielectric. These results are both of NMOS and PMOS. 21.

(33) For GF devices, the drive currents of the devices with various thicknesses of capping layer were different. The other side, the leakage currents would be decreased by the capping layer. The threshold voltages of the devices with various thicknesses of capping layer were related to the Dit and the oxygen vacancies in the gate dielectric. The thicker capping layer would induce much Dit in gate dielectric, thus there was the larger threshold voltage shift. With the deposition of the capping layer, the oxygen in the gate dielectric would be pulled into the capping layer, which caused more oxygen vacancies in the gate dielectric. Therefore, the threshold voltage would decrease while the thickness of the capping layer increased. That effect was obvious for the devices with the LaO deposition than the AlO ones. The flat-band voltages both of the NMOS and PMOS devices without PMA condition were the smallest. The normalized C-V curves both of the NMOS and PMOS devices were almost overlapped, which means the Dit of the devices would not vary a lot with various PMA conditions. The C-V curves of the GF devices almost revealed the same trend to the GL devices, but the slopes of the curves in accumulation region were different. The Dit of the GF devices would change with various deposition thicknesses. The thicker capping layer would induce much Dit in gate dielectric, because more cycles of deposition would induce more oxygen to release from high-k dielectric and thus result in more oxygen vacancies, which would cause flat-band voltage shift. Thus there was the larger threshold voltage shift with much Dit in gate dielectric. Besides, The Dit of the GL devices would not vary a lot according to the accumulation region of the C-V curves.. 22.

(34) Table 3.1 Various factors of the 12 inch wafers. Various factors of the 12 inch wafers Without Post Metallization Annealing Condition With 400oC Annealing and Oxygen Post Treatment. Gate. With 400oC Annealing and Nitrogen Post Treatment. Last With 450oC Annealing and Oxygen Post Treatment With 450oC Annealing and Nitrogen Post Treatment Without Lanthanum Oxide Post Treatment. LaO. With Lanthanum Oxide 15C Post Treatment. Gate. With Lanthanum Oxide 30C Post Treatment. First. Without Aluminum Oxide Post Treatment. AlO. With Aluminum Oxide 6C Post Treatment With Aluminum Oxide 11C Post Treatment. 23.

(35) Table 3.2 Experiment methods and parameters setup. Device Characteristics Vth, Sub-Threshold Swing (SS), ID, Gm. Measured Type ID-VG. Parameter Setup. Drive Current (ID). ID-VD. Leakage Current (IG). IG-VG. Capacitance, Equivalent Oxide Thickness (EOT). C-V. Frequency = 1 MHz VG range depends on the curve shape (Sweeep Mode). ICP, Interface Trap Density (Dit). Charge Pumping. Frequency = 1 MHz Pulse Amplitude = 1.2 V Pulse Period = 1μsec Vbase range depends on the curve shape. Reliability. Constant Voltage Stress. Room Temperature VG = Vstress (Constant Mode) VD = VS = VB = 0 V (Common Mode). VG = -05 ~ 1.5 V (Sweeep Mode) VD = 0.05 ~ 1.5 V (Step Mode) VS = VB = 0 V (Common Mode) (For NMOS. Add minus if PMOS) VG = Vth + 1 V (Constant Mode) VD = 0 ~ 1.5 V (Sweep Mode) VS = VB = 0 V (Common Mode) (For NMOS. Use Vth - 1 or add minus if PMOS) VG = -1.5 ~ 1.5 V (Sweeep Mode) VD = VS = VB = 0 V (Common Mode) (For NMOS. Add minus if PMOS). 24.

(36) Two Metals HK Gate Oxide IL. Source. Drain Silicon Substrate. (a). TiN LaO or AlO HK Gate Oxide IL. Source. Drain Silicon Substrate. (b). Figure 3.1 Structure of the (a) gate last and (b) gate first devices. 25.

(37) 2.0. ID (mA/um). 1.5 1.0. Both NMOS & PMOS Without PMA o With 400 C O2 PMA o. With 400 C N2 PMA. NMOS VG = Vt + 1. W = 10 um L = 1 um. 0.5 0.0. PMOS VG = Vt - 1 -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. 1.5. VD (volts) (a). 0.30 0.25. ID (mA/um). 0.20 0.15 0.10. W = 10 um L = 1 um Without LaO LaO15C LaO30C Without AlO AlO6C AlO11C. NMOS VG = Vt + 1. 0.05 PMOS VG = Vt - 1. 0.00 -0.05. -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. 1.5. VD (volts) (b) Figure 3.2 IDVD curves of the (a) gate last and (b) gate first devices. 26.

(38) 2.0. ID (mA/um). 1.5. NMOS W = 10 um L = 1 um VG = V t + 1. 1.0. No PMA o 400 C O2 PMA. 0.5. 400 C N2 PMA. o o. 450 C O2 PMA o. 450 C N2 PMA. 0.0 0.0. 0.5. 1.0. 1.5. VD (Volts). ID (A/um). (a). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 -2.0. No PMA o 400 C O2 PMA o. 400 C N2 PMA o. 450 C O2 PMA o. 450 C N2 PMA. NMOS W = 10 um L = 1 um -1.5. -1.0. -0.5. 0.0. 0.5. VG - Vt (Volts) (b). 27. 1.0. 1.5.

(39) IG (A). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.0. NMOS W = 10 um L = 1 um. No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA. -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. 1.5. 2.0. VG (V) (c) Figure 3.3 (a) IDVD (b) IDVG and (c) IGVG curves of the gate last NMOS devices with various PMA conditions. 28.

(40) 0.6 PMOS W = 10 um L = 1 um. ID (mA). 0.4. 0.2. V G = Vt - 1 No PMA o 400 C O2 PMA o. 400 C N2 PMA o. 0.0. 450 C O2 PMA o. 450 C N2 PMA -1.5. -1.0. -0.5. 0.0. VD (V). ID (A/um). (a). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 PMOS 1E-11 W = 10 um 1E-12 L = 1 um 1E-13 1E-14 -1.0 -0.5 0.0. No PMA o 400 C O2 PMA o. 400 C N2 PMA o. 450 C O2 PMA o. 450 C N2 PMA. 0.5. 1.0. VG - Vt (Volts) (b). 29. 1.5. 2.0.

(41) IG (A). 1 0.1 PMOS 0.01 W = 10 um 1E-3 L = 1 um 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.0 -1.5 -1.0. No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA. -0.5. 0.0. 0.5. 1.0. 1.5. 2.0. VG (V) (c) Figure 3.4 (a) IDVD (b) IDVG and (c) IGVG curves of the gate last PMOS devices with various PMA conditions. 30.

(42) 1.0 0.9. NMOS W=10um L=1um. Vt (volts). 0.8 0.7 0.6 0.5 0.4 0.3. Without PMA. 400C 400C 450C Nitrogen Nitrogen Oxygen PMA PMA PMA. 450C Oxygen PMA. (a). -0.6 -0.7. PMOS W=10um L=1um. Vt (volts). -0.8 -0.9 -1.0 -1.1 -1.2 -1.3 Without PMA. 400C 400C 450C Nitrogen Nitrogen Oxygen PMA PMA PMA. 450C Oxygen PMA. (b) Figure 3.5 The threshold voltages both of the gate last (a) NMOS and (b) PMOS devices. 31.

(43) 0.4. ID (mA/um). 0.3. No LaO LaO15C LaO30C. NMOS W = 10 um L = 1 um VG = Vt + 1. 0.2. 0.1. 0.0 0.0. 0.5. 1.0. 1.5. VD (Volts). ID (A/um). (a). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15. No LaO LaO15C LaO30C. NMOS W = 10 um L = 1 um -1.5. -1.0. -0.5. 0.0. 0.5. VG - Vt (Volts) (b). 32. 1.0. 1.5. 2.0.

(44) IG (A). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.0. NMOS W = 10 um L = 1 um. No LaO LaO15C LaO30C. -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. 1.5. 2.0. VG (Volts) (c) Figure 3.6 (a) IDVD (b) IDVG and (c) IGVG curves of the gate first NMOS devices with various thicknesses of capping layer. 33.

(45) ID (mA/um). 0.06. No AlO AlO6C AlO11C. PMOS W = 10 um L = 1 um VG = Vt - 1. 0.04. 0.02. 0.00 -1.5. -1.0. -0.5. 0.0. VD (Volts). ID (A/um). (a). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 PMOS 1E-12 W = 10 um 1E-13 L = 1 um 1E-14 1E-15 -1.5 -1.0 -0.5. No AlO AlO6C AlO11C. 0.0. 0.5. VG - Vt (Volts) (b). 34. 1.0. 1.5.

(46) IG (A). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.0. No AlO AlO6C AlO11C. PMOS W = 10 um L = 1 um. -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. 1.5. 2.0. VG (Volts) (c) Figure 3.7 (a) IDVD (b) IDVG and (c) IGVG curves of the gate first PMOS devices with various thicknesses of capping layer. 35.

(47) 0.7 NMOS W=10um L=1um. 0.6. Vt (volts). 0.5 0.4 0.3 0.2 0.1 0.0 Without LaO. LaO15C. LaO30C. (a). -0.3 PMOS W=10um L=1um. Vt (volts). -0.4. -0.5. -0.6. -0.7 Without AlO. AlO6C. AlO11C. (b) Figure 3.8 The threshold voltages both of the gate first (a) NMOS and (b) PMOS devices. 36.

(48) No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA. 2.0. C (pF). 1.5. NMOS W = 10 um L = 1 um. 1.0. 0.5. 0.0. f = 1MHz -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. 1.5. VG (Volts) (a). 400C O2 PMA 400C N2 PMA No PMA. 2.0. 450C O2 PMA 450C N2 PMA. C (pF). 1.5. 1.0 PMOS W = 10 um L = 1 um. 0.5. f = 1MHz 0.0 -2.0. -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. 1.5. VG (Volts) (b) Figure 3.9 C-V curves of the gate last (a) NMOS and (b) PMOS devices with various PMA conditions. 37.

(49) No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA. 2.0. C (pF). 1.5. NMOS W = 10 um L = 1 um. 1.0. 0.5. f = 1MHz. 0.0 -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. 1.5. 2.0. VG-VFB (Volts) (a). 400C O2 PMA 400C N2 PMA No PMA. 2.0. 450C O2 PMA 450C N2 PMA. C (pF). 1.5. 1.0 PMOS W = 10 um L = 1 um. 0.5. f = 1MHz 0.0. -2.0. -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. 1.5. VG-VFB (Volts) (b) Figure 3.10 Normalized C-V curves of the gate last (a) NMOS and (b) PMOS devices with various PMA conditions. 38.

(50) 3.0 2.5. No LaO LaO15C LaO30C. NMOS W = 10 um L = 1 um. C (pF). 2.0 1.5 1.0 0.5 0.0. f = 1MHz. -2.5 -2.0 -1.5 -1.0 -0.5 0.0. 0.5. 1.0. 1.5. 2.0. VG (Volts) (a). 3.0 2.5. No ALO AlO6C AlO11C. PMOS W = 10 um L = 1 um. C (pF). 2.0 1.5 1.0 0.5 0.0. f = 1MHz. -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5. V (Volts) (b) Figure 3.11 C-V curves of the gate first (a) NMOS and (b) PMOS devices with various thicknesses of capping layer. 39.

(51) 3.0 2.5. No LaO LaO15C LaO30C. NMOS W = 10 um L = 1 um. C (pF). 2.0 1.5 1.0 0.5 0.0. f = 1MHz. -1.5 -1.0 -0.5 0.0. 0.5. 1.0. 1.5. 2.0. 2.5. VG-VFB (Volts) (a). 3.0 2.5. No ALO AlO6C AlO11C. PMOS W = 10 um L = 1 um. C (pF). 2.0 1.5 1.0 0.5 0.0. f = 1MHz. -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5. VG-VFB (Volts) (b) Figure 3.12 Normalized C-V curves of the gate first (a) NMOS and (b) PMOS devices with various thicknesses of capping layer 40.

(52) NMOS W = 10 um L = 1 um. No LaO LaO15C LaO30C. 0.20. ICP (uA). 0.15. f = 1MHz. 0.10 0.05 0.00. -0.05. -2.0. -1.5. -1.0. -0.5. 0.0. 0.5. V (Volts) (a). PMOS W = 10 um L = 1 um. No ALO AlO6C AlO11C. 0.20. ICP (uA). 0.15. f = 1MHz. 0.10 0.05 0.00. -0.05 -2.0. -1.5. -1.0. -0.5. 0.0. 0.5. V (Volts) (b) Figure 3.13 ICP curves of the gate first (a) NMOS and (b) PMOS devices with various thicknesses of capping layer. 41.

(53) Chapter 4 Reliability of High-k/Metal Gate Devices with Various Post Treatments. 4.1 Methods of the Measured Work After the basic measured work, stress steps could be executed. The stress step should be executed after the other measured steps to realize the reliability of the samples. The stress treatment would cause more defects thus increase the leakage current, and the device was not in fresh condition anymore. The setup of the stress measurements were shown earlier in Table 3.2. In order to extract the reliability of the devices, stress steps were added among every time I-V measuring. If necessary, C-V and Charge Pumping measuring could be added in the same condition. The way of stress is providing a constant voltage for gate terminal while the other terminals were grounded. The constant voltage was chosen from Vth and then added a constant value, like 1 or 1.5 V. That voltage was higher than used to be applied for basic characteristics measuring. During a stress, ICS auto-measurement would extract I-V every period. That data was useful to realize the variation of the device. In this work, at first, a device would be measured for basic characteristics in fresh condition, and then it was provided with five time stresses. After every time stress, the device would be measured for basic characteristics again. In addition, more precise details were shown in Table 4.1. The purpose of the stress was that used to realize the degradation during the stress process. Higher gate voltage would induce more defects and accelerate destruction of the device. This degradation could be taken to determine and estimate the extent of destruction that a device could resist, and how long the device could be used.. 42.

(54) 4.2 Experimental Results and Discussion In this section, it was focused on the results of gate last devices. According to Chapter 3, these 12 inch wafers of GL process were manufactured with various post metallization annealing (PMA) treatments. The PMA treatments were fabricated with oxygen or nitrogen, and the annealing temperatures were 400oC or 450oC, respectively. These factors constituted various treatments of the PMA conditions.. 4.2.1 Reliability of the Gate Last Devices For the GL devices with various PMA conditions, Figure 4.1 shows the IDVD curves after stress treatments for the NMOS devices, as well as the IDVG curves and the IGVG curves were shown in Figure 4.2 and Figure 4.3. The constant voltage stress which applied to the devices was Vt + 1.5 V. It was found that there was the degradation of the drive currents after the stress work. The best reliability of all samples was the devices with oxygen treatments, and the worst one was the devices with nitrogen treatments. The reason might that the bonding energy between silicon and oxygen would be stronger than the silicon and nitrogen one in the gate dielectric, thus the bonding with nitrogen would be easier to be broken than the oxygen one and then produced more traps in the gate dielectric, even more than the one without PMA condition. Besides, it was found that the stressing effect of the devices with oxygen treatments would be sensitive to the annealing temperature. According to Figure 4.2 and Figure 4.3, the threshold voltages of the devices with nitrogen treatments and without PMA condition were shift after the stresses, while the one with oxygen treatments was not varied a lot. The degradation of Dit and the bulk traps of the device with PMA conditions were reduced. Figure 4.4 shows the ID degradation and the Vt variation of these gate last NMOS devices. It was found that the devices with the oxygen treatments would be improved the most. For the PMOS ones of GL, Figure 4.5 shows the IDVD curves of the PMOS devices after stress treatments, while the IDVG and the IGVG curves were shown in Figure 4.6 and Figure 4.7. The constant voltage stress which applied to the devices was Vt - 1.2 V. The drive currents degradation of the devices with PMA conditions was reduced. The degradation of Dit and the bulk traps of the devices with PMA conditions were also reduced. Figure 4.8 shows the ID degradation and the Vt variation of these gate last PMOS devices. The improvement of the devices with the oxygen treatments was still the best 43.

(55) one. As the above-mentioned, ID degradation and the Vt variation were used to determine the reliability of the devices. To compare with the results of which were shown in Figure 4.4 and Figure 4.8, there were the other four stress voltages with the same operation steps. For NMOS, there were the results with Vt + 2 V and Vt + 1.2 V shown in Figure 4.9 and Figure 4.10, respectively. For PMOS, there were the results with Vt - 1 V and Vt – 0.7 V shown in Figure 4.11 and Figure 4.12, respectively. Therefore, the stress results both of NMOS and PMOS were shown with three various stress voltage, respectively. According to Figure 3.2, it was found that the drain currents of NMOS would be higher than the ones of PMOS. Thus, the three stress voltages of the PMOS were not as high as the NMOS to avoid the devices breakdown. Figure 4.13 shows the Vt shift of the GL devices after the various constant voltage stresses. Both NMOS and PMOS results were shown with three stress voltages. It was found that the threshold voltage of the device with the oxygen treatments was the highest than the other ones. The reason might that the oxygen vacancies in the gate dielectric were filled up with the oxygen treatments. That effect was not obvious for the nitrogen treatments. Thus the threshold voltage of the devices with the oxygen treatments was highest and with the least variation after the stress. Besides, the stressing effects of the devices with oxygen treatments were sensitive to the annealing temperature, as well as the nitrogen ones were not sensitive so much. The threshold voltage variations of the NMOS devices were larger than the ones of the PMOS devices. Especially the threshold voltage variation of the NMOS device with nitrogen treatments was the largest one. The weaker bonding energy between silicon and nitrogen caused that the bond with nitrogen would be easier to be broken than the oxygen one. Thus there were more traps in the gate dielectric with the nitrogen treatment than the oxygen one. Those traps would capture the carriers, and thus the threshold voltage variation of the NMOS device with nitrogen treatments would be the largest one. Finally, the results of the ID degradation and the Vt variation with the three stress voltage were compared together. They were shown in Figure 4.14 and Figure 4.15 for NMOS and PMOS, respectively. The results were based on logarithmic y-axis and they were shown within linear trend. It was matched that the higher stress voltage would induce the much ID degradation and Vt variation.. 44.

(56) 4.3 Summary It was found that there was the degradation of the drive currents after the stress work. For NMOS, The best reliability of all samples was the devices with oxygen treatments, and the worst one was the devices with nitrogen treatments, even worse than the one without PMA condition. In other side, for PMOS, the devices with nitrogen treatments were batter than the one without PMA condition, and not worse than the oxygen ones so much. The reason might that the carriers in NMOS and PMOS devices are electrons and holes, respectively. The mass and the mobility of electrons and holes are different, thus the transmitted principle of them were different and caused different results. Besides, the same constant voltage might induce different degradation to NMOS and PMOS. That would also cause different results. As the above-mentioned, the devices with the oxygen treatments would be improved the most both of NMOS and PMOS. The degradation of drive currents, Dit and the bulk traps of the devices with the oxygen treatments were reduced. Furthermore, the bonding energy between silicon and oxygen would be stronger than the silicon and nitrogen one in the gate dielectric, thus the bonding with nitrogen would be easier to be broken than the oxygen one and then produced more traps in the gate dielectric, even more than the one without PMA condition for NMOS. Besides, it was found that the stressing effect of the devices with oxygen treatments would be sensitive to the annealing temperature. While the annealing temperature was increased, the threshold voltage would increase obviously. It was found that the threshold voltages of the devices with nitrogen treatments and without PMA condition were shift after the stresses, while the one with oxygen treatments was not varied a lot. The threshold voltage of the device with the oxygen treatments was the highest than the other ones. The reason might that the oxygen vacancies in the gate dielectric were filled up with the oxygen treatments. That effect was not obvious for the nitrogen treatments. Thus the threshold voltage of the devices with the oxygen treatments was highest and with the least variation after the stress. Besides, the stressing effects of the devices with oxygen treatments were sensitive to the annealing temperature, as well as the nitrogen ones were not sensitive so much. The threshold voltage variations of the NMOS devices were larger than the ones of the PMOS devices. Especially the threshold voltage variation of the NMOS device with 45.

(57) nitrogen treatments was the largest one. The weaker bonding energy between silicon and nitrogen induced that the bond with nitrogen would be easier to be broken than the oxygen one. Thus there were more traps in the gate dielectric with the nitrogen treatment than the oxygen one. Those traps would capture the carriers, and thus the threshold voltage variation of the NMOS device with nitrogen treatments would be the largest one. It was matched that the best reliability of all samples was the devices with oxygen treatments, and the higher stress voltage would cause the much ID degradation and Vt variation. Eventually, Figure 4.16 shows the energy bands of various states, which were accumulation, depletion and weak inversion, strong inversion before tunneling occurs and tunneling Occurs. They were matched to the above-mentioned results.. 46.

(58) Table 4.1 Stress experiment setting flow chart. Start. Measure ID-VG, ID-VD and IG-VG at room temperature and fresh condition. If necessary, measure Charge Pumping and C-V at the same condition, and also does the following steps. Stress condition setting. ICS auto-measurement. Measure ID-VG, ID-VD and IG-VG after every time stress. Whether all stress measurements are accomplished. No. Yes After all stress measurements are accomplished, measure final time ID-VG, ID-VD and IG-VG. Finish. 47.

(59) 2.0. ID (mA/um). 1.5. NMOS W: 10 um L: 1 um. No PMA. 1.0 Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.5 VG = Vt + 1 0.0. Vstress= Vt+1.5 V 0.0. 0.5. 1.0. 1.5. VD (Volts) (a). 2.0. NMOS W: 10 um L: 1 um. o. 400 C O2 PMA. ID (mA/um). 1.5 1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.5 V G = Vt + 1 0.0. Vstress= Vt+1.5 V 0.0. 0.5. 1.0. VD (Volts) (b). 48. 1.5.

(60) 2.0. NMOS W: 10 um L: 1 um. o. 400 C N2 PMA. ID (mA/um). 1.5 1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.5 VG = V t + 1 0.0. Vstress= Vt+1.5 V 0.0. 0.5. 1.0. 1.5. VD (Volts) (c). 2.0. ID (mA/um). 1.5. NMOS W: 10 um L: 1 um. o. 450 C O2 PMA. 1.0 Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.5 VG = Vt + 1. 0.0. Vstress= Vt+1.5 V 0.0. 0.5. 1.0. VD (Volts) (d). 49. 1.5.

(61) 2.0. NMOS W: 10 um L: 1 um. o. 450 C N2 PMA. ID (mA/um). 1.5 1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.5 VG = Vt + 1 0.0. Vstress= Vt+1.5 V 0.0. 0.5. 1.0. 1.5. VD (Volts) (e) Figure 4.1 IDVD curves of the NMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses. 50.

(62) ID (A/um). 1 0.1 NMOS 0.01 W: 10 um 1E-3 L: 1 um 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -1.0 -0.5. No PMA Vstress= Vt+1.5 V. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress 0.0. 0.5. 1.0. 1.5. 2.0. VG (Volts). ID (A/um). (a). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. NMOS W: 10 um L: 1 um o. 400 C O2 PMA Vstress= Vt+1.5 V -0.5. 0.0. 0.5. 1.0. VG (Volts) (b). 51. 1.5. 2.0.

(63) ID (A/um). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. NMOS W: 10 um L: 1 um o. 400 C N2 PMA Vstress= Vt+1.5 V -0.5. 0.0. 0.5. 1.0. 1.5. 2.0. VG (Volts). ID (A/um). (c). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. NMOS W: 10 um L: 1 um o. 450 C O2 PMA Vstress= Vt+1.5 V -0.5. 0.0. 0.5. 1.0. VG (Volts) (d). 52. 1.5. 2.0.

(64) ID (A/um). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. NMOS W: 10 um L: 1 um o. 450 C N2 PMA Vstress= Vt+1.5 V -0.5. 0.0. 0.5. 1.0. 1.5. 2.0. VG (Volts) (e) Figure 4.2 IDVG curves of the NMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses. 53.

(65) IG (A/um). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.0. NMOS W: 10 um L: 1 um. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. -1.5. -1.0. -0.5. No PMA Vstress= Vt+1.5 V 0.0. 0.5. 1.0. 1.5. 2.0. VG (Volts). IG (A/um). (a). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 NMOS 1E-12 W: 10 um 1E-13 L: 1 um 1E-14 1E-15 -2.0 -1.5 -1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. o. 400 C O2 PMA Vstress= Vt+1.5 V -0.5. 0.0. 0.5. VG (Volts) (b). 54. 1.0. 1.5. 2.0.

(66) IG (A/um). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 NMOS 1E-12 W: 10 um 1E-13 L: 1 um 1E-14 1E-15 -2.0 -1.5 -1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. o. 400 C N2 PMA Vstress= Vt+1.5 V -0.5. 0.0. 0.5. 1.0. 1.5. 2.0. VG (Volts). IG (A/um). (c). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 NMOS 1E-12 W: 10 um 1E-13 L: 1 um 1E-14 1E-15 -2.0 -1.5 -1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. o. 450 C O2 PMA Vstress= Vt+1.5 V -0.5. 0.0. 0.5. VG (Volts) (d). 55. 1.0. 1.5. 2.0.

(67) IG (A/um). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 NMOS 1E-12 W: 10 um 1E-13 L: 1 um 1E-14 1E-15 -2.0 -1.5 -1.0. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. o. 450 C N2 PMA Vstress= Vt+1.5 V -0.5. 0.0. 0.5. 1.0. 1.5. 2.0. VG (Volts) (e) Figure 4.3 IGVG curves of the NMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses. 56.

(68) ID Degradation (%). 20 15. No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA. NMOS W=10um L=1um Vstress= Vt+1.5 V. 10 5 0 0. 5. 10. 15. Stress Time (minutes) (a). 30. Vt variation (%). 25. NMOS W=10um L=1um Vstress= Vt+1.5 V. 20 No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA. 15 10 5 0 0. 5. 10. 15. Stress Time (minutes) (b) Figure 4.4 (a) ID degradation and (b) Vt variation of the gate last NMOS devices after the constant voltage stress which was Vt + 1.5 V. 57.

(69) No PMA. PMOS W: 10 um L: 1 um. ID (mA/um). 0.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.0 -1.5. -1.0. VG = Vt - 1 Vstress= Vt-1.2 V -0.5. 0.0. VD (Volts) (a). 400C O2 PMA. ID (mA/um). 0.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.0 -1.5. -1.0. VG = Vt - 1 Vstress= Vt-1.2 V -0.5. VD (Volts) (b). 58. PMOS W: 10 um L: 1 um. 0.0.

(70) 400C N2 PMA. ID (mA/um). 0.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.0 -1.5. -1.0. PMOS W: 10 um L: 1 um. VG = Vt - 1 Vstress= Vt-1.2 V -0.5. 0.0. VD (Volts) (c). 450C O2 PMA. ID (mA/um). 0.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.0 -1.5. -1.0. VG = Vt - 1 Vstress= Vt-1.2 V -0.5. VD (Volts) (d). 59. PMOS W: 10 um L: 1 um. 0.0.

(71) 450C N2 PMA. ID (mA/um). 0.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. 0.0 -1.5. -1.0. PMOS W: 10 um L: 1 um. VG = Vt - 1 Vstress= Vt-1.2 V -0.5. 0.0. VD (Volts) (e) Figure 4.5 IDVD curves of the PMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses. 60.

(72) ID (A/um). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. PMOS W: 10 um L: 1 um No PMA Vstress= Vt-1.2 V -2.0. -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. VG (Volts). ID (A/um). (a). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. PMOS W: 10 um L: 1 um 400C O2 PMA Vstress= Vt-1.2 V -2.0. -1.5. -1.0. -0.5. VG (Volts) (b). 61. 0.0. 0.5. 1.0.

(73) ID (A/um). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. PMOS W: 10 um L: 1 um 400C N2 PMA Vstress= Vt-1.2 V -2.0. -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. VG (Volts). ID (A/um). (c). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. PMOS W: 10 um L: 1 um 450C O2 PMA Vstress= Vt-1.2 V -2.0. -1.5. -1.0. -0.5. VG (Volts) (d). 62. 0.0. 0.5. 1.0.

(74) ID (A/um). 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -2.5. Fresh After 1st stress After 2nd stress After 3rd stress After 4th stress After 5th stress. PMOS W: 10 um L: 1 um 450C N2 PMA Vstress= Vt-1.2 V -2.0. -1.5. -1.0. -0.5. 0.0. 0.5. 1.0. VG (Volts) (e) Figure 4.6 IDVG curves of the PMOS devices which (a) without PMA, (b) with 400oC O2, (c) with 400oC N2, (d) with 450oC O2 and (e) with 450oC N2 conditions after the stresses. 63.