Principle of Charge Pumping

There is the typical Charge Pumping measured system chart shown in Figure 2.12.

As the figure showing, the source and drain (S/D) of the device are connected together with a variable voltage source. The channel would be conducted while the device is applied to a high voltage pulse and achieves inversion region. Therefore, the charges in the source and drain region could move through the channel, and they are liable to be captured by the traps in the surface.

The channel would return to depletion while the device is applied to a low voltage pulse, and the mobile charge would come back to the S/D terminals. The charges which are captured by the traps could not come back to the S/D region. They would have recombination with the majority carriers from the substrate and then increase the currents in substrate. This phenomenon is called Charge Pumping [10].

By exploring the currents (ICP) from Charge Pumping measurement, Dit and the defect of the device could be estimated.

Figure 2.1 The instruments in the laboratory

Figure 2.2 The 12 inch wafer for the measured experiments

Figure 2.3 Probe Station

Figure 2.4 Agilent HP 4156A (Semiconductor Parameter Analyzer)

Figure 2.5 Agilent HP 4284A (Precision LCR Meter)

Figure 2.6 Agilent HP 81110A (165/330 MHz Pulse/Pattern Generator)

Figure 2.7 Agilent E5250A (Low-leakage Switch Mainframe)

Figure 2.8 Agilent ICS (Interactive Characterization Software)

Figure 2.9 Origin

Figure 2.10 The diagram of SILC [6]

Figure 2.11 The diagram of HCE [8]

Figure 2.12 The typical Charge Pumping measured system chart [10]

Chapter 3

Basic Characteristics of High-k/Metal Gate Devices with Various Post Treatments

3.1 About the Experiments Working

As the beginning for the experiments, it is necessary to realize the composition of the devices. Various post treatments induced various structures and measured results for the devices. In order to work the experiments successfully, the setting for the software is very important. The following are comments about both devices forming and software setting.

3.1.1 The Wafers for the Measured Work

The devices which based on GL and GF process were both measured in the experimental work. For these 12 inch wafers, it were focused on results of the gate last process, and then compared to results of the gate first process.

For GL process, these 12 inch wafers were manufactured with various post metallization annealing (PMA) treatments. The PMA treatments were fabricated with oxygen or nitrogen, and the annealing temperatures were 400^oC or 450^oC, respectively.

These factors constituted various treatments of the PMA conditions. First, there was a wafer without any post metallization annealing. Second, there was a wafer with 400^oC annealing and oxygen post treatment, and another one with nitrogen post treatments at the same annealing temperature. Third, there was a wafer with 450^oC annealing and oxygen post treatment, and another one with nitrogen post treatment at the same temperature, respectively.

For GF process, those 12 inch wafers were manufactured with the capping layer of the lanthanum oxide (LaO) and aluminum oxide (AlO) for NMOS and PMOS, respectively. The various cycles of deposition would cause various thicknesses of the

would induce much Dit in gate dielectric, thus there was the larger threshold voltage shift. Titanium nitride (TiN) was used as the gate electrodes for both GL and GF process devices.

These various factors of the 12 inch wafers were listed in Table 3.1, and the simple structure both of the GL and GF devices were shown in Figure 3.1.

3.1.2 Setting for ICS

After the preparation for the instruments which were mentioned in chapter 2, ICS used to measure I-V, C-V, and Charge Pumping. For I-V measuring, the terminals of source and body would be grounded. Gate and drain would be provided with the voltage in sweep mode or step mode. The mode selecting depends on IDVG or IDVD measuring.

C-V and Charge Pumping settings were similar to I-V, and both of their VG range selecting depends on the curve shape. The frequency would also affect the curves.

To describe accurately, the detailed setting appeared in Table 3.2. It also shows the stress details for reliability which will be discussed in chapter 4.

3.2 Experimental Results and Discussion

It was found that the characteristics of nMOSFETs and pMOSFETs were not symmetrical. Figure 3.2 shows the IDVD curves both of GL and GF devices. No matter GL or GF devices, the currents of PMOS were smaller than NMOS ones. The key factor was that the carrier of NMOS devices was electron, and the carrier of PMOS was holes.

Their operational principles were different. Therefore, the results of NMOS and PMOS should be discussed respectively. The experimental results would be discussed later.

3.2.1 I-V

Currents versus voltage curves of the gate last NMOS devices were shown in Figure 3.3. For the normalized IDVD curves, VG was set as (Vt + 1), while the IDVG curves were normalized with (V – V) at x-axis. The purpose was eliminating the effect of threshold

PMA condition would be highest than the others according to the figure of normalized IDVG curves. The leakage currents in gate layer would reveal the same trend according to the figure of IGVG curves. The gate leakage currents of the device without PMA condition would be also the highest one.

Figure 3.4 shows the I-V curves of the gate last PMOS devices. For the normalized IDVD curves, VG was set as (Vt – 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. They revealed the same trend to NOMS. The drain currents at saturation region with various post treatments were almost the same. The gate leakage currents of the device without PMA condition would be the highest one. It was found that the gate leakage currents would be decreased by PMA post treatments.

The threshold voltages of the devices with various PMA conditions were different shown in Figure 3.5. It was related to the Dit and the oxygen vacancies in the gate dielectric. They would be discussed later in chapter 4.

I-V curves of the gate first NMOS devices were shown in Figure 3.6. For the normalized IDVD curves, VG was set as (Vt + 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. The purpose was eliminating the effect of threshold voltage. The IDVD curves with various thicknesses of capping layer were different. The differences of the drain currents at saturation region were under 0.1 mA, but the GF drive currents were smaller than GL ones. The GL drive currents were about 8 times of the GF ones, according to Figure 3.2. Therefore the differences of drive currents could not be ignored for GF devices. The leakage currents in gate layer of the device without LaO capping layer was the highest one, as well as the other ones decreased with capping layer increased due to the thicker dielectric thickness. Figure 3.7 shows the I-V curves of the gate first PMOS devices. For the normalized IDVD curves, VG was set as (Vt – 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. They revealed the same trend to NMOS.

The threshold voltages of the devices with various thicknesses of capping layer were different which were shown in Figure 3.8. The oxygen in the gate dielectric would be pulled into the capping layer, which caused the more oxygen vacancies in the gate dielectric. Therefore, the threshold voltage would decrease while the thickness of the

3.2.2 C-V

Figure 3.9 shows the capacitance versus voltage curves of the GL devices. In order to eliminate the effect of flat-band voltage, the normalized C-V curves were shown in Figure 3.10. The flat-band voltages both of the NMOS and PMOS devices without PMA condition were the smallest. The normalized C-V curves both of the NMOS and PMOS devices were almost overlapped, which means the Dit of the devices would not vary a lot with various PMA conditions.

Figure 3.11 shows the C-V curves of the GF devices, and the normalized C-V curves of the ones were shown in Figure 3.12. They almost revealed the same trend to the GL devices, but the slopes of the curves in accumulation region were different. All the C-V curves were measured with 1MHz frequency.

3.2.3 Charge Pumping

Figure 3.13 shows the charge pumping curves of the gate first devices. The Dit of the PMOS devices was higher than NMOS ones. Comparing to the normalized C-V curves shown in Figure 3.12, the slope of the accumulation region of the C-V curves would correspond to the Dit of the Charge Pumping.

The Dit of the GF devices would change with various deposition thicknesses. The thicker capping layer would induce much Dit in gate dielectric, because more cycles of deposition would induce more oxygen to release from high-k dielectric and thus result in more oxygen vacancies, which would cause flat-band voltage shift. Thus there was the larger threshold voltage shift with much Dit in gate dielectric.

The Dit of the GL devices would not vary a lot according to the accumulation region of the C-V curves shown in Figure 3.10.

3.3 Summary

For GL devices, the drive currents of the devices with various PMA conditions would not vary a lot. They were almost the same. The other side, the leakage currents and

For GF devices, the drive currents of the devices with various thicknesses of capping layer were different. The other side, the leakage currents would be decreased by the capping layer. The threshold voltages of the devices with various thicknesses of capping layer were related to the Dit and the oxygen vacancies in the gate dielectric. The thicker capping layer would induce much Dit in gate dielectric, thus there was the larger threshold voltage shift. With the deposition of the capping layer, the oxygen in the gate dielectric would be pulled into the capping layer, which caused more oxygen vacancies in the gate dielectric. Therefore, the threshold voltage would decrease while the thickness of the capping layer increased. That effect was obvious for the devices with the LaO deposition than the AlO ones.

The flat-band voltages both of the NMOS and PMOS devices without PMA condition were the smallest. The normalized C-V curves both of the NMOS and PMOS devices were almost overlapped, which means the Dit of the devices would not vary a lot with various PMA conditions. The C-V curves of the GF devices almost revealed the same trend to the GL devices, but the slopes of the curves in accumulation region were different.

The Dit of the GF devices would change with various deposition thicknesses. The thicker capping layer would induce much Dit in gate dielectric, because more cycles of deposition would induce more oxygen to release from high-k dielectric and thus result in more oxygen vacancies, which would cause flat-band voltage shift. Thus there was the larger threshold voltage shift with much Dit in gate dielectric. Besides, The Dit of the GL devices would not vary a lot according to the accumulation region of the C-V curves.

Table 3.1 Various factors of the 12 inch wafers

Various factors of the 12 inch wafers

Without Post Metallization Annealing Condition

With 400^oC Annealing and Oxygen Post Treatment

With 400^oC Annealing and Nitrogen Post Treatment

With 450^oC Annealing and Oxygen Post Treatment

Gate Last

With 450^oC Annealing and Nitrogen Post Treatment

Without Lanthanum Oxide Post Treatment

With Lanthanum Oxide 15C Post Treatment

LaO

With Lanthanum Oxide 30C Post Treatment

Without Aluminum Oxide Post Treatment

With Aluminum Oxide 6C Post Treatment

Gate First

AlO

With Aluminum Oxide 11C Post Treatment

Table 3.2 Experiment methods and parameters setup

Device

Characteristics

Measured Type

Parameter Setup

Vth, Sub-Threshold

Swing (SS), ID, Gm

ID-VG VG = -05 ~ 1.5 V (Sweeep Mode) VD = 0.05 ~ 1.5 V (Step Mode) VS = VB = 0 V (Common Mode) (For NMOS. Add minus if PMOS) Drive Current (ID) ID-VD VG = Vth + 1 V (Constant Mode) (For NMOS. Add minus if PMOS) Capacitance,

Equivalent Oxide Thickness (EOT)

C-V Frequency = 1 MHz

VG range depends on the curve shape (Sweeep Mode)

ICP, Interface Trap Pulse Period = 1μsec

Vbase range depends on the curve shape Reliability Constant

Voltage Stress

Room Temperature

VG = Vstress (Constant Mode)

VD = VS = VB = 0 V (Common Mode)

(a)

(b)

Figure 3.1 Structure of the (a) gate last and (b) gate first devices

Source Drain

Silicon Substrate IL

Two Metals HK Gate Oxide

Source Drain IL

HK Gate Oxide LaO or AlO

TiN

Silicon Substrate

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Without PMA

With 400^oC O₂ PMA With 400^oC N

2 PMA W = 10 um

L = 1 um

Both NMOS & PMOS

(a)

Without LaO LaO15C LaO30C Without AlO AlO6C AlO11C

W = 10 um L = 1 um

(b)

0.0 0.5 1.0 1.5

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

NMOS W = 10 um L = 1 um

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

I

G

(A )

V

G

(V)

(c)

Figure 3.3 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate last NMOS devices with various PMA conditions

-1.5 -1.0 -0.5 0.0

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

PMOS W = 10 um L = 1 um

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

I

G

(A)

V

G

(V)

(c)

Figure 3.4 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate last PMOS devices with various PMA conditions

0.3

W=10um L=1um

V

t

(vol ts)

W=10um L=1um

V

t

(volts)

(b)

0.0 0.5 1.0 1.5

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

No LaO LaO15C LaO30C

NMOS W = 10 um L = 1 um

I

G

(A )

V

_G

(Volts)

(c)

Figure 3.6 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate first NMOS devices with various thicknesses of capping layer

-1.5 -1.0 -0.5 0.0

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

No AlO AlO6C AlO11C PMOS

W = 10 um L = 1 um

I

G

(A )

V

_G

(Volts)

(c)

Figure 3.7 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate first PMOS devices with various thicknesses of capping layer

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

LaO30C LaO15C

Without LaO

NMOS

W=10um L=1um

V

t

(v olts)

(a)

-0.7 -0.6 -0.5 -0.4 -0.3

AlO11C AlO6C

Without AlO PMOS

W=10um L=1um

V

t

(vo lts)

(b)

Figure 3.8 The threshold voltages both of the gate first

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0

0.5 1.0 1.5 2.0

f = 1MHz NMOS

W = 10 um L = 1 um

V

G

(Volts)

C (pF)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(a)

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0

0.5 1.0 1.5 2.0

f = 1MHz PMOS W = 10 um L = 1 um

V

G

(Volts)

C (pF)

400C O2 PMA 450C O2 PMA 400C N2 PMA 450C N2 PMA

No PMA

(b)

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0.0

0.5 1.0 1.5 2.0

f = 1MHz NMOS

W = 10 um L = 1 um

V

G

-V

FB

(Volts)

C ( pF)

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

(a)

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0

0.5 1.0 1.5 2.0

f = 1MHz PMOS W = 10 um L = 1 um

V

G

-V

FB

(Volts)

C ( pF)

400C O2 PMA 450C O2 PMA 400C N2 PMA 450C N2 PMA

No PMA

(b)

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0.0

0.5 1.0 1.5 2.0 2.5 3.0

f = 1MHz NMOS

W = 10 um L = 1 um

V

G

(Volts)

C ( pF)

No LaO LaO15C LaO30C

(a)

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0

0.5 1.0 1.5 2.0 2.5 3.0

f = 1MHz PMOS

W = 10 um L = 1 um

V (Volts)

C (pF)

No ALO AlO6C AlO11C

(b)

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5

-2.0 -1.5 -1.0 -0.5 0.0 0.5 -0.05

0.00 0.05 0.10 0.15 0.20

f = 1MHz NMOS W = 10 um L = 1 um

V (Volts) I

CP

(uA)

No LaO LaO15C LaO30C

(a)

-2.0 -1.5 -1.0 -0.5 0.0 0.5

-0.05 0.00 0.05 0.10 0.15 0.20

f = 1MHz PMOS W = 10 um L = 1 um

V (Volts) I

CP

(uA)

No ALO AlO6C AlO11C

(b)

Chapter 4

Reliability of High-k/Metal Gate Devices with Various Post Treatments

4.1 Methods of the Measured Work

After the basic measured work, stress steps could be executed. The stress step should be executed after the other measured steps to realize the reliability of the samples.

The stress treatment would cause more defects thus increase the leakage current, and the device was not in fresh condition anymore. The setup of the stress measurements were shown earlier in Table 3.2.

In order to extract the reliability of the devices, stress steps were added among every time I-V measuring. If necessary, C-V and Charge Pumping measuring could be added in the same condition. The way of stress is providing a constant voltage for gate terminal while the other terminals were grounded. The constant voltage was chosen from Vth and then added a constant value, like 1 or 1.5 V. That voltage was higher than used to be applied for basic characteristics measuring.

During a stress, ICS auto-measurement would extract I-V every period. That data was useful to realize the variation of the device. In this work, at first, a device would be measured for basic characteristics in fresh condition, and then it was provided with five time stresses. After every time stress, the device would be measured for basic characteristics again.

In addition, more precise details were shown in Table 4.1. The purpose of the stress was that used to realize the degradation during the stress process. Higher gate voltage would induce more defects and accelerate destruction of the device. This degradation could be taken to determine and estimate the extent of destruction that a device could resist, and how long the device could be used.

4.2 Experimental Results and Discussion

In this section, it was focused on the results of gate last devices. According to Chapter 3, these 12 inch wafers of GL process were manufactured with various post metallization annealing (PMA) treatments. The PMA treatments were fabricated with oxygen or nitrogen, and the annealing temperatures were 400^oC or 450^oC, respectively.

These factors constituted various treatments of the PMA conditions.

4.2.1 Reliability of the Gate Last Devices

For the GL devices with various PMA conditions, Figure 4.1 shows the IDVD curves after stress treatments for the NMOS devices, as well as the IDVG curves and the IGVG

curves were shown in Figure 4.2 and Figure 4.3. The constant voltage stress which applied to the devices was Vt + 1.5 V. It was found that there was the degradation of the drive currents after the stress work. The best reliability of all samples was the devices with oxygen treatments, and the worst one was the devices with nitrogen treatments.

The reason might that the bonding energy between silicon and oxygen would be stronger than the silicon and nitrogen one in the gate dielectric, thus the bonding with nitrogen would be easier to be broken than the oxygen one and then produced more traps in the gate dielectric, even more than the one without PMA condition. Besides, it was found that the stressing effect of the devices with oxygen treatments would be sensitive to the annealing temperature.

According to Figure 4.2 and Figure 4.3, the threshold voltages of the devices with nitrogen treatments and without PMA condition were shift after the stresses, while the one with oxygen treatments was not varied a lot. The degradation of Dit and the bulk traps of the device with PMA conditions were reduced. Figure 4.4 shows the ID degradation and the Vt variation of these gate last NMOS devices. It was found that the devices with the oxygen treatments would be improved the most.

For the PMOS ones of GL, Figure 4.5 shows the IDVD curves of the PMOS devices after stress treatments, while the IDVG and the IGVG curves were shown in Figure 4.6 and Figure 4.7. The constant voltage stress which applied to the devices was Vt - 1.2 V. The drive currents degradation of the devices with PMA conditions was reduced. The

one.

As the above-mentioned, ID degradation and the Vt variation were used to determine the reliability of the devices. To compare with the results of which were shown in Figure 4.4 and Figure 4.8, there were the other four stress voltages with the same operation steps.

For NMOS, there were the results with Vt + 2 V and Vt + 1.2 V shown in Figure 4.9 and Figure 4.10, respectively. For PMOS, there were the results with Vt - 1 V and Vt – 0.7 V shown in Figure 4.11 and Figure 4.12, respectively. Therefore, the stress results both of NMOS and PMOS were shown with three various stress voltage, respectively.

According to Figure 3.2, it was found that the drain currents of NMOS would be higher than the ones of PMOS. Thus, the three stress voltages of the PMOS were not as high as the NMOS to avoid the devices breakdown.

Figure 4.13 shows the Vt shift of the GL devices after the various constant voltage stresses. Both NMOS and PMOS results were shown with three stress voltages. It was found that the threshold voltage of the device with the oxygen treatments was the highest than the other ones. The reason might that the oxygen vacancies in the gate dielectric were filled up with the oxygen treatments. That effect was not obvious for the nitrogen treatments. Thus the threshold voltage of the devices with the oxygen treatments was highest and with the least variation after the stress. Besides, the stressing effects of the devices with oxygen treatments were sensitive to the annealing temperature, as well as the nitrogen ones were not sensitive so much.

The threshold voltage variations of the NMOS devices were larger than the ones of the PMOS devices. Especially the threshold voltage variation of the NMOS device with nitrogen treatments was the largest one. The weaker bonding energy between silicon and nitrogen caused that the bond with nitrogen would be easier to be broken than the oxygen one. Thus there were more traps in the gate dielectric with the nitrogen treatment than the oxygen one. Those traps would capture the carriers, and thus the threshold voltage variation of the NMOS device with nitrogen treatments would be the largest one.

Finally, the results of the ID degradation and the Vt variation with the three stress voltage were compared together. They were shown in Figure 4.14 and Figure 4.15 for NMOS and PMOS, respectively. The results were based on logarithmic y-axis and they

4.3 Summary

It was found that there was the degradation of the drive currents after the stress work. For NMOS, The best reliability of all samples was the devices with oxygen treatments, and the worst one was the devices with nitrogen treatments, even worse than the one without PMA condition. In other side, for PMOS, the devices with nitrogen treatments were batter than the one without PMA condition, and not worse than the oxygen ones so much. The reason might that the carriers in NMOS and PMOS devices are electrons and holes, respectively. The mass and the mobility of electrons and holes are different, thus the transmitted principle of them were different and caused different results.

It was found that there was the degradation of the drive currents after the stress work. For NMOS, The best reliability of all samples was the devices with oxygen treatments, and the worst one was the devices with nitrogen treatments, even worse than the one without PMA condition. In other side, for PMOS, the devices with nitrogen treatments were batter than the one without PMA condition, and not worse than the oxygen ones so much. The reason might that the carriers in NMOS and PMOS devices are electrons and holes, respectively. The mass and the mobility of electrons and holes are different, thus the transmitted principle of them were different and caused different results.

在文檔中 針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討 (頁 21-0)