Chapter 5 Conclusions and Future Work
5.2 Future work
When the fabrication process is beyond 22nm technology node, it is
ther fabrication process instead of the process with high-k/metal gate, because there are more problems coming out, which are difficult to overcome. The fin field-effect transistor (FinFET) is a good idea, which was known early than ten years ago.
For a FinFET structure, the gate is fabricated like a fin. The device could be switched with the two sides of the fin, while the gate length is scaled more and the leakage currents are reduced more. This structure could enhan
y for the channel. For the fabrication process which is under 22nm technology node. Fig 5.1 shows the comparison between the traditional transistor and FinFET.
FinFET would play an important role in future [22].
For example, in 2011, Intel Corporation announced what it called the most radical shift in semiconductor technology in 50 years. The
FET will enable the production of integrated-circuit chips that operate faster with less power. Intel’s 3-D Tri-Gate transistor will be used in 22-nanometer-technology microprocessors slated for high-volume manufacturing by the end of the year [23]. The FinFET structure is shown in Fig 5.2.
Figure 5.1 Comparison with the various structures of the devices [22]
Figure 5.2 Structure of FinFET [23]
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Availa
The Improvement of Reliability of 28nm High-k/Metal Gate Device with Various PMA Conditions
Chi-Yun Cheng1, Wen-Kuan Yeh1, Yi-Lin Yang2, Chia-Wei Hsu3
1 Department of Electrical Engineering, National University of Kaohsiung
2 Department of Electronic Engineering, National Kaohsiung Normal University
3 Institute of Microelectronics, National Cheng Kung University
Abstract
In this work, the oxygen and nitrogen were shown to diffuse through the TiN layer in the high-k/metal gate devices during PMA. Both the oxygen and nitrogen annealing will reduce the gate leakage current without increasing oxide thickness. The threshold voltages of the devices changed with various PMA conditions. The reliability of the devices, especially for the oxygen annealed devices, was improved after PMA treatments.
Introduction
High-k/metal gates are needed to continuous device scaling down. However, threshold voltage instability and performance degradation are important problems for high-k devices [1]. The defect density in the interface of gate stack is the major cause for negative bias temperature instability (NBTI) as well as mobility degradation [1].
Oxygen vacancy is known to play an important role in threshold voltage variations [2] and is a significant defect in the HfO2/Si system [3]. The influence of charge oxygen vacancies introduce a dipole offset between the gate metal and the substrate [4].
Post metallization annealing (PMA) is used to reduce the defects at the interface, such as fixed oxide charges, oxide trapped charges and interface charges [5]. Previous work has demonstrated that oxygen vacancies can be passivated for device with noble metal gate by oxygen diffusion through the gate metal [6]. However, these suffer from high equivalent oxide thickness. In this work, we show that both oxygen and nitrogen can be diffused through thin TiN layer and passivate the oxygen vacancies without increasing the oxide thickness by using PMA with various temperatures. Negative bias instability for pFET is improved, especially for the oxygen annealed one.
Experimental
28nm FET high-k/metal gate was formed on bulk Si.
After interfacial SiO2 layer/high-k and TiN deposition, some of the samples were annealed respectively at 400oC and 450oC in oxygen or nitrogen ambient.
The capacitance-voltage (C-V) curves were measured with an HP4280 precision LCR meter and the current-voltage (I-V) curves with an HP-4156B. After the
Results and Discussions
Figure 1 shows the C-V curves of the samples measured with 1 MHz. The merged C-V curves at low voltage for all samples indicate that there is no extra growth in oxide thickness even after 450oC PMA in O2
ambient. Figure 2 shows the IG-VG curves for all samples.
It could be found that the sample without PMA shows an obviously huge gate leakage current than other samples.
On the other hand, the gate leakage current reduced after PMA in all conditions. The reduction of gate leakage current is because of the defects passivation in high-k/Si interface [7].
Figure 3 shows the variation of threshold voltage after various PMA conditions. It could be observed that the no annealing device shows the most negative threshold voltage due to the existence of charged oxygen vacancy, and the threshold voltage shifts positive ward after PMA treatment. Both the threshold voltages are similar with various annealing temperature for the nitrogen annealed devices. On the other hand, the amount of threshold voltage shift of oxygen annealed device is strongly dependent on the annealing temperature. The positive shift of threshold voltage might be due to the passivation of oxygen vacancies in the interfacial layer (IL) region [6]. It is surprising that both the oxygen and nitrogen could be permeated through the TiN region and reaches the IL region because TiN is commonly used as d diffusion barrier. The phenomenon is suggested to reduce the threshold voltage of pMOSFET for the high performance application.
Figure 4 and Figure 5 show the ID-VG and ID-VD
curves with various PMA conditions which eliminate the effect of threshold voltage. It could be observed that the characteristics of ID of pFET device would not be affected after PMA treatments. In other words, the oxygen vacancies passivation in the IL region would not decrease the ID of the devices. After constant voltage stress, the degradation of ID were measured and shown in Figure 6. It could be observed that the device without PMA shows the most serious ID degradation. On the other hand, the reliability is improved for devices treated with PMA. As comparing with the various PMA conditions, the oxygen annealed devices show the better reliability than the
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
Conclusions 4.0 No PMA
400C O2 PMA
Post metallization annealing was used in this work to improve the performances of the high-k/metal gate pFET devices. The gate leakage current reduced with similar oxide thickness after PMA. On the other hand, the amount of threshold voltage shift would be affected with various PMA conditions, and the reliability would also be improved after PMA.
This work was supported by the National Science Council under contract NSC 99-2221-E-390-037. The authors would also like to thank UMC staffs for their helpful supporting.
Fig.1. Normalized CV curve.
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3267, 2007
Without PMA
With 400C Oxygen PMA With 400C Nitrogen PMA With 450C Oxygen PMA
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“Oxygen Vacancy mobility and diffusion coefficient determined from current measurements in SiO2/HfO2/TiN stacks,” International Conference on Solid State Devices and Materials, pp. 669, 2010.
pMOS 10um-1um With 450C Nitrogen PMA
I
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Nakajima, M. Konno, T. Chikyow, H. Kitajima and T. Arikado, “Oxygen Vacancy Induced Substantial Threshold Voltage Shifts in the Hf-based High-K MISFET with p+poly-Si Gates -A Theoretical Approach,” Jpn. J. Appl. Phys.. Part 2, Vol. 43, PP.
L1413, 2004
Fig.2. IGVG curve of pMOSFET with various PMA condition.
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[6]. E. Cartier, M. Hopstaken, and M. Copel, “Oxygen Passivation of Vacancy Defects in Metal-Nitride Gated HfO2/SiO2/Si Devices,” Appl. Phys. Lett., Vol. 95, PP. 042901, 2009
[7]. C.C.Hong and J.G.Hwu, “Degradation in Metal-Oxide-Semiconductor Structure with Ultrathin Gate Oxide due to External Compressive Stress,” Applied Physics Letters, Vol.79, No.23,
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Without PMA
With 400C Oxygen PMA With 400C Nitrogen PMA With 450C Oxygen PMA With 450C Nitrogen PMA
pMOS
Without PMA
With 400C Oxygen PMA With 400C Nitrogen PMA With 450C Oxygen PMA With 450C Nitrogen PMA
0 5 10 15
0 5 10
Fig.4. Normalized IDVG curve of pMOSFET with various PMA condition.
Fig.5. IDVD curve of pMOSFET with various PMA condition.
Without PMA 400C Oxygen PMA 400C Nitrogen PMA 450C Oxygen PMA 450C Nitrogen PMA
pMOS
W=10um, L=1um NBTI Vstress=VT-1V
I D Degradation (%)
Stress Time (minutes) Fig.6. ID degradation after constant voltage stress.