2-1 Introduction
Recently, mobility enhancements by stress control technologies is emerging as one of the
key elements in scaling of complementary metal-oxide-semiconductor (CMOS) transistors
since it offers increased drive current without the penalty of additional capacitance and gate
current leakage. There are two main approaches for implementing strain on
metal-oxide-semiconductor field-effect-transistors (MOSFETs). One is the substrate biaxial
stress where stress is introduced across the entire substrate [1-5]. When a thin film with a
larger lattice constant (SiGe) is grown on a substrate with smaller lattice constant (Si), the
film retains the in-plane lattice constant of the substrate and a biaxially compressive strain (or
tensile strain under contrary condition) will be generated [6]. However, biaxial tensile stress
using strained Si on relaxed SiGe face a lot of challenges such as misfit and defects, Ge
up-diffusion [7], high cost and modest hole mobility gain at high field because quantization
effect [8-9].
In contrast, the second approach, process-induced uniaxial strain such as shallow-trench
isolation (STI) [10], silicon nitride capping layer [11], silicidation process [12] and embedded
SiGe source/drain (S/D) [13] can offer similar electron mobility enhancement compared with
biaxial strain, while the hole mobility improvement is more significant at high field [7]. For
this reason, although STI-induced strain in the channel region had generally considered a
problem rather than an opportunity in the past, nowadays, STI-induced compressive stress in
the channel has become a key point as device scaled down. Besides, another simple way to
enhance mobility is using a wafer with a specific channel orientation which has smaller
carrier effective mass. The <100>-channel device on (100), whose channel direction is rotated
by 45 degree from the conventional <110>-channel device, had been reported that PMOS
drive current could be improved, with NMOS performance maintained [14].
In this chapter, active-region layout dependence of 65 nm PMOSFET performance with
<110>- and <100>- channel orientations were fully investigated. We have further examined
the fully study of STI-induced strain impacts on the performances of small devices with
<110>- and <100>-channel orientations. For 65 nm PMOSFET, <100>-channel show about
8-15% higher drain current than <110>-channel devices as S/D length increased from 0.21
m to 10
m. Furthermore, higher immunity to boron diffusion and less sensitivity on STI-induced strain in both of channel length and width directions for <100>-channel devices
were also demonstrated.
2-2 Experiment
(100) orientation substrate with <110>- and <100>-notch wafers (Fig. 2-1(a), (b),
respectively), where the wafer notched at different directions with 45 degree-off were used for
experiment splits. CMOS devices were fabricated with state-of-the-art 300 mm wafer foundry
technology [15] which includes super steep retrograde (SSR) indium and arsenic channels,
aggressive poly Si gate control, multi-tilted pocket implants, shallow source/drain extensions,
and deep source/drain with low junction leakage. Implants are followed by spike anneal
process to minimize diffusion.
STI was used for isolation followed by retrograde well formation. After channel
implantation, plasma nitrided gate-oxide with a gate oxide thickness (Tox) of 1.4 nm and
un-doped poly-silicon deposition with N+ gate pre-doping and gate patterning were followed.
After shallow source/drain extensions and pocket implantation, tetraethoxysilane (TEOS)
liner and low-temperature silicon nitride were processed in sequence to form a sidewall spacer.
Modified S/D implants were adopted to improve activation and junction capacitance while
maintaining good SCE. The fabrication of a heavily doped source/drain junction by
implantation was followed by rapid thermal annealing (RTA) and NiSi self-aligned
silicidation. The symbols of layout parameters were also defined in Fig. 2-1(a).
2-3 Results and Discussions
The drive current (Id at Vg = Vd = -1.2 V) improvement ratio of <100>-channel to
conventional <110>-channel with varied channel length devices as a function of S/D length
(La: length from gate edge to STI edge) are shown in Fig. 2-2 (a), (b) for NMOSFET and
PMOSFET, respectively. It is found that NMOS characteristics won’t be deteriorated by using
<100>-channel. There is little difference of drain current between two kinds of NMOSFET
with <110>- and <100>-channel. The drive current ratio of NMOS devices are all smaller
than 4%, in spite of varied gate length and decreased La. This result indicates that
STI-induced stress have no significant impact on performance of NMOSFET devices for both
of conventional <110>- and <100>-channel. It was also reported that there is a slight
difference of drift velocity even between <110> and <111> direction, but that the difference
of saturated velocity becomes still minute with an increase in electric field [16]. In contrast,
for long channel (Lg > 0.24 μm) PMOS devices with La = 10 μm where the STI-induced
stress doesn’t impact the channel region, the drain current ratio of <100>- to <110>-channel is
as high as 24 %. The drive current improvement ratio decreases as channel length scales down
to smaller than 0.24 μm due to velocity saturation. Furthermore, although the drive current
ratio of PMOSFET decreases as La shrinks (higher STI-induces compressive stress), it still
shows about 6 % ~ 10 % improvement for devices with shortest La (0.21 μm), as shown in
Fig. 2-2 (b). Figure 2-3 shows comparisons the current ratio of <100>-channel to
<110>-channel between La = 10 μm and La = 0.21 μm for the devices with varied channel
length for both of NMOSFET and PMOSFET. For NMOSFET devices, there is no significant
difference in current ratio under STI-induced stress as devices length scales down. For
PMOSFET with La = 10 μm, <100>-channel devices show a higher drive current than
<110>-channel devices. Although the drive current improvement of <100>-channel to
<110>-channel drops dramatically as channel length scales down, PMOSFET with
<100>-channel still shows about 16% higher than <110>-channel. But if the channel region
was influenced by STI-induced compressive stress, the current ratio of <100>-channel to
<110>-channel will down to smaller than 10%. This result illustrates that the impact of
STI-induced compressive stress on PMOSFET with <110>-channel was much higher than
that of <100>-channel. Since there is no significant dependence of STI-induced compressive
stress for NMOS devices with these two different channel directions, we’ll focus on the
device characteristics of PMOSFET hereafter.
Figures 2-4(a), (b) depict the characteristics of drain current Id at Vd = -1.2 V and linear
transconductance Gm at Vd = -0.05 V between <110>-channel and <100>-channel of 65 nm
PMOSFET devices with a La =10 μm and 0.21 μm, accordingly. For the case of the La = 10
μm which no STI-induced strain in the channel region, <100>-channel shows a 37% higher
than <110>-channel PMOSFET in Gm. As La shrunk from 10 μm to 0.21 μm, the Gm of
<110>-channel device increases about 11% while <100>-channel devices show the
La-independent characteristics and this results in that the Gm difference between <110>- and
<100>-channel PMOSFET is reduced to only 12%. This means that higher compressive stress
in the channel region from STI edge can enhance hole mobility of <110>-channel PMOSFET
devices. By contract, <100>-channel PMOS is almost free from to the change of STI-induced
local compressive strain in the channel region. Figure 2-5 illustrates the hole band structure
with two different channel directions to explain these different results between <110>- and
<100>-channel PMOSFETs. Figure 2-5(a) depicts the band structure of hole with large La as
no STI-induced strain. Unstrained Si has a lager effective mass of heavy hole in <110> than
<100> direction so that <100>-channel PMOS device has higher hole mobility and so that
higher Gm and drive current than <110>-channel devices. Figure 2-5(b) shows hole band
structure under uniaxial STI-induced compressive strain. This strain not only lift the
degeneracy in the valance band [17-18], but also to change the band shape of the heavy hole
to the “light hole like” in <110> directionc so that this STI-induced uniaxial compressive
stress can improve the performance of <110>-channel PMOSFET, while <100>-channel
device is independent of this stress so that <100> direction keeps almost the same shape under
the local strain.
Figure 2-6 (a) shows an Ion (Id at Vg = Vd = -1.2 V) versus Ioff (Id at Vg = 0 V and Vd = -1.2
V) characteristics of 65 nm PMOSFET with La = 10 μm, it should be noted that Ion of
<100>-channel PMOSFET is approximately 17% larger than that of <110> under the same Ioff
conditions. As La shrunk to 0.21 μm, <100>-channel PMOSFET still shows better current
drive than <110>-devices by 8%, although the drive current of <110>-channel devices are
enhanced by STI-induced compressive stress, as shown in Fig. 2-6 (b). The dependence of
Id_sat on Vth_sat under STI-induced compressive stress for <110>- and <100>-channel devices
are plotted in Fig. 2-7 (a) and Fig. 2-7 (b), respectively. For conventional <110>-channel
PMOSFET, Id_sat of the devices with La = 0.21 μm are higher than that of La = 10 μm ones by
7% at the same Vth_sat condition. In contrast, the Ids of <100>-channel devices are almost
independent of layout dimensions and have higher Id_sat as compared with <110>-channel. In
order to eliminate the effect of Vth_sat variation on performance comparison in La
dependence between <110>- and <100>-channel devices, the overdrive current (Id at the bias
of Vg -Vth = - 0.75 V) of 60 nm PMOSFETs with varied La are shown in Fig. 2-8. Although
<110>-channel PMOSFETs gain an increase of 7% in overdrive current from La = 10 to 0.21
μm, <100>-channel devices still show 11% higher than <110>-channel devices. Furthermore,
for fair comparison on short channel effect, Fig. 2-9 (a), (b) show the Id_sat as a function of
drain-induced-barrier-lowering (DIBL) for the devices with <110>- and <100>-channel,
respectively. Compared with <110>-channel PMOSFET, <100>-channel device shows a less
layout dependence of short channel effect owing to its non-sensitive to STI-induced local
stain. In addition, under the same Id_sat conditions, <100>-channel device also has smaller
DIBL than <110>-channel PMOSFET, this indicates that <100>-channel has higher immunity
in short channel effect. To understand the reason of this result, Fig. 2-10 shows the
comparison of drain (or source) to gate overlap capacitance (Cgd) for <110>- and
<100>-channel devices. <100> direction shows a smaller and tighter distribution of Cgd than
<110>. This is mainly due to the slower boron diffusivity in <100>-channel so that
<100>-channel PMOSFET shows smaller DIBL and better short channel effect.
For comprehending the impact of STI-induced compressive stress from devices width
direction on performance and narrow width effect, Fig. 2-11 (a), (b) show the Id_sat versus
Vth_sat for devices with varied channel width for <110>-channel and <100>-channel,
respectively. It is worth to note that here we used the devices with La =10 μm to eliminate the
effect of the stress from channel length direction. It is obviously that Id_sat of <110>-channel
devices are reduced approximately 20% as channel width scaled down while <100>-channel
devices show no dependence on channel width direction contrarily. This result demonstrates
that STI-induced uniaxial compressive stress from width direction is unfavorable for
<110>-channel PMOSFET although this compressive stress from channel length direction can
enhance the device performance. However, PMOSFET devices with <100>-channel is
non-sensitive to STI-induced strain not only in channel length direction but also in width
direction.
2-4 Summary
We have systematically study the STI-induced strain impacts on the performances of 65 nm
technology PMOSFET with <110>- and <100>-channel directions, respectively. Table 2-1
summarizes the impact of STI-induces uniaxial compressive strain on PMOSFET
performance for both of <110> and <100> channel directions. <100>-channel devices have
smaller DIBL and less layout dependence due to lower boron diffusivity and its non-sensitive
to STI-induced stress, accordingly. Furthermore, as Compared to <110>-channel,
<100>-channel devices show not only higher hole mobility, but also keep the advantage of
free from STI stress in both of channel length and width directions. This offers a very
promising alternative CMOS technology and design window for high performance ULSI.
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Fig. 2-1 (a) scheme of <110>-channel devices and layout parameter definition (b) scheme of
<100>-channel devices. The definition of La is S/D length (the length from gate edge to STI
edge).
Fig. 2-2 Id_sat (Id at Vg = Vd = -1.2V) ratio of <100> to <110> with varied La and channel
length for (a) NMOSFET (b) PMOSFET.
Fig. 2-3 Id_sat (Id at Vg = Vd = -1.2V) ratio of <100> to <110> with La = 10 μm and 0.21μm
for NMOS and PMOS devices.
Fig. 2-4 Id-Vg at Vd = -1.2V and Gm at Vd = -0.05V characteristics of 60 nm PMOS devices
with <110>- and <100>-channel orientations for (a) La = 10 μm (b) La = 0.21 μm
Fig. 2-5 Schemes of hole valence band structures for (a) unstrained Si and (b) Si under
uniaxial compressive stress.
Fig. 2-6 Ion-Ioff characteristics of 60 nm PMOSFETs between <110>- and <100>-channel
orientations for (a) La = 10 μm and (b) La = 0.21 μm
Fig. 2-7 Id_sat dependence Vth_sat at Vd = -1.2V of 60 nm PMOS devices with La = 10 and 0.21
μm for (a) <110>-channel (b) <100>-channel directions.
Fig. 2-8 Constant overdrive current at Vg – Vth = -0.75V of 60 nm PMOSFETs with <110>-
and <100>-channel.
Fig. 2-9 Id_sat versus DIBL of PMOSFET with La = 10 and 0.21 μm for (a) <110>-channel and
(b) <100>-channel devices.
Fig. 2-10 PMOS overlap capacitance cumulative distributions of <110> and <100>- channel
devices.
Fig. 2-11 Id_sat dependence Vth_sat of Lg/La = 1 μm/10 μm PMOS devices with varied channel
widths for (a) <110>-channel and (b) <100>-channel directions.
* Here we assume stress from Z direction is identical for <110> and <100> channel orientations, and use the result in ref. [1]
Table 2-1 summarized table for compressive stress impacts on PMOSFET performance with
<110> and <100> in 3D directions.