5-1 Introduction
As CMOS devices are scaling down aggressively, it has become necessary to identify
alternate high-k gate dielectrics that meet the stringent requirements for low leakage current
and thin equivalent oxide thickness (EOT) [1-5]. High-k dielectrics are especially
advantageous for low-power application and for thickness uniformity control owing to the
thicker physical thickness. Among high-k gate dielectric materials, Hf-based gate dielectric
including HfO2 and Hf-silicate are the attractive materials because it has good device
characteristics and is compatible with the conventional polysilicon gate process [6-9].
However, before Hf-based gate dielectrics being successfully integrated into future
technologies, their reliability characteristics still need to be better identified. Bias temperature
instability (BTI) has been recognized as one of the critical concern in the reliability of modern
CMOS devices. Many of the past BTI researches on the SiO2 dielectric have just focused on
the negative BTI (NBTI) on PMOS devices [10-11], since it impacts more the devices
reliability with respect to positive BTI (PBTI) on NMOS [12]. In conventional SiO2 gate
a reliability concern while PMOS under NBTI stress has a continued reliability issue as the
gate oxide thickness is scaled thinner.
On the contrary, unlike conventional SiO2 gate dielectrics, NMOS positive bias temperature
instability (PBTI) could be a potential scaling limit of CMOS technology with Hf-based gate
dielectrics [13]. Most of the previous studies showed a significant positive threshold voltage
shift for the high-k gate stack under PBTI stressing, which was attributed to the preexisting
traps in the high-k layer or the hole induced oxygen vacancy traps [14-18]. In addition, one of
main issues for high-k gate dielectrics is the charge trapping/de-trapping characteristics during
reliability test. Initial observation of instability was studied through capacitance–voltage (CV)
characteristics in Vfb change and current–voltage (IV) in Vth change. Since electrons can be
trapped and de-trapped in the high-k dielectrics with a minimal residual damage to its atomic
structure, a Vth instability associated with electron trapping/detrapping in high-k layer can
significantly affect the transistor performance [19]. Nevertheless, it also complicates the
evaluation of the effects of stress-induced defect generation phenomenon on the high-k gate
dielectrics, which typically is not an issue in the case of SiO2 dielectrics [20]. In order to
investigate the additional electron trapping effects on top of defect generation, a de-trapping
step has been proposed for studying generation of the electron trapping process and its impact
on high-k device reliability [21]. Recently, the electron de-trapping behavior in the high-k
films has used under specific gate bias conditions identifying charge trapping and relaxation
mechanism [22]. However, the dependence of the dielectric electrical characteristics on the
de-trapping conditions has not been investigated in detail.
In this work, the comparison of trapping/de-trapping effect under PBTI stress test between
NMOSFETs with HfO2 and Hf-silicates (HfSiON) high-k dielectrics has been investigated.
We just primary focus on NMOS devices PBTI here since it is more significant than PMOS
NBTI in the case of Hf-based dielectrics MOSFETs.
5-2 Experiment
NMOS devices were fabricated by state-of-the-art 300 mm wafer foundry technology.
Shallow trench isolation (STI) was performed for devices isolation followed by super-steep
retrograde well formation. The high-K dielectric including HfO2 and Hf-silicate were
deposited by atomic-layer deposition (ALD). Chemical oxide was used as the interfacial layer
unless it is specifically mentioned. The nitridation of HfSiO with Hf/(Hf+Si) ratio of 50% was
carried by NH3 annealing in the ambient. After shallow source/drain extensions and pocket
implantation, tetraethoxysilane (TEOS) liner and low-temperature silicon nitride were
processed in sequence to form a sidewall spacer. Modified S/D implants were adopted to
improve activation and junction capacitance while maintaining good SCE. The fabrication of
a heavily doped source/drain junction by implantation was followed by a rapid thermal
annealing (RTA) of 1000 oC for 5s for S/D activation and thermal stability of HfSiON.
5-3 Results and Discussion 5-3-1 Device performance
Figure 5-1 shows the high-frequency C-V characteristics at 100 kHz for HfO2 and HfSiON
gate dielectrics, respectively. The well C-V characteristics under accumulation, depletion and
inversion regions can be observed in this work for both HfO2 and HfSiON gate dielectrics.
The effective oxide thickness was also extracted from these C-V curves under accumulation
without considering quantum effects. Since the EOT were almost the same (1.3 nm) for HfO2
and HfSiON gate dielectrics as shown in Fig. 5-1, therefore, the reliability test can be
analyzed by biasing the same gate voltage in this work. The effective electron mobility
measured on HfO2 and HfSiON gate dielectrics using split CV method is shown in Fig. 5-2.
The effective mobility was almost the same for both HfO2 and HfSiON gate dielectrics at low
electric field as shown in this figure. However, at a higher field (>1 MV/cm), the mobility of
HfSiON gate dielectrics was large than HfO2 gate dielectrics, we speculate that the Si-O and
Si-N bodings were formed for the HfSiON gate dielectrics resulting in annihilation of oxygen
vacancies to offer mobility enhancement at high electric field. This result indicates that the
HfSiON gate dielectrics can be suitable for high performance application. Besides, the
effective mobility can meet the universal curve well at a higher field for both HfO2 and
HfSiON gate dielectrics as shown in inset of Fig. 5-2.
5-3-2 PBTI degradation for HfO2 and HfSiON gate dielectrics
To understand the mechanism of PBTI in our high-k dielectrics, Fig. 5-3 shows the
threshold voltage degradation (ΔVth ) of HfO2 and HfSiON gate dielectrics under the same
PBTI stress (Vg = +2.5 V) at room temperature. It is worth to note that the HfSiON dielectric
leads to an obvious reduction in ΔVTH under PBTI stress. Figure 5-4 shows the charge
pumping current (ICP) before and after PBTI stressing at +2.5V for HfO2 and HfSiON.
Contrast to ΔVth , the HfO2 gate dielectrics had better HfO2/Si interface due to its less initial
ICP. However, although HfSiON dielectrics had larger initial ICP than HfO2, the increase in ICP
during PBTI stress was almost the same for HfO2 and HfSiON gate dielectrics, as shown in
Fig. 5-5. Furthermore, from the equation of charge pumping current as followed [23]:
ICP = ×q Nit×f (eq. 5-1)
where q is electron charge, and f is measurement frequency. We can extract the number of
interface trap generated during PBTI stress. Figure 5-6 shows the extracted result of Nit
generation for both of HfO2 and HfSiON dielectrics, which is consist with Fig. 5-5. It should
be noted that the Nit increase for both HfO2 and HfSiON dielectrics is quite low (< 2×109
cm-2) in this work.
Furthermore, if we assume that the threshold voltage shift during PBTI stress is only
contributed by generated interface trap ΔNit and generated oxide bulk trap ΔNot, the equation
can by expressed as followed [24]:
th ( it ot
i
V q N
Δ =C × Δ + ΔN ) (eq. 5-2) where q is electron charge, and Ci is inversion capacitance. As eq. 5-2 and the results from
Fig 5-3 to Fig. 5-6, the generated oxide trap (Not) during PBTI stress can be easily extracted in
this work. Figure 5-7 shows the Not increase for both of HfO2 and HfSiON dielectrics during
PBTI stress, respectively. The HfSiON dielectric leads to an obvious reduction in ΔNot during
PBTI stress as compared to HfO2. The ΔNot is larger than 4×1012 cm-2 after 6000s PBTI stress
for HfO2 dielectrics while the ΔNot of HfSiON is smaller than 4×1012 cm-2. This result
demonstrates that the HfSiON thin film quality is better than HfO2. As mentioned previous,
the HfSiON gate dielectrics had the extra Si-O and Si-N bodings resulting in annihilation of
oxygen vacancies, resulting in PBTI reduction for HfSiON dielectrics. On the other hand, it is
worth to note that all these results show the ΔNot is about 2~3 orders larger than ΔNit,
indicating that the generated oxide trap will dominate the PBTI degradation characteristics for
Hf-based gate dielectrics. Thus, the charge trapping model for Hf-based gate dielectrics under
PBTI stress was illustrated in Fig. 5-8. At first, a little electron named as IInterface Trap will
immediately trap in HfO2/Si interface while the positive bias was applied in device. Then, the
most of electrons IBulk Trap will tunnel from Si substrate through the interfacial layer and are
trapped at the bulk oxide, as shown in the schematic energy band diagram. However, there are
still some electrons, which directly through the gate dielectrics named as Itunnel.
5-3-3 Temperature-dependent de-trapping characteristics for HfO2 and HfSiON gate
dielectrics
In this section, the temperature-dependent trapping and de-trapping characteristics for both
of HfO2 and HfSiON were compared. After each biasing stress and sensing cycle, the stress
bias was removed and held up for 0 and100 seconds respectively to examine the electron
de-trapping characteristics.
In Fig. 5-9, we compare the HfO2 and HfSiON gate dielectrics under PBTI stress (Vg =
+2.5 V) with no hold time at different temperatures, including 25, 75 and 100 oC. The ΔVTH
in PBTI stress increasing with increasing measuring temperature for both HfO2 and HfSiON
gate dielectrics. The difference of threshold voltage degradation under PBTI stress between
HfO2 and HfSiON dielectrics is not quite apparent expect for 100 oC. On the other hand, the
obvious improvement in PBTI characteristics was observed for HfSiON gate dielectrics while
the hold time is 100 seconds as indicated in Fig. 5-10. The electron de-trap will result in ΔVTH
reduction in PBTI stress due to less electron being trapped in high-k thin films. This result
indicates that the electron de-trapping will easily happen in HfSiON gate dielectrics. In
generally, the electron will be trapped in gate dielectric of device while positive bias is
applied, and de-trapped while remove the applied bias is removed. In addition, we assume that
the charge de-trapping phenomenon results from some shallow trap in high-k gate dielectrics.
It means that the extra Si-O and Si-N bodings effectively removed the dielectric vacancies to
have a lower trapping cross section and a lower concentration of generated traps, and reduce
some trapping levels. This implies that some deep electron traps were effectively eliminated
for HfSiON gate dielectrics, resulting in the characteristics as shown in Fig. 5-9 and 5-10.
The different hold time (0 & 100 s) under PBTI stress (Vg = +2.5 V) at different
temperatures, including 25, 75 and 100 oC for HfO2 gate dielectrics were shown in Fig. 5-11.
There is almost no difference for ΔVTH in PBTI stress at 25 and 75 oC between 0 and 100 s
hold time as indicated in this figure. However, the ΔVTH in PBTI stress is quite different at
100 oC for HfO2 gate dielectric. The ΔVTH with 0 s hold time is larger than ΔVTH with 100 s
hold time at the high temperature of 100 oC, indicating that the HfO2 gate dielectric generated
deeper charge trap during PBTI stress and trapped electrons need higher thermal energy to
de-trap from HfO2 film. On the other hand, the HfSiON gate dielectric shows the obvious
dependence between ΔVTH and measuring hold time as illustrated in Fig. 5-12. The ΔVTH in
PBTI stress with 0 s hold time is larger than ΔVTH with 100 s hold time at different
temperatures. As we mentioned above, some deep electron traps were effectively eliminated
for HfSiON gate dielectrics, resulting in the characteristics in Fig. 5-12. Figure 5-13 (a), (b)
illustrated the charge trapping/de-trapping models for HfO2 and HfSiON gate dielectrics
under PBTI stress respectively. As compared to HfO2 dielectrics, the HfSiON has deep charge
trapping level under PBTI stress as illustrated in Fig. 5-13(b).
5-4 Summary
In this chapter, the PBTI degradation for HfO2 and HfSiON NMOSFETs with the metal
gate electrode has been successfully demonstrated. The generated oxide trap during PBTI
stress will dominate the PBTI characteristics for Hf-based gate dielectrics. In addition, the
reduction of threshold voltage degradation and oxide trap generation under PBTI stress
indicates that the HfSiON thin film quality is better than HfO2 attributed to HfSiON gate
dielectrics had the extra Si-O and Si-N bodings resulting in annihilation of oxygen vacancies.
On the other hand, the electron trapping/de-trapping effect has been investigated in both HfO2
and HfSiON NMOSFETs correlated with constant voltage stress. As compared to HfO2
dielectrics, the HfSiON has shallower charge trapping level under PBTI stress due to
elimination of deep dielectric vacancies.
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Fig. 5-1 High-frequency C-V characteristics at 100 kHz for NMOSFET with HfO
2 and HfSiON gate dielectrics, respectively.
Fig. 5-2 The effective electron mobility measured on HfO2 and HfSiON gate dielectrics using
split CV method.
Fig. 5-3 Threshold voltage degradation (ΔVth ) of HfO2 and HfSiON gate dielectrics under the
same PBTI stress (Vg = +2.5 V) at room temperature.
Fig. 5-4 Charge pumping current (ICP) before and after PBTI stressing at +2.5V for HfO2 and
HfSiON dielectrics, respectively.
Fig. 5-5 Charging pumping increase (ΔICP) of HfO2 and HfSiON gate dielectrics during the
same PBTI stress bias (Vg = +2.5 V) at room temperature.
Fig. 5-6 Interface trap increase (ΔNit) which extracted from ΔICP of HfO2 and HfSiON gate
dielectrics during the same PBTI stress bias (Vg = +2.5 V) at room temperature.
Fig. 5-7 Generated oxide trap (ΔNot) in the bulk of higk-k film during PBTI stress for both of
HfO2 and HfSiON dielectrics, respectively.
Fig. 5-8 Illustration of electron trapping model for Hf-based gate dielectrics under PBTI stress
Fig. 5-9 Threshold voltage degradation of HfO2 and HfSiON gate dielectrics during PBTI
stress (Vg = +2.5 V) with no hold time at different temperatures, including 25, 75 and 100 oC.
Fig. 5-10 Threshold voltage degradation of HfO2 and HfSiON gate dielectrics during PBTI
stress (Vg = +2.5 V) with hold time 100 s at different temperatures, including 25, 75 and 100
oC.
Fig. 5-11 Comparison of different hold time (0 & 100 s) under PBTI stress (Vg = +2.5 V) at
different temperatures, including 25, 75 and 100 oC for HfO2 gate dielectrics.
Fig. 5-12 Comparison of different hold time (0 & 100 s) under PBTI stress (Vg = +2.5 V) at
different temperatures, including 25, 75 and 100 oC for HfSiON gate dielectrics.
Fig. 5-13 Illustration of the charge trapping/de-trapping models for (a) HfO2 and (b) HfSiON
gate dielectrics under PBTI stress respectively.