先進金氧半場效電晶體閘極工程對改善元件特性及可靠度之研究

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(1)國立交通大學電子工程學系電子研究所. 博士論文. 先進金氧半場效電晶體閘極工程對改善元件特性及可靠度之研究 Gate Engineering of Advanced MOSFETs for Device Performance and Reliability Improvement. 研究生：羅文政指導教授：張俊彥博士趙天生博士. 中華民國九十六年九月 -1-.

(2) 先進金氧半場效電晶體閘極工程對改善元件特性及可靠度之研究 Gate Engineering of Advanced MOSFETs for Device Performance and Reliability Improvement. 研究生：羅文政. Student ：Wen-Cheng Lo. 指導教授：張俊彥博士指導教授：趙天生博士. Advisor ：Dr. Chun-Yen Chang Advisor ：Dr. Tien-Sheng Chao 國立交通大學. 電子工程學系. 電子研究所. 博士論文 A Dissertation Submitted to Department of Electronics Engineering and Institute of Electronics College of Electrical Engineering and Computer Engineering National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electronics Engineering September 2007 Hsinchu, Taiwan, Republic of China. 中華民國九十六年九月 -2-.

(3) 先進金氧半場效電晶體閘極工程對改善元件特性及可靠度之研究研究生：羅文政. 指導教授：張俊彥博士趙天生博士國立交通大學電子工程學系電子研究所摘. 要. 在本論文中，我們針對先進元件的閘極工程整合部分對特性及可靠度的改善進行研究，涵蓋的內容包括淺溝渠隔離(STI)所造成的區域性單向壓縮應力在<110>及<100>通道方向的比較；在(111)晶向基版上利用氮化矽覆蓋層來改善 N 型金氧半場效電晶體的特性；以電漿氮化氧化層或熱氮化氧化層使用在雙閘極氧化層厚度的 P 型金氧半場效電晶體上在負電壓溫度不穩定性及熱載子注入等可靠度之比較，以及元件使用以鉿為基本材料之高介電係數介電層在正電壓溫度不穩定性分析中捕捉/反捕捉電子的可靠度分析。我們完整地研究了 65 奈米技術的 P 型金氧半場效電晶體在<110>及<100>通道方向上對主動區佈局的相依性以及淺溝渠隔離所造成的單向壓縮應力對其特性的影響。對 65 奈米的 P 型金氧半場效電晶體而言，當源/汲極長度從 0.21 微米增加到 10 微米，<100> 通道方向在飽和汲極電流特性方面會比<110>通道的元件高出約從 8 % 提高到 15 ％。再者，我們也證明了對於不管在通道長度或寬度方向來說，<100>通道的元件對硼的擴散有較高的抑制能力以及對淺溝渠隔離所造成的應力也有較低的感受度。我們亦利用高應力之氮化矽覆蓋層以及非晶矽與多晶矽堆疊之閘極結構等區域應變通道技術在(111)晶向矽基版上製作出 N 型金氧半場效電晶體。當氧化矽覆蓋層或非 i.

(4) 晶矽層厚度增加時，元件的飽和電流及轉移電導也隨之上升。我們的實驗結果顯示相對於非晶矽厚度為 20 奈米的元件而言，非晶矽厚度為 70 奈米的元件在飽和電流方面有約 6.7 %的改善；在轉移電導方面則有約 10.2 %的增加。此外，我們比較了使用電漿氮化氧化層及熱氮化氧化層兩種不同閘極介電層的核心與輸入/輸出之 P 型金氧半場效電晶體受到負電壓溫度不穩定性及熱載子注入等可靠度的影響。以電漿氮化氧化層作為閘極氧化層材料之 P 型金氧半場效電晶體在漂移率方面比熱氮化氧化層元件高了約 30 %，定電壓過驅動電流的值也比熱氮化氧化層高了約 23 %。相較於熱氮化氧化層，電漿氮化氧化層之核心 P 型金氧半場效電晶體因為在氧化層與矽基版界面有較低之氮的濃度，所以有較佳的負電壓溫度不穩定性及熱載子注入抵抗能力。然而，電漿氮化氧化層之輸入/輸出 P 型金氧半場效電晶體則表現出較高的熱載子注入造成的特性退化率因為其有較高的氧化層內的主體缺陷。不過對於操作在一般電壓之負電壓溫度不穩定性方面，仍是優於熱氮化氧化層歸因於較低的界面缺陷密度。最後，我們論證了以二氧化鉿(HfO2)及鉿之氮氧化矽(HfSiON)兩種材料作為閘極氧化層的N型金氧半場效電晶體在正電壓溫度不穩定性可靠度的特性退化。對以鉿為基本材料之高介電係數介電層而言，在正電壓溫度不穩定性可靠度測試期間所產生的氧化層主體缺陷會主導元件的正電壓溫度不穩定性之特性退化。在正電壓溫度不穩定性可靠度測試中，較低的臨界啟始電壓退化以及氧化層主體缺陷產生率，證明了鉿之氮氧化矽的薄膜品質優於二氧化鉿。此外，在正電壓溫度不穩定性可靠度測試期間，相對於二氧化鉿介電層而言，鉿之氮氧化矽則有較淺的電荷捕捉能階。. ii.

(5) Gate Engineering of Advanced MOSFETs for Device Performance and Reliability Improvement. Student: Wen-Cheng Lo. Advisors: Dr. Chun-Yen Chang Dr. Tien-Sheng Chao. Department of Electronics Engineering & Institute of Electronics National Chiao Tung Univerity. Abstract In this dissertation, we investigated the gate engineering integration for advanced device performance and reliability improvement including the comparison of STI-induced local uniaxial compressive stress in <110>- and <100>-channel directions, the use of SiN capping layer on (111) orientation substrate to improve the NMOSFET performance, the reliability comparisons in negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) between dual gate oxide PMOSFETs using plasma nitrided oxide (PNO) and thermally nitrided. oxide. (TNO). and. the. positive-bias. temperature. instability. (PBTI). trapping/de-trapping reliability issues for devices using Hf-based high-k dielectrics. Active-region layout dependence and STI-induced uniaxial compressive stress impact on the performance of 65 nm technology PMOSFETs with <110>- and <100>-channel directions were fully investigated. For 65 nm PMOSFET, <100>-channel show as higher as about 8 ~. iii.

(6) 15% in Id_sat than <110>-channel devices as S/D length increased from 0.21 m to 10 m. Furthermore, higher immunity to boron diffusion and less sensitivity on STI-induced strain in both of channel length and width directions for <100>-channel devices were also demonstrated. We also investigated NMOSEFT fabricated with local strained channel techniques on a (111) Si substrate using a SiN capping layer with high mechanical stress and the stack gate of amorphous silicon (α-Si) and polycrystalline silicon (poly-Si). The on-current and transconductance (Gm) increased with increasing SiN capping layer or α-Si layer thickness. Our experimental results show that devices with a 700 Å α-Si layer show a 6.7% on-current improvement percentage relative to those with a 200 Å α-Si layer, and a corresponding Gm improvement percentage of 10.2%. Besides, we compared the effects of NBTI and HCI on the core and input/output (I/O) PMOSFET fabricated using the different gate dielectrics of PNO and TNO. The mobility and constant overdrive current of the PMOSFETs fabricated using PNO as a gate oxide material are about 30% and 23% higher than those of the devices fabricated using TNO, respectively. The core PMOSFETs fabricated using PNO show a better NBTI and HCI immunity than those fabricated using TNO owing to the lower nitrogen concentration at the SiO2/Si-substrate interface. However, the I/O PMOSFETs fabricated using PNO show a higher HCI-induced degradation rate because of a higher oxide bulk trap density but a better NBTI than the. iv.

(7) devices fabricated using TNO at a normal stressed bias due to a low interface trap density. In the final part, PBTI degradation for HfO2 and HfSiON NMOSFETs with the metal gate electrode has been successfully demonstrated. The generated oxide trap during PBTI stress will dominate the PBTI characteristics for Hf-based gate dielectrics. The reduction of threshold voltage degradation and oxide trap generation under PBTI stress indicates that the HfSiON thin film quality is better than HfO2. In addition, as compared to HfO2 dielectrics, the HfSiON has shallower charge trapping level under PBTI stress.. v.

(8) 致. 謝. 終於…畢業了！一本薄薄百來頁的博士論文，也許可以顯示出了這幾年的研究成果，但卻描述不出這些年遇到的挫折、低潮與掙扎。無論如何，總算是完成了我人生的一個重要目標。首先要感謝我的指導教授張俊彥博士在這個領域上給我的指導與幫助，從老師身上也讓我看到了身為一個領導者該有的風範。另外，我還要感謝共同指導教授趙天生博士。老師對我來說，是亦師亦友。對於有關我畢業的事情，總是比我還要關心與在乎。老師的一句話：「家庭就是我們最大的事業」，讓我感動到幾度熱淚盈框，我會一直將這句話謹記在心並奉為圭臬。感謝在我博士求學生涯帶我、指導我的張勝傑學長與李耀仁學長。在學校求學以及在台積電工作的期間，因為有張勝傑學長對我的許多指導與幫助，讓我學到很多，也讓我人生規劃明確的多。李耀仁學長在學術實驗上嚴謹的態度是我最推崇的，在我畢業前這一年，也給予我很多課業上的討論與想法。在此也感謝在台積電工作期間一起工作的所有同事們，你們讓我的人生眼界寬廣不少。也感謝一起渡過漫長求學路的實驗室成員們，讓我在學校的生活更加多采多姿。相信不久之後在職場中，我們會再相遇的。要感謝的，還有一群交心的麻吉幫兄弟：偉成（軟成）、弘彬（娘彬）、亦臺（娘臺）、百騏（百娘）、克竣（克軟）、智維等等，和你們的兄弟聚會，是我最輕鬆、最快樂的時光。在我學業跟感情低潮那時，能夠遇到你們這群交心的好兄弟，是我最開心也最珍惜的一件事！感謝在我漫長求學期間曾經陪在我身邊、離開我身邊的女人，妳們豐富了我的感情生活，讓我能夠用更成熟、更自省的心態去完善我以後的感情與人生。感謝 Foxy 的關心與包容，讓我在最後這段壓力最大，脾氣最煩躁的關頭能夠順利將論文衝刺出來。最後，謹以這本博士論文，獻給我的爸媽，沒有你們無怨無悔的犧牲奉獻，不會有今日的我。還有我的老弟。我的成就，因為有你們，一切才具有了意義。你們永遠都是我最最最愛的家人！. 2007 于風城․交大 vi.

(9) Contents Abstract (in Chinese)…………………………………………………………….i Abstract (in English)…………………………………………………………...iii Acknowledge (in Chinese)……………………………………………………..vi Contents………………………………………………………………………..vii Table Captions…………………………………………………………………..x Figure Captions………………………………………………………………...xi. Chapter 1. Introduction…………………………………………………..…..1 1-1 General background………………………………………….…………………….……..… ...1 1-2 Motivation……………………………………………………….…….……………………………...6 1-3 Thesis outline……………………………………………………………….…...……………..… ...9 1-4 References…………………………………………………………….………….………………….12. Chapter 2. Systematical Comparisons on Performance Improvement by STI-Induced Strain between <110>- and <100>- Channel Directions Sub-65 nm PMOSFETs……………….…..…….….23 2-1. Introduction………………………………...……………………….………………….….………23. 2-2. Experiment….…………………………………………..…………………………………….........25. 2-3 Results and discussions..………………………………………………………….………...26. Chapter 3. 2-4. Summary…………………………………………………………………………...……….............31. 2-5. References…..………………………………………………………...………...…………………..32. Performance Enhancement by Local Strain in <110> Channel n-channel Metal-Oxide-Semiconductor Field-Effect Transistors on (111) Substrate…………………….……………………….. 48 vii.

(10) 3-1. Introduction………………………………………………………………...….…..…….………...48. 3-2. Experiment. 3-3. Results and discussions……………………………………………………...….…...…........51. ………………………………………………………………....…….…………..........49. 3-3-1 Single-poly-Si gate structure with SiN capping layer of different thicknesses……………………………………………...…………………...51 3-3-2 Stack of α-Si and Poly-Si gate with SiN capping layer of fixed thickness……………………………………………………………………...………............54. Chapter 4. Chapter 5. 3-4. Summary…………………………………………………………………………….………..…. ….56. 3-5. References……………………………………………………………….……….………………….57. Systematical Study of Reliability Issues in Plasma-Nitrided and Thermally Nitrided Oxides for Advanced Dual-Gate Oxide PMOSFETs…………………………………………….………. 70 4-1. Introduction……………………………………………………………………………….…...…..70. 4-2. Experiment……………………………………………………….………………………………...71. 4-3. Results and discussions…………………………………………………………….………..72 4-3-1 Material analysis and device performance of PNO and TNO PMOSFETs……………………………………………….……………….……….…72 4-3-2 NBTI and HCI comparison between PNO and TNO…...............74 4-3-3 Mechanism………………………………………………….…………………….………77. 4-4. Summary…………………………………………………………………...………………………..80. 4-5. References……………………………………………………………………..……………………81. The Comparisons of Trapping and De-trapping effects in Positive Bias Temperature Instability Stress between HfO2 and HfSiON Gate Dielectrics……………………….………………98 5-1. Introduction…………………………………………………….……………………….…………98. 5-2. Experiment…………………………………………………………………...…………….…….100. 5-3. Results and discussions……………………………………………….…………….……..101 5-3-1 Device performance……………………………………...………………...……….101 5-3-2 PBTI degradation for HfO2 and HfSiON gate dielectrics…102 viii.

(11) 5-3-3 Temperature-dependent de-trapping characteristics for HfO2 and HfSiON gate dielectrics…………………………….…….......……………104. Chapter 6. 5-4. Summary………………………………………………………………….……….………………106. 5-5. References………………………………………………………………………………..…….….107. Conclusions and Recommendations for Future Study….…..124 6-1. Conclusions…………………………………………………………………………………….…124. 6-2. Suggestions for future work………………………………………...………………….127. Vita (Chinese)……………………………………….………………………..128 Publication list……………………………………….……………………….129. ix.

(12) Table captions Chapter 2 Table 2-1. Summarized table for compressive stress impacts on PMOSFET performance with <110> and <100> in 3D directions……………………………………..47. Chapter 4 Table 4-1. Summary of effect and mechanisms of NBTI and HCI on core and I/O PMOSFETs with PNO and TNO oxides……………………………………..97. x.

(13) Figure captions Chapter 2 Fig. 2-1. (a) scheme of <110>-channel devices and layout parameter definition (b) scheme of <100>-channel devices. The definition of La is S/D length (the length from gate edge to STI edge)..................................................................36. Fig. 2-2. Id_sat (Id at Vg = Vd = -1.2V) ratio of <100> to <110> with varied La and channel length for (a) NMOSFET (b) PMOSFET…………………………...37. Fig. 2-3. Id_sat (Id at Vg = Vd = -1.2V) ratio of <100> to <110> with La = 10 μm and 0.21 μm for NMOS and PMOS devices……………………………………...38. Fig. 2-4. Id-Vg at Vd = -1.2V and Gm at Vd = -0.05V characteristics of 60 nm PMOS devices with <110>- and <100>-channel orientations for (a) La = 10 μm (b) La = 0.21 μm………………………………………………………...……….39. Fig. 2-5. Schemes of hole valence band structures for (a) unstrained Si and (b) Si under uniaxial compressive stress…………………………………………………..40. Fig. 2-6. Ion-Ioff characteristics of 60 nm PMOSFETs between <110>- and <100>channel orientations for (a) La = 10 μm and (b) La = 0.21 μm……....41. Fig. 2-7. Id_sat dependence Vth_sat at Vd = -1.2V of 60 nm PMOS devices with La = 10 and 0.21 μm for (a) <110>-channel (b) <100>-channel directions…………..42. Fig. 2-8. Constant overdrive current at Vg – Vth = -0.75V of 60 nm PMOSFETs with. xi.

(14) <110>- and <100>-channel……………………………………………..…….43 Fig. 2-9. Id_sat versus DIBL of PMOSFET with La = 10 and 0.21 μm for (a) <110>channel and (b) <100>-channel devices…………………………….44. Fig. 2-10. PMOS overlap capacitance cumulative distributions of <110> and <100>channel devices…………………………………………………………….…45. Fig. 2-11. Id_sat dependence Vth_sat of Lg/La = 1 μm /10 μm PMOS devices with varied channel widths for (a) <110>-channel and (b) <100>-channel directions…...46. Chapter 3 Fig. 3-1. Schematic cross section of local strained channel nMOSFET on (111) substrate…………………………………………………………...………….60. Fig. 3-2. Electrical Id-Vd characteristics of devices using fixed single-poly-Si thickness (2000 Å) with various SiN capping layer thicknesses on (111) orientation substrate…………………………………………………..………………….61. Fig. 3-3. Gm characteristics versus overdrive gate voltage for devices with various SiN capping layer thicknesses…………………………………………………….62. Fig. 3-4. 2-D simulation results due to SiN-capping-layer-induced stress in channel region using SILVACO simulation tool. Negative values indicate compressive stress and positive values indicate tensile stress……………………………..63. xii.

(15) Fig. 3-5. Threshold voltages of devices with poly-Si = 2000 Å and different SiN thicknesses……………………………………………..……………………..64. Fig. 3-6. Charging pumping current curves of devices with different SiN capping layer thicknesses……………………………………………………..……………..65. Fig. 3-7. Id-Vd characteristics of devices with different α-Si thicknesses and fixed SiN capping layer thickness (1500 Å)……………………………………...……..66. Fig. 3-8. Output characteristics of Gm for all devices with fixed SiN thickness (1500 Å) and various α-Si thicknesses in gate construction………………………..….67. Fig. 3-9. Simulated 2-D stress distribution contour of nMOSFET with 700 Å α-Si on (111) orientation substrate……………………………………………………68. Fig. 3-10. Threshold voltages of devices with fixed SiN capping layer thickness (1500 Å) and various α-Si thicknesses…………………………………………………69. Chapter 4 Fig. 4-1. Schematic illustration of nitrided oxide formation processes for PNO and TNO…………………………………………………………………………..86. Fig. 4-2. High-frequency C-V characteristics of Core and I/O PMOS devices with gate dielectrics of PNO and TNO. The measurement frequency for core devices is 1 MHz and that for I/O devices is 100 kHz………………………………...…..87. Fig. 4-3. Nitrogen concentration profiles of PNO and TNO in nitrided oxide analyzed xiii.

(16) by ARXPS. The insert shows the normalized Gm of core PMOSFETs as a function of Vg-Vt for both PNO and TNO……………………………..…….88 Fig. 4-4. Comparison of Id-Vd characteristics between PNO and TNO for Core PMOSFETs at Vg – Vt from 0 to -1.2 V with steps of -0.3 V…………..……89. Fig. 4-5. Charge pumping currents of PNO and TNO Core PMOSFETs before and after 4095 s NBTI stress at Vg = -2.5 V at 125°C………………………..………..90. Fig. 4-6. NBTI-induced interface trap generation (ΔNit) and drive current degradation as functions of stress time for both PNO and TNO PMOSFETs. The stress bias Vg is -2.5 V and the temperature is 125°C…………………………………...91. Fig. 4-7. Time dependences of NBTI-induced Vth degradation at various stress biases from -2.2 to -2.8 V per -0.3 V at 125°C for PNO and TNO for (a) core and (b) I/O PMOSFETs…………………………………………………………….....92. Fig. 4-8. HCI-induced Vth degradation, at various stress biases versus stress times of PNO and TNO for (a) Core and (b) I/O PMOSFETs. The stress bias conditions used are Vg = Vd from -2.2 to -2.8 V with steps of -0.3 V………………..…93. Fig. 4-9. Schematic illustration of degradation mechanism for (a) core TNO, (b) Core PNO, (c) I/O TNO, and (d) I/O PNO devices. “L” and “ℓ” indicate the channel regions where NBTI and HCI effects on devices are observed, respectively...94. Fig. 4-10. The normalized gate current density ((Jg – Jg0)/Jg0) at a constant gate voltage. xiv.

(17) of electric field is about 10 MV/cm versus the stress times of PNO and TNO core and I/O PMOS capacitors…………………………………………….….95 Fig. 4-11. SILC phenomena of Jg before and after constant 1000 s voltage stress of Vg = 5.5 V, as function of measured gate voltage of I/O PMOS capacitors with PNO and TNO oxides………………………………………………………..……..96. Chapter 5 Fig. 5-1. High-frequency C-V characteristics at 100 kHz for NMOSFET with HfO and 2. HfSiON gate dielectrics, respectively……………………………………….111 Fig. 5-2. The effective electron mobility measured on HfO 2 and HfSiON gate dielectrics using split CV method…………………………………………...112. Fig. 5-3. Threshold voltage degradation (ΔVth ) of HfO2 and HfSiON gate dielectrics under the same PBTI stress (Vg = +2.5 V) at room temperature……………113. Fig. 5-4. Charge pumping current (ICP) before and after PBTI stressing at +2.5V for HfO2 and HfSiON dielectrics, respectively…………………………………114. Fig. 5-5. Charging pumping increase (ΔICP) of HfO2 and HfSiON gate dielectrics during the same PBTI stress bias (Vg = +2.5 V) at room temperature……………..115. Fig. 5-6. Interface trap increase (ΔNit) which extracted from ΔICP of HfO2 and HfSiON gate dielectrics during the same PBTI stress bias (Vg = +2.5 V) at room. xv.

(18) Temperature…………………………………………………………...…….116 Fig. 5-7. Generated oxide trap (ΔNot) in the bulk of higk-k film during PBTI stress for both of HfO2 and HfSiON dielectrics, respectively…………………….…..117. Fig. 5-8. Illustration of electron trapping model for Hf-based gate dielectrics under PBTI stress………………………………………………………………..…118. Fig. 5-9. Threshold voltage degradation of HfO2 and HfSiON gate dielectrics during PBTI stress (Vg = +2.5 V) with no hold time at different temperatures, including 25, 75 and 100 oC……………………………...…………………119. Fig. 5-10. Threshold voltage degradation of HfO2 and HfSiON gate dielectrics during PBTI stress (Vg = +2.5 V) with hold time 100 s at different temperatures, including 25, 75 and 100 oC……………………….………………………..120. Fig. 5-11. Comparison of different hold time (0 & 100 s) under PBTI stress (Vg = +2.5 V) at different temperatures, including 25, 75 and 100 oC for HfO2 gate dielectrics……………………………...…………………………………….121. Fig. 5-12. Comparison of different hold time (0 & 100 s) under PBTI stress (Vg = +2.5 V) at different temperatures, including 25, 75 and 100 oC for HfSiON gate dielectrics………………………………………………………………..…..122. Fig. 5-13. Illustration of the charge trapping/de-trapping models for (a) HfO2 and (b) HfSiON gate dielectrics under PBTI stress respectively………………….123. xvi.

(19) Chapter 1 Introduction. 1-1 General Background 1-1-1 Mobility enhancement technology As integrated circuit (IC) technology enters ultra-large-scale integration (ULSI) generation, geometric scaling of silicon complementary metal-oxide semiconductor (CMOS) transistors has enabled not only an exponential increase in circuit integration density, but also a corresponding enhancement in the transistor performance itself. For this reason, mobility enhancement technology has become a very important research in CMOS fabrication. Recently, mobility enhancement by stress control technologies is emerging as one of the key elements in scaling of complementary metal-oxide-semiconductor (CMOS) transistors since it offers increased drive current without the penalty of additional capacitance and gate current. leakage.. There. are. two. main. approaches. for. implementing. strain. on. metal-oxide-semiconductor field-effect-transistors (MOSFETs). One is the substrate biaxial stress where stress is introduced across the entire substrate [1-5]. When a thin film with a larger lattice constant (SiGe) is grown on a substrate with smaller lattice constant (Si), the film retains the in-plane lattice constant of the substrate and a biaxially compressive strain (or tensile strain under contrary condition) will be generated [6]. However, biaxial tensile stress. -1-.

(20) using strained Si on relaxed SiGe face a lot of challenges such as misfit and defects, Ge up-diffusion [7], high cost and modest hole mobility gain at high field because quantization effect [8-9]. In contrast, the second approach, process-induced uniaxial strain such as shallow-trench isolation (STI) [10], silicon nitride capping layer [11], silicidation process [12] and embedded SiGe source/drain (S/D) [13] can offer similar electron mobility enhancement compared with biaxial strain, while the hole mobility improvement is more significant at high field [7]. For this reason, although STI-induced strain in the channel region had generally considered a problem rather than an opportunity in the past, nowadays, STI-induced compressive stress in the channel has become a key point as device scaled down. Another simple way to enhance mobility is using a wafer with a specific channel orientation which has smaller carrier effective mass. The <100>-channel device on (100), whose channel direction is rotated by 45 degree from the conventional <110>-channel device, had been reported that PMOS drive current could be improved, with NMOS performance maintained [14]. On the other hand, novel three-dimensional (3-D) device structures with a double or surrounded gate such as fin field-effect transistor (FinFET) [15-17] and vertical metal-oxide-semiconductor field-effect transistor (MOSFET) [18-20] are widely investigated. These specific structures enable the device channel to be fabricated on various surface crystal orientations. Since channel mobility is well known to be strongly dependent on crystal. -2-.

(21) orientation [21-22], the characteristics of devices with various crystal orientations should be carefully studied to optimize the performance for ultra large-scale integration (ULSI) technology applications. It has recently been reported that oxide quality and reliability on a (111) substrate are slightly better than those on a conventional (100) substrate for ultrathin (< 2 nm) gate oxide [23]. It was also found that for a thin gate oxide of less than 2 nm, the oxidation rate of a (111) silicon substrate is lower than that of a (100) substrate such that the oxide uniformity of the (111) substrate is also improved [23-24]. The mobility of pMOSFETs on a (111) substrate can be improved owing to the low hole effective mass of the substrate; however, the low-field mobility of a (111) nMOSFETs is still less than that of (100) substrate. Therefore, it is very important to determine how to increase electron mobility in the channel region [25-27] on a (111) substrate.. 1-1-2 Reliability issues For advanced ultra-large-scale integration (ULSI) technology, nitrogen atoms are incorporated into silicon dioxide to block an undesirable boron penetration from a P+ poly-gate electrode of a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET). [28-30].. Even. for. cutting-edge. 65. nm. complementary. metal-oxide-semiconductor (CMOS) technology, nitrided oxide is still a key gate dielectric material for achieving a high device performance for both general and low-power applications. -3-.

(22) [31-33]. On the other hand, devices feature dual gate oxide (DGO) processes in which thin oxide is used for core and logic circuits and thick oxide is used for input/output (I/O) and analog circuits, owing to the decreasing size and increasing number of system-on-chip applications. Consequently, reliability issues, such as negative-bias temperature instability (NBTI) [34-35] and hot-carrier injection (HCI) [36-38], that could induce threshold voltage shift and performance degradation in DGO PMOSFETs become a serious concern for realizing highly reliable integrated CMOS devices. Therefore, both the concentration and distribution of nitrogen in the gate oxide should be optimized since excessive nitrogen at the interface may induce interface traps, resulting in reduced channel carrier mobility [39] and a degraded reliability [40]. Furthermore, it has become necessary to identify alternate high-k gate dielectrics that meet the stringent requirements for low leakage current and thin equivalent oxide thickness (EOT) [41-45]. High-k dielectrics are especially advantageous for low-power application and for thickness uniformity control owing to the thicker physical thickness. Among high-k gate dielectric materials, Hf-based gate dielectric including HfO2 and Hf-silicate are the attractive materials because it has good device characteristics and is compatible with the conventional polysilicon gate process [46-49]. However, before Hf-based gate dielectrics being successfully integrated into future technologies, their reliability characteristics still need to be better identified. Bias temperature instability (BTI) has been recognized as one of the critical. -4-.

(23) concern in the reliability of modern CMOS devices. Many of the past BTI researches on the SiO2 dielectric have just focused on the negative BTI (NBTI) on PMOS devices [50-51], since it impacts more the devices reliability with respect to positive BTI (PBTI) on NMOS [52]. In conventional SiO2 gate oxides, NMOS under PBTI stress shows little threshold voltage degradation and hence is not a reliability concern while PMOS under NBTI stress has a continued reliability issue as the gate oxide thickness is scaled thinner. On the contrary, unlike conventional SiO2 gate dielectrics, NMOS positive bias temperature instability (PBTI) could be a potential scaling limit of CMOS technology with Hf-based gate dielectrics [53]. Most of the previous studies showed a significant positive threshold voltage shift for the high-k gate stack under PBTI stressing, which was attributed to the preexisting traps in the high-k layer or the hole induced oxygen vacancy traps [54-58]. In addition, one of main issues for high-k gate dielectrics is the charge trapping/de-trapping characteristics during reliability test. Initial observation of instability was studied through capacitance–voltage (CV) characteristics in Vfb change and current–voltage (IV) in Vth change. Since electrons can be trapped and de-trapped in the high-k dielectrics with a minimal residual damage to its atomic structure, a Vth instability associated with electron trapping/detrapping in high-k layer can significantly affect the transistor performance [59]. Nevertheless, it also complicates the evaluation of the effects of stress-induced defect generation phenomenon on the high-k gate dielectrics, which typically is not an issue in the case of SiO2 dielectrics [60]. In order to. -5-.

(24) investigate the additional electron trapping effects on top of defect generation, a de-trapping step has been proposed for studying generation of the electron trapping process and its impact on high-k device reliability [61]. Recently, the electron de-trapping behavior in the high-k films has used under specific gate bias conditions identifying charge trapping and relaxation mechanism [62]. However, the dependence of the dielectric electrical characteristics on the de-trapping conditions has not been investigated in detail.. 1-2 Motivation 1-2-1 STI-induced compressive stress in <110> and <100>-channel direction Recently, mobility enhancements by stress control technologies is emerging as one of the key elements in scaling of CMOS transistors since it offers increased drive current without the penalty of additional capacitance and gate current leakage. Process-induced uniaxial strain such as shallow-trench isolation (STI), silicon nitride capping layer, silicidation process and embedded SiGe source/drain (S/D) can offer similar electron mobility enhancement compared with biaxial strain, while the hole mobility improvement is more significant at high field. Nowadays, STI-induced compressive stress in the channel has become a key point as device scaled down. Besides, the <100>-channel device on (100), whose channel direction is rotated by 45 degree from the conventional <110>-channel device, had been reported that PMOS drive current could be improved, with NMOS performance maintained.. -6-.

(25) In this thesis, we have examined the fully study of STI-induced strain impacts on the performances of small devices with <110>- and <100>-channel orientations.. 1-2-2 Tensile strain induced by SiN capping layer and stack of α-Si gate on (111) substrate It has recently been reported that oxide quality and reliability on a (111) substrate are slightly better than those on a conventional (100) substrate for ultrathin (< 2 nm) gate oxide. It was also found that for a thin gate oxide of less than 2 nm, the oxidation rate of a (111) silicon substrate is lower than that of a (100) substrate such that the oxide uniformity of the (111) substrate is also improved. The mobility of pMOSFETs on a (111) substrate can be improved owing to the low hole effective mass of the substrate; however, the low-field mobility of a (111) nMOSFETs is still less than that of (100) substrate. Therefore, it is very important to determine how to increase electron mobility in the channel region on a (111) substrate. In this thesis, we proposed the use of local strained channel techniques on a (111) Si substrate by depositing a SiN capping layer with high mechanical tensile stress and using the stack gate of amorphous silicon (α-Si) and polycrystalline silicon (poly-Si) to improve the performance of NMOSFETs with the <110> channel direction on a (111) substrate.. 1-2-3 Reliability issues of dual-gate oxide PMOSFET with PNO and TNO For ULSI generation, nitrogen atoms are incorporated into silicon dioxide to block an. -7-.

(26) undesirable. boron. penetration. from. a. P+. poly-gate. electrode. of. a. p-channel. metal-oxide-semiconductor field-effect transistor (PMOSFET). Even for cutting-edge 65 nm CMOS technology, nitrided oxide is still a key gate dielectric material for achieving a high device performance for both general and low-power applications. Consequently, reliability issues, such as negative-bias temperature instability (NBTI) and hot-carrier injection (HCI), that could induce threshold voltage shift and performance degradation in DGO PMOSFETs become a serious concern for realizing highly reliable integrated CMOS devices. Therefore, both the concentration and distribution of nitrogen in the gate oxide should be optimized since excessive nitrogen at the interface may induce interface traps, resulting in reduced channel carrier mobility and a degraded reliability. In this thesis, the impacts of NBTI and HCI on core and I/O PMOSFETs between devices with plasma nitrided oxide (PNO) and devices with thermally nitrided oxide (TNO) were compared systematically.. 1-2-4 De-trapping effects in high-k dielectrics under PBTI stress As CMOS devices are scaling down aggressively, it has become necessary to identify alternate high-k gate dielectrics that meet the stringent requirements for low leakage current and thin equivalent oxide thickness (EOT). However, before Hf-based gate dielectrics being successfully integrated into future technologies, their reliability characteristics still need to be. -8-.

(27) better identified. Unlike conventional SiO2 gate dielectrics, NMOS positive bias temperature instability (PBTI) could be a potential scaling limit of CMOS technology with Hf-based gate dielectrics. In addition, one of main issues for high-k gate dielectrics is the charge trapping/de-trapping characteristics during reliability test. The electron de-trapping behavior in the high-k films has used under specific gate bias conditions identifying charge trapping and relaxation mechanism. However, the dependence of the dielectric electrical characteristics on the de-trapping conditions has not been investigated in detail. In this thesis, the comparison of trapping/de-trapping effect of NMOSFET under PBTI stress test between NMOSFETs with HfO2 and Hf-silicates (HfSiON) high-k dielectrics has been investigated.. 1-3 Thesis outline This dissertation is divided into six chapters as follows: In chapter 1, a brief general background of gate engineering such as process-induced local strain, channel direction, substrate orientation and different gate dielectrics for performance and reliability improvement is introduced. Then we discuss some of the most important issues of CMOS technology and the motivation of our study. Then the outline throughout this dissertation is described here. In chapter 2, the layout dimension dependence of relative performance for 65-nm. -9-.

(28) MOSFETs is systematically investigated. We have further examined the fully study of STI-induced strain impacts on the performances of small devices with <110>- and <100>-channel orientations. Furthermore, higher immunity to boron diffusion and less sensitivity on STI-induced strain in both of channel length and width directions for <100>-channel devices were also demonstrated. In chapter 3, we proposed the use of local strained channel techniques on a (111) Si substrate by depositing a SiN capping layer with high mechanical tensile stress and using the stack gate of amorphous silicon (α-Si) and polycrystalline silicon (poly-Si) to improve the performance of NMOSFETs with the <110> channel direction on a (111) substrate. By using these techniques, the performance improvement of the NMOSFETs in the <110> channel direction on the (111) substrate was achieved. In chapter 4, the impacts of NBTI and HCI on core and I/O PMOSFETs between devices with plasma nitrided oxide (PNO) and devices with thermally nitrided oxide (TNO) were compared systematically. The mobility of the PMOSFETs fabricated using PNO is higher than those of the devices fabricated using TNO. The core PMOSFETs with PNO show a better NBTI and HCI immunity than those fabricated using TNO. However, the I/O PMOSFETs fabricated using PNO show a higher HCI-induced degradation rate but a better NBTI than the devices fabricated using TNO. In chapter 5, the comparison of trapping/de-trapping effect under PBTI stress test between. - 10 -.

(29) NMOSFETs with HfO2 and Hf-silicates (HfSiON) high-k dielectrics has been investigated. We just primary focus on NMOS devices PBTI here since it is more significant than PMOS NBTI in the case of Hf-based dielectrics MOSFETs. In chapter 6, we summary our experimental results and give a brief conclusion. Recommendations are also given for further study.. - 11 -.

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(41) Chapter 2 Systematical Comparisons on Performance Improvement by STI-Induced Strain between <110>- and <100>-Channel Directions Sub-65 nm PMOSFETs. 2-1 Introduction Recently, mobility enhancements by stress control technologies is emerging as one of the key elements in scaling of complementary metal-oxide-semiconductor (CMOS) transistors since it offers increased drive current without the penalty of additional capacitance and gate current. leakage.. There. are. two. main. approaches. for. implementing. strain. on. metal-oxide-semiconductor field-effect-transistors (MOSFETs). One is the substrate biaxial stress where stress is introduced across the entire substrate [1-5]. When a thin film with a larger lattice constant (SiGe) is grown on a substrate with smaller lattice constant (Si), the film retains the in-plane lattice constant of the substrate and a biaxially compressive strain (or tensile strain under contrary condition) will be generated [6]. However, biaxial tensile stress using strained Si on relaxed SiGe face a lot of challenges such as misfit and defects, Ge up-diffusion [7], high cost and modest hole mobility gain at high field because quantization effect [8-9]. In contrast, the second approach, process-induced uniaxial strain such as shallow-trench. - 23 -.

(42) isolation (STI) [10], silicon nitride capping layer [11], silicidation process [12] and embedded SiGe source/drain (S/D) [13] can offer similar electron mobility enhancement compared with biaxial strain, while the hole mobility improvement is more significant at high field [7]. For this reason, although STI-induced strain in the channel region had generally considered a problem rather than an opportunity in the past, nowadays, STI-induced compressive stress in the channel has become a key point as device scaled down. Besides, another simple way to enhance mobility is using a wafer with a specific channel orientation which has smaller carrier effective mass. The <100>-channel device on (100), whose channel direction is rotated by 45 degree from the conventional <110>-channel device, had been reported that PMOS drive current could be improved, with NMOS performance maintained [14]. In this chapter, active-region layout dependence of 65 nm PMOSFET performance with <110>- and <100>- channel orientations were fully investigated. We have further examined the fully study of STI-induced strain impacts on the performances of small devices with <110>- and <100>-channel orientations. For 65 nm PMOSFET, <100>-channel show about 8-15% higher drain current than <110>-channel devices as S/D length increased from 0.21 m to 10 m. Furthermore, higher immunity to boron diffusion and less sensitivity on STI-induced strain in both of channel length and width directions for <100>-channel devices were also demonstrated.. - 24 -.

(43) 2-2 Experiment (100) orientation substrate with <110>- and <100>-notch wafers (Fig. 2-1(a), (b), respectively), where the wafer notched at different directions with 45 degree-off were used for experiment splits. CMOS devices were fabricated with state-of-the-art 300 mm wafer foundry technology [15] which includes super steep retrograde (SSR) indium and arsenic channels, aggressive poly Si gate control, multi-tilted pocket implants, shallow source/drain extensions, and deep source/drain with low junction leakage. Implants are followed by spike anneal process to minimize diffusion. STI was used for isolation followed by retrograde well formation. After channel implantation, plasma nitrided gate-oxide with a gate oxide thickness (Tox) of 1.4 nm and un-doped poly-silicon deposition with N+ gate pre-doping and gate patterning were followed. After shallow source/drain extensions and pocket implantation, tetraethoxysilane (TEOS) liner and low-temperature silicon nitride were processed in sequence to form a sidewall spacer. Modified S/D implants were adopted to improve activation and junction capacitance while maintaining good SCE. The fabrication of a heavily doped source/drain junction by implantation was followed by rapid thermal annealing (RTA) and NiSi self-aligned silicidation. The symbols of layout parameters were also defined in Fig. 2-1(a).. - 25 -.

(44) 2-3 Results and Discussions The drive current (Id at Vg = Vd = -1.2 V) improvement ratio of <100>-channel to conventional <110>-channel with varied channel length devices as a function of S/D length (La: length from gate edge to STI edge) are shown in Fig. 2-2 (a), (b) for NMOSFET and PMOSFET, respectively. It is found that NMOS characteristics won’t be deteriorated by using <100>-channel. There is little difference of drain current between two kinds of NMOSFET with <110>- and <100>-channel. The drive current ratio of NMOS devices are all smaller than 4%, in spite of varied gate length and decreased La. This result indicates that STI-induced stress have no significant impact on performance of NMOSFET devices for both of conventional <110>- and <100>-channel. It was also reported that there is a slight difference of drift velocity even between <110> and <111> direction, but that the difference of saturated velocity becomes still minute with an increase in electric field [16]. In contrast, for long channel (Lg > 0.24 μm) PMOS devices with La = 10 μm where the STI-induced stress doesn’t impact the channel region, the drain current ratio of <100>- to <110>-channel is as high as 24 %. The drive current improvement ratio decreases as channel length scales down to smaller than 0.24 μm due to velocity saturation. Furthermore, although the drive current ratio of PMOSFET decreases as La shrinks (higher STI-induces compressive stress), it still shows about 6 % ~ 10 % improvement for devices with shortest La (0.21 μm), as shown in Fig. 2-2 (b). Figure 2-3 shows comparisons the current ratio of <100>-channel to. - 26 -.

(45) <110>-channel between La = 10 μm and La = 0.21 μm for the devices with varied channel length for both of NMOSFET and PMOSFET. For NMOSFET devices, there is no significant difference in current ratio under STI-induced stress as devices length scales down. For PMOSFET with La = 10 μm, <100>-channel devices show a higher drive current than <110>-channel devices. Although the drive current improvement of <100>-channel to <110>-channel drops dramatically as channel length scales down, PMOSFET with <100>-channel still shows about 16% higher than <110>-channel. But if the channel region was influenced by STI-induced compressive stress, the current ratio of <100>-channel to <110>-channel will down to smaller than 10%. This result illustrates that the impact of STI-induced compressive stress on PMOSFET with <110>-channel was much higher than that of <100>-channel. Since there is no significant dependence of STI-induced compressive stress for NMOS devices with these two different channel directions, we’ll focus on the device characteristics of PMOSFET hereafter. Figures 2-4(a), (b) depict the characteristics of drain current Id at Vd = -1.2 V and linear transconductance Gm at Vd = -0.05 V between <110>-channel and <100>-channel of 65 nm PMOSFET devices with a La =10 μm and 0.21 μm, accordingly. For the case of the La = 10 μm which no STI-induced strain in the channel region, <100>-channel shows a 37% higher than <110>-channel PMOSFET in Gm. As La shrunk from 10 μm to 0.21 μm, the Gm of <110>-channel device increases about 11% while <100>-channel devices show the. - 27 -.

(46) La-independent characteristics and this results in that the Gm difference between <110>- and <100>-channel PMOSFET is reduced to only 12%. This means that higher compressive stress in the channel region from STI edge can enhance hole mobility of <110>-channel PMOSFET devices. By contract, <100>-channel PMOS is almost free from to the change of STI-induced local compressive strain in the channel region. Figure 2-5 illustrates the hole band structure with two different channel directions to explain these different results between <110>- and <100>-channel PMOSFETs. Figure 2-5(a) depicts the band structure of hole with large La as no STI-induced strain. Unstrained Si has a lager effective mass of heavy hole in <110> than <100> direction so that <100>-channel PMOS device has higher hole mobility and so that higher Gm and drive current than <110>-channel devices. Figure 2-5(b) shows hole band structure under uniaxial STI-induced compressive strain. This strain not only lift the degeneracy in the valance band [17-18], but also to change the band shape of the heavy hole to the “light hole like” in <110> directionc so that this STI-induced uniaxial compressive stress can improve the performance of <110>-channel PMOSFET, while <100>-channel device is independent of this stress so that <100> direction keeps almost the same shape under the local strain. Figure 2-6 (a) shows an Ion (Id at Vg = Vd = -1.2 V) versus Ioff (Id at Vg = 0 V and Vd = -1.2 V) characteristics of 65 nm PMOSFET with La = 10 μm, it should be noted that Ion of <100>-channel PMOSFET is approximately 17% larger than that of <110> under the same Ioff. - 28 -.