3-1 Introduction
In order to circumvent downsizing limitations and realize high-speed and high-performance
scaled complementary metal-oxide-semiconductor (CMOS) devices, novel three-dimensional
(3-D) device structures with a double or surrounded gate such as fin field-effect transistor
(FinFET) [1-3] and vertical metal-oxide-semiconductor field-effect transistor (MOSFET) [4-6]
are widely investigated. These specific structures enable the device channel to be fabricated
on various surface crystal orientations. Since channel mobility is well known to be strongly
dependent on crystal orientation [7-8], the characteristics of devices with various crystal
orientations should be carefully studied to optimize the performance for ultra large-scale
integration (ULSI) technology applications.
It has recently been reported that oxide quality and reliability on a (111) substrate are
slightly better than those on a conventional (100) substrate for ultrathin (< 2 nm) gate oxide
[9]. It was also found that for a thin gate oxide of less than 2 nm, the oxidation rate of a (111)
(111) substrate is also improved [9-10]. The mobility of PMOSFETs on a (111) substrate can
be improved owing to the low hole effective mass of the substrate; however, the low-field
mobility of a (111) NMOSFETs is still less than that of (100) substrate. Therefore, it is very
important to determine how to increase electron mobility in the channel region [11-13] on a
(111) substrate.
In this chapter, we proposed the use of local strained channel techniques on a (111) Si
substrate by depositing a SiN capping layer with high mechanical tensile stress and using the
stack gate of amorphous silicon (α-Si) and polycrystalline silicon (poly-Si) to improve the
performance of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs)
with the <110> channel direction on a (111) substrate. By using these techniques, the
performance improvement of the NMOSFETs in the <110> channel direction on the (111)
substrate was achieved. The on-current and transconductance (Gm) increased with increasing
SiN capping layer or α-Si layer thickness. Our experimental results show that devices with a
700 Å α-Si layer show a 6.7% on-current improvement percentage relative to those with a
200 Å α-Si layer, and a corresponding Gm improvement percentage of 10.2%. In addition,
charge pumping current/interface state density decreased for the samples with a thicker SiN
layer.
3-2 Experiment
A local strained structure with a stack of α-Si layer and a SiN capping layer was fabricated.
The schematic cross section is shown in Fig. 3-1. After BF2 implantation for the p-well region,
the chemical vapor deposition (CVD) of SiO2 for oxidation-enhanced diffusion (OED) in the
well drive-in process was executed. Pad oxide and Si3N4 were deposited and active region
alignment was followed. After Si3N4 etching, BF2 was implanted for the sake of channel stop.
Then, field oxidation was carried out in high-temperature ambience for local oxidation of
silicon (LOCOS) isolation. Two runs of sacrificial oxide growth followed Si3N4 removal to
eliminate the Kooi effect. To adjust the threshold voltage, BF2 was implanted (50 keV, 5x1012).
After RCA cleaning, a 2 nm gate oxide was grown in a vertical furnace (800oC, O2 ambience).
The stacked gate, α-Si (550oC, 20-70 nm) and in-situ-doped n+ poly-Si (550oC) were
deposited in the same ambience. The total thickness of the poly gate for all the samples was
200nm. Poly-Si and α-Si were etched following gate alignment. To prevent leakage around
the gate edge, poly-reoxidation was carried out here. After sidewall polymer removal, wafers
underwent n+-source/drain implantation (As, 20 keV, 5x1015) followed by alignment.
PP+-substrate alignment and implantation (BF , 50 keV, 2.5x102 15) were executed and then rapid
thermal annealing was carried out in nitrogen ambience at 1050oC for 10 s. A thermal CVD
SiN layer (at 780oC) with different thicknesses, 100-300 nm, was directly deposited onto the
transistor, followed by tetraethoxysilane (TEOS) deposition (700oC, 350-450 nm). After
contact alignment, contact etching was carried out by etching TEOS and SiN. At first, we
used dry etching to remove the upper TEOS and then wafer was dipped in a buffer oxide
etchant (BOE) solution in order to confirm that the TEOS was completely removed. After
removing the TEOS, we used another recipe to etch the lower SiN layer. In order to protect
the Si surface from plasma etching damage, the SiN layer was etched using two steps. We
calculated the SiN etching rate. We left a thin SiN layer of about 20 nm after the etching.
Then, we used H PO solution to etch the thin SiN layer. It is necessary to have an
over-etching step in this wet etching process to ensure that the SiN layer is completely
removed. (Ti/TiN/Al/TiN) four-level metallization was then carried out in a physical vapor
deposition (PVD) system, and final alignment was followed. After carrying out metal etching,
annealing in a H / N ambience at 400
3 4
2 2 oC for 30 min was performed in order to mend dangling bonds and reduce the interface state density at the oxide/Si interface.
3-3 Results and Discussions
3-3-1 Single-poly-Si gate structure with SiN capping layer of different thicknesses
Figure 3-2 shows the electrical drain current and drain voltage (Id-Vd) characteristics of the
devices using a single-poly-Si gate with a fixed thickness (2000 Å) and various SiN capping
layer thicknesses on a (111) orientation substrate. The improvement in drain current is
proportional to the thickness of the SiN layers. Since the SiN capping layer can provide
tensile strain in the channel region and thus increase the electron mobility of the devices
fabricated on a conventional (100) orientation substrate [13], this result implies that capping
with SiN has also the same advantage of providing tensile strain in the channel region for
NMOSFETs on the (111) substrate. For the devices on the (100) orientation substrate, this
SiN-capping-layer-induced tensile strain can cause the sixfold degenerate valleys of the
silicon conduction band to split into two degeneracy states: electrons with a longitudinal
effective mass axis perpendicular to the interface in two lowered valleys, and those with a
longitudinal mass axis parallel to the interface in four raised valleys [14-16]. For the
NMOSFETs on the (111) substrate, which also shows sixfold-valley degeneracy [17], this
tensile strain can also induce conduction band splitting and suppress the intervalley transitions
of electrons from lower to upper valleys, thus reducing the intervalley scattering. Furthermore,
in the lower valleys, electrons show a smaller effective mass in transport parallel to the
interface. The combination of the reduced intervalley phonon scattering and the small
effective mass increases electron mobility. The dependence of Gm on SiN capping layer
thickness is shown in Fig. 3-3. Gm increased as SiN capping layer thickness increased. This
result illustrates that capping with thicker SiN layers induced higher tensile strain, improving
the mobility of electrons in NMOSFETs in the channel region on the (111) substrate, which is
consistent with the trend of drain current shown in Fig. 3-1. However, at high vertical field
(high Vg), Gm shows a little decreased as SiN thickness increases. This maybe due to
hydrogen species from NH3 gas exit at channel interface during SiN-capping layer deposited.
As vertical field increases, electrons are attracted more closed to oxide/channel interface, and
the surplus hydrogen species at interface will impact the electrons drift from source to drain.
The thicker SiN-capping layer, the more surplus hydrogen species at channel interface. In
order to analyze our measured data more completely, Fig. 3-4 shows two-dimensional (2-D)
simulation results of the SiN-capping-layer-induced stress along the channel length direction
using the SILVACO simulation tool. The mechanical parameter, that is, the intrinsic stress of
this simulation, is assumed to be 1.4x1010 dynes/cm2 for a nitride film, as reported by Irene
[18]. The device with the thickest SiN capping layer (3000 Å) used in this study showed the
highest tensile stress (negative values for compressive stress and positive values for tensile
stress ) from the corner to the center region of the channel when compared with the samples
with SiN layer thicknesses of 2200 and 1000 Å. The stress simulation results demonstrate that
thicker SiN capping layers can induce higher tensile stresses in the channel region, and
therefore improve the performance of the NMOSFETs fabricated on the (111) substrate.
Figure 3-5 shows the threshold voltages (Vth) of the devices with SiN capping layers of
different thicknesses. For all the devices, except those without a SiN capping layer, the
magnitude of the threshold voltage decreases with increasing thickness of the SiN layers. This
is believed to be due to the effects of band gap narrowing resulting from local strain and the
long processing time for the deposition of thicker SiN films [19]. The charge pumping
currents of the devices with a 0.5 μm gate length and SiN layers of different thicknesses are
shown in Fig. 3-6. The charge pumping currents illustrate the quality of the SiO2/Si interface
after the strain was induced in the channel region. The devices without a SiN capping layer
have the lowest charge pumping current, which indicates that they have the lowest number of
interface traps of all the samples. The capping SiN layer may have also induced more
interface traps at the oxide/Si interface. However, it is interesting that the charge pumping
current decreases when the SiN layer thickness increases above 1000 Å. This implies that
although the SiN capping layer may cause some damage and induces interface traps at the oxide/Si interface, SiN layer deposition may provide some hydrogen species from the NH3
gas that passivate the interface states during the process. Thicker SiN layer capping required
longer processing time; thus, more interface states were passivated.
3-3-2 Stack of -Si and Poly-Si gate with SiN capping layer of fixed thickness
The output characteristics of Id-Vd and Gm for all the devices with a fixed SiN layer
thickness (1500 Å) and various α-Si thickneses in gate construction are shown in Figs. 3-7
and 3-8, individually. The drain current and transconductance increase as the thickness of the
α-Si layer increases. The on-current improvement percentage of the devices with a 700 Å
α-Si layer is 6.7 % relative to that of the devices with a 200 Å α-Si layer, and the
corresponding Gm improvement percentage was 10.2 %. This result implies that there is a
strain dependence of electron mobility enhanced by the stack of the α-Si gate structure. It is
observed that the strain effect between the devices with 500 and 700 Å α-Si layers is not very
strong and this suggests that the strain effect saturates at an α-Si layer thickness of 500 Å.
Figure 3-9 shows the simulated 2-D stress distribution contour of the NMOSFET with a 700
Å α-Si layer on the (111) orientation substrate. The simulation mechanical parameter of
intrinsic stress is assumed to be 1.4x1010 dynes/cm2 and 9x109 dynes/cm2 for the nitride and
α-Si films, respectively. The simulation result shows that tensile strain is induced in the
channel region owing to the stacking of α-Si for the gate structure. The mechanism of the
stress elevation could be as follows: before the dopant activation, the n+-poly gate is in the
amorphous phase owing to the stacking of α-Si and the high-dose implantation of arsenic.
The recrystallization of the amorphous region during rapid thermal annealing leads to n+-poly
gate expansion and residual compressive stress. Therefore, the compressive stress in the
n+-poly gate provides tensile strain to the channel region.
Figure 3-10 shows the threshold voltages of the devices with α-Si layers of different
thicknesses. The threshold voltage of the device with a thick α-Si layer is apparently larger
than that of the device with a thin α-Si layer owing to the wider poly depletion region in the
stack gate structure with a thicker α-Si layer. Since the total thicknesses of all the stack gate
structures are the same (2000 Å), the in-situ doping dose becomes lower when the
in-situ-doped poly-Si layer becomes thinner. After the annealing, the doping concentration of
the stack gate with a thinner poly-Si layer and a thicker α-Si layer is lower than that of the
other stack gates. A lower doping concentration in the gate causes a wider poly depletion
region and a decrease in gate capacitance. As a result, the threshold voltage increases when
the stack gate structure α-Si layer thickness increases.
3-4 Summary
Local strained channel techniques for depositing a SiN capping layer and a stack of α-Si
and poly-Si gate structures on a (111) substrate were investigated in this study. We
demonstrated that the use of the strain structures can improve the performance of NMOSFETs
fabricated in the <110> channel direction on a (111) substrate. The device performance is
further enhanced as the SiN capping layer and α-Si layer become thicker. The stack of α-Si
gate structures also affects the threshold voltages of the gate because of its poly depletion
width. In addition, charge pumping current decreases with increasing split SiN layer thickness.
To optimize these strained conditions, advanced CMOS fabricated on a (111) substrate or
novel 3-D device structures will achieve this advantage more completely and become more
suitable for future ULSI applications.
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Fig. 3-1 Schematic cross section of local strained channel NMOSFET on (111) substrate.
V d (V)
0 1 2 3 4
I d (A)
0.000 0.001 0.002 0.003 0.004
SiN 1000A SiN 2200A
SiN 3000A
V
g-V
t=1.8V
V
g-V
t=1.2V
V
g-V
t=0.6V
Poly-Si = 2000A
W/L = 10/0.5 μm
Fig. 3-2 Electrical Id-Vd characteristics of devices using fixed single-poly-Si thickness (2000
Å) with various SiN capping layer thicknesses on (111) orientation substrate.
Poly-Si = 2000A
V g - V t (V)
0.0 0.1 0.2 0.3 0.4 0.5 0.6
G m (A/V)
0.0001 0.0002 0.0003 0.0004 0.0005
SiN 1000A SiN 2200A SiN 3000A
W/L = 10/0.5 μm
Fig. 3-3 Gm characteristics versus overdrive gate voltage for devices with various SiN capping
layer thicknesses.
Fig. 3-4 2-D simulation results due to SiN-capping-layer-induced stress in channel region
using SILVACO simulation tool. Negative values indicate compressive stress and positive
values indicate tensile stress.
V th (mV)
240 260 280 300 320
w/o SiN
SiN 1000A
SiN 2200A
SiN 3000A Poly-Si = 2000 A
W/L = 10/0.5 μm
Fig. 3-5 Threshold voltages of devices with poly-Si = 2000 Å and different SiN thicknesses.
V base (V)
Fig. 3-6 Charging pumping current curves of devices with different SiN capping layer
thicknesses.
Fig. 3-7 Id-Vd characteristics of devices with different α-Si thicknesses and fixed SiN capping
layer thickness (1500 Å).
Fig. 3-8 Output characteristics of Gm for all devices with fixed SiN thickness (1500 Å) and
various α-Si thicknesses in gate construction.
Fig. 3-9 Simulated 2-D stress distribution contour of NMOSFET with 700 Å α-Si on (111)
orientation substrate.
Fig. 3-10 Threshold voltages of devices with fixed SiN capping layer thickness (1500 Å) and
various α-Si thicknesses.