PMOSFETs
4-1 Introduction
As IC technology enters sub- m dual -gate ultra-large-scale integration (ULSI) generation,
nitrogen atoms are incorporated into silicon dioxide to block an undesirable boron penetration
from a P+ poly-gate electrode of a p-channel metal-oxide-semiconductor field-effect transistor
(PMOSFET) [1-3]. Even for cutting-edge 65 nm complementary metal-oxide-semiconductor
(CMOS) technology, nitrided oxide is still a key gate dielectric material for achieving a high
device performance for both general and low-power applications [4-6]. On the other hand,
devices feature dual gate oxide (DGO) processes in which thin oxide is used for core and
logic circuits and thick oxide is used for input/output (I/O) and analog circuits, owing to the
decreasing size and increasing number of system-on-chip applications. Consequently,
reliability issues, such as negative-bias temperature instability (NBTI) [7-8, 20-21] and
hot-carrier injection (HCI) [9-11], that could induce threshold voltage shift and performance
degradation in DGO PMOSFETs become a serious concern for realizing highly reliable
the gate oxide should be optimized since excessive nitrogen at the interface may induce
interface traps, resulting in a reduced channel carrier mobility [12] and a degraded reliability
[13].
In this study, the impacts of NBTI and HCI on core and I/O PMOSFETs between devices
with plasma nitrided oxide (PNO) and devices with thermally nitrided oxide (TNO) were
compared systematically. The mobility and constant overdrive current of the PMOSFETs
fabricated using PNO as a gate oxide material are about 30% and 23% higher than those of
the devices fabricated using TNO, respectively. The core PMOSFETs fabricated using PNO
show a better NBTI and HCI immunity than those fabricated using TNO owing to the lower
nitrogen concentration at the SiO2/Si-substrate interface. However, the I/O PMOSFETs
fabricated using PNO show a higher HCI-induced degradation rate because of a higher oxide
bulk trap density but a better NBTI than the devices fabricated using TNO at a normal
stressed bias due to a low interface trap density.
4-2 Experiment
PMOS devices were fabricated by state-of-the-art 300 mm wafer foundry technology.
Shallow trench isolation (STI) was performed for devices isolation followed by super-steep
retrograde well formation. After channel implantation, a DGO process was performed with
different gate oxide thicknesses for low-power core and I/O devices. Following the thermal
base oxide growth, plasma nitridation post annealing and poly-silicon deposition steps were
clustered together. The thermally nitrided oxide fabricated by exposing the oxide films to pure
ammonia (NH3) at an atmospheric pressure and high temperatures was used and compared
with plasma nitrided oxide. After lightly-doped drain (LDD) and pocket implantation,
tetraethoxysilane (TEOS) liner and low-temperature silicon nitride were processed in
sequence to form a sidewall spacer. The fabrication of a heavily doped source/drain junction
by BF2 implantation was followed by rapid thermal annealing (RTA) and NiSi self-aligned
silicidation.
Electrical characterizations, which included high-frequency capacitance-voltage (C-V) and
current-voltage (I-V) curves and reliability tests, were performed using a Cascade probe
station S-300, HP4156, and HP4284 system. Charge-pumping current measurements were
also performed to extract the generation of interface states. NBTI stress tests were performed
using a temperature-regulated hot chuck at 125°C, whereas HCI stress tests were performed
under various with varied Vg = Vd stress bias conditions at room temperature.
4-3 Result and Discussions
4-3-1 Material analysis and device performance of PNO and TNO PMOSFETs
Figure 4-1 shows a schematic illustration of nitrided oxide formation processes for both
PNO and TNO. After base oxide growth, PNO and TNO were formed using nitrogen plasma
and NH3 gas, respectively. The high-frequency C-V comparison between the TNO and PNO
of core (1 MHz) and I/O (100 kHz) PMOS devices is shown in Fig. 4-2. The capacitance
equivalent thicknesses measured in the inversion region of C-V (Tox_inv) are about 2.8 and
5.5 nm for low-power core and I/O PMOS devices respectively, for both PNO and TNO
devices. The flat-band voltage difference between PNO and TNO I/O PMOSFETs is about
100mV.
Figure 4-3 shows the nitrogen concentration profiles of PNO and TNO for core devices
analyzed by angle-resolved X-ray photoelectron spectroscopy (ARXPS). From the nitrogen
concentration distribution, it is observed that, unlike TNO that incorporates a high amount of
nitrogen into the SiO2/sub-Si interface [14-16], PNO increases the concentration of nitrogen
near the polycrystalline silicon (poly-Si)/SiO2 interface. The normalized transconductance
(Gm) of core PMOSFET devices as a function of gate overdrive voltage (Vg-Vth) is illustrated
in the inset in Fig. 4-3. From the result, one observes that the hole mobility of PNO is always
higher than that of TNO from a low field to a high field. The peak mobility is 31% higher for
PNO devices. The degradation of the carrier mobility of TNO is attributed to the high
interface trap density at the TNO SiO2/sub-Si interface and/or the enhancement of coulomb
scattering caused by a high nitrogen concentration [17-18]. Consequently, PMOSFET devices
with PNO exhibit a higher driving current than those with TNO. The electrical Id-Vd
characteristics of the PNO and TNO core PMOSFETs are plotted in Fig. 4-4. As a result of the
low nitrogen incorporation into the oxide interface that induced a high mobility in the channel
region, PNO devices exhibit a 23% higher drive current than TNO devices at Vg -Vt = -1.2 V.
4-3-2 NBTI and HCI comparison between PNO and TNO
To study the effects of interface trap density on the NBTI reliability of TNO and PNO
PMOSFETs, a fixed base level charge pumping current measurement, in which a pulse with a
high state voltage is fixed and a varying pulse low base level voltage is applied to the gate,
was performed [19]. Figure 4-5 shows the charge pumping currents of PNO and TNO core
PMOSFETs measured before and after a NBTI 4095 s stress at Vg = -2.5V at 125°C. Note that
in order to remove the leakage current component during the charge pumping measurement,
an incremental frequency charge pumping (IFCP) method [20], in which a correct charge
pumping current is calculated by testing two charge pumping curves at different frequencies,
was used. Both TNO and PNO devices show increasing charge-pumping currents after NBTI
stressing, indicating an enhanced interface trap generation, particularly for TNO PMOSFETs.
Compared with the fresh devices, the increases in charge pumping current after 4095 s NBTI
stressing are 2.86 x 10-10 and 1.99 x 10-10 A for TNO and PNO, respectively. The calculated
interface traps generation (ΔNit) and drain drive current degradation rate obtained by
identical NBTI stress processed are plotted for both core TNO and PNO PMOSFETs, as
depicted in Fig. 4-6. As observed from Fig. 4-6, not only the drain current degradation rate but
also the time dependence of interface trap generation follows a fractional power-law curve,
which is in agreement with the previous literature [15]. Plasma nitridation suppresses the
NBTI-induced drain current degradation. The amount of generated interface traps is lower for
PNO than that of TNO, which is attributed to the low nitrogen concentration at the oxide
interface. In addition, due to the superior capability of nitrogen plasma nitridation to pile up a
high nitrogen concentration at the poly-Si/SiO2 interface, which effectively blocks the
penetration of boron to the SiO2/sub-Si interface, TNO is also more vulnerable to
boron-induced interface trap generation than PNO [21].
Figure 4-7(a) shows the time dependences of the threshold voltage degradation under
various NBTI stress voltages for Core TNO and PNO devices. It is apparent thatΔVth obeys a
power-law dependence on stress time, as given by
ΔVth ∝ t n , (eq. 4-1)
where the exponent value n is found to be 0.25 for both TNO and PNO Core PMOSFETs. A
similar exponent value has been recently reported, generally proving that this time
dependence is due to the diffusion of hydrogen or hydrogen-related species in a
diffusion-controlled electrochemical reaction model [22-23]. For PNO devices, the threshold
voltage degradation by NBTI stress is lower than that for TNO devices under various stress
voltages. To compare with core devices in Fig. 4-7(a), NBTI-induced threshold voltage
degradation as a function of stress time for thick TNO and PNO I/O PMOSFETs are shown in
Fig. 4-7(b). The threshold voltage degradation for both TNO and PNO I/O devices are similar
to that for thin nitrided oxide, indicating the power-law dependence and the PNO immunity to
NBTI that is higher than the TNO immunity under various stress voltages in the range from
-3.5 to -4.5 V.
Although the mean free path of holes in silicon is only about one-half of electrons, the
hot-carrier-induced degradation of PMOSFETs has been critical as that of NMOSFETs.
Figure 4-8(a) illustrates the time dependences of the threshold voltage degradation under
various HCI stress voltages for Core TNO and PNO PMOSFETs at room temperature. Note
that the HCI stress-bias conditions we used hereafter are all for Vg = Vd since the positive
oxide charge generation by hot holes injected into oxide is the most significant mechanism for
deep-submicro-PMOSFETs with nitrided oxide [10]. The HCI-induced threshold voltage
degradation of TNO and PNO Core PMOSFETs follows the power law dependence [eq. (4-1)],
and in the bias range from -2.2 to -2.5 V, the threshold voltage degradation of PNO devices is
always lower than that of TNO devices. The time dependences of the threshold voltage
degradation under various HCI stress voltages from Vg = Vd = -3.5 to - 4.5 V for I/O devices
are shown in Fig.4- 8(b). Although the initial threshold voltage shift of TNO PMOSFETs is
higher than that of PNO PMOSFETs under the same bias conditions, the PNO PMOSFETs
show a markedly higher degradation rate than the TNO PMOSFETs. At an electric oxide field
higher than those mentioned above such as Vg = Vd = -4.5 V, the threshold voltage
degradation of the PNO devices is higher than that of the TNO devices. We will discuss this
result more detail in next section.
4-3-3 Mechanism
Figure 4-9 shows the schematic illustration of the degradation mechanisms at NBTI and HCI stresses for core and I/O PMOSFETs with TNO and PNO, respectively. The exponent
value in eq. (4-1) for the NBTI power law dependence is found to be 0.25 for both TNO and
PNO core devices. This implies that the initial degraded value is strongly dependent on the
number of interface traps for the NBTI of core thin nitrided oxide. On the other hand, for core
PMOSFETs, TNO [Fig. 4-9(a)] shows a higher initial NBTI-induced degradation than PNO
[Fig. 4-9(b)]. This can be attributed to the higher interface trap generation due to the higher
nitrogen concentration at the SiO2/sub-Si interface. In addition, for thick I/O oxide, the
location where the interface traps and fixed positive oxide charges generated at NBTI “static”
stress is relatively near the SiO2/Sub-Si interface; therefore, for the NBTI reliability issue, the
oxide interface quality is markedly more important for thick I/O oxide. This is the reason that
the NBTI-induced degradation of I/O PNO devices [Fig. 4-9(d)] is always lower than that of
I/O TNO devices [Fig. 4-9(c)] under the stress bias conditions in this study.
The degradation mechanism of HCI is different from NBTI. For HCI stress at Vg = Vd,
holes exhibit a high energy owing to impact ionization and are injected into gate oxide
directly. In addition to the interface traps, the oxide bulk traps (Not) are also an important
factor of HCI-induced degradation. However, for thin oxide whose thickness is smaller than 3
nm, the effect of the oxide bulk traps is insignificant and the interface traps are a predominant
factor. For this reason, the core PMOSFETs with TNO show a higher initial degraded value
than the core PMOSFETs with PNO owing to a higher nitrogen concentration at the oxide
interface, but the exponent values for the degradation rate at HCI stress are similar for the
TNO and PNO Core devices. In contrast, for I/O devices with Tox_inv of 5.5 nm, the
plasma-induced oxide traps in the oxide bulk of PNO, when hot holes are injected into oxide,
have a higher probability to be captured, forming charged oxide defects, than those in the
oxide bulk of TNO. Although the initial degraded value of PNO at HCI stress is smaller than
that of TNO owing to the lower number of interface traps, PNO I/O devices show a markedly
higher degradation rate (higher exponent value of power law dependence) owing to a higher
number of oxide traps, which are induced by plasma implantation.
To prove this mechanism, the charge trapping characteristics were measured and are shown
in Fig. 4-10. The normalized gate current density during Fowler-Nordheim (FN) stress at an
electric field of about 10 MV/cm is plotted versus stress time for large-area PMOS capacitors
with core and I/O TNO and PNO, respectively. The normalized gate current density is defined
as (Jg – Jg0) / Jg0, where Jg0 is the initial gate current density of the devices and Jg is the gate
current density after FN stress. As observed, for 5.5-nm-thick I/O oxide, the normalized gate
leakage current density increases with stress time for both TNO and PNO PMOS devices,
whereas PNO shows a higher rate of Jg increase than TNO. This result indicates that for thick
I/O nitride oxide, there are more oxide defect traps in the oxide bulk of PNO, causing a higher
number of holes trapped than in that of TNO. For the thin oxide of core devices, the Jg
increases at constant voltage stress are lower than 1% and are negligible for both TNO and
PNO capacitors. These should be due to the elimination of oxide traps and direct tunneling
being the dominate mechanism for thin oxide. Furthermore, Figure 4-11 shows the electrical
stress-induced leakage current (SILC) phenomena before and after a constant gate bias stress
of 5.5V as functions of positive gate voltages of the TNO and PNO I/O capacitors. From the
evolution of the Jg characteristics during stress, it is observed that PNO exhibits a larger SILC
increase than TNO. Since the SILC has been explained to be due to a trap-assisted tunneling
mechanism occurring in bulk oxide defects [24], the larger SILC of PNO indicates a higher
oxide trap defect density, which is consistent to the proposed mechanism in Fig. 4-9.
The results of this work are summarized in Table 4-1. Owing to a lower interface trap
density, PNO shows higher immunities to HCI and NBTI for core devices and a higher NBTI
immunity for I/O devices when compared with TNO. However, due to the higher oxide trap
density in thick I/O devices for PNO, PNO shows a higher HCI-induced degradation rate than
TNO.
4-4 Summary
In this study, we have performed a systematical investigation of reliability issues, such as
NBTI and HCI, for core and I/O PMOSFETs with TNO and PNO. As a result, the devices
with TNO exhibit a lower NBTI immunity owing to the higher nitrogen concentration at the
SiO2/sub-Si interface than those with PNO, generating more interface traps during NBTI
stress. In contrast, for HCI under the stress conditions of hot-hole injection, bulk oxide traps
are an important factor for device degradation. For thick I/O devices, plasma induces more
oxide traps in the bulk oxide of PNO and HCI induced a higher degradation rate than those for
TNO devices. However, for an oxide thickness smaller than 3 nm in core devices, the effects
of the oxide traps are negligible and interface traps are a predominant factor. This makes Core
PMOSFETs with PNO have a higher immunity to HCI than those with TNO.
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