The effect of post-deposition annealing in the condition of 400°C/120s is not clear. But forming gas annealing (300°C/30min.) is a key process to effective reduce frequency dispersion in strong accumulation and depletion regions and improve the interface quality for all the capacitors.
Overall, TMA/ HfO2 gate dielectric owns the optimumly electrical characteristics because of its high Cmax and weak frequency dispersion in accumulation, depletion, and inversion regimes.
References (Chapter 2)
[1] R. Chau, S. Datta, and A. Majumdar, “Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications,” IEEE Compound Semiconductor Integrated Circuit Symposium, (IEEE, New York, 2005).
[2] K. Brennan, and K. Hess, “High field transport in GaAs, InP, and InAs,”
Solid-State Electron., vol. 27, p. 643, 1984.
[3] H.-S. Kim, I. Ok, M. Zhang, C. Choi, T. Lee, F. Zhu, G. Thareja, L. Yu, and J. C.
Lee, “Ultrathin HfO2 (equivalent oxide thickness = 1.1 nm) metal-oxide-semiconductor capacitors on n-GaAs substrate with germanium passivation,” Appl. Phys. Lett., vol. 88, p. 252906, 2006.
[4] H.-S. Kim, I. Ok, M. Zhang, T. Lee, F. Zhu, L. Yu, and J. C. Lee, “Metal gate-HfO2 metal-oxide-semiconductor capacitors on n-GaAs substrate with silicon/germanium interfacial passivation layers,” Appl. Phys. Lett., vol. 89, p.
222903, 2006.
[5] S. Koveshnikov, W. Tsai, I. Ok, J. C. Lee, V. Torkanov, M. Yakimov, and S.
Oktyabrsky, “Metal-oxide-semiconductor capacitors on GaAs with high-k gate oxide and amorphous silicon interface passivation layer,” Appl. Phys. Lett., vol.
88, p. 022106, 2006.
[6] D. Shahrjerdi, E. Tutuc, and S. K. Banerjee, “Impact of surface chemical treatment on capacitance-voltage characteristics of GaAs metal-oxide-semiconductor capacitors with Al2O3 gate dielectric,” Appl. Phys.
Lett., vol. 91, p. 063501, 2007.
[7] Y. Xuan, H. C. Lin, P. D. Ye, and G. D. Wilk, “Capacitance-voltage studies on
using atomic-layer-deposited Al2O3 gate dielectric,” Appl. Phys. Lett., vol. 88, p.
263518, 2006.
[8] M. M. Frank, G. D. Wilk, D. Starodub, T. Guatafsson, E. Garfunkel, Y. J.
Chabal, J. Grazul, and D. A. Muller, “HfO2 and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition,” Appl. Phys. Lett., vol. 86, p. 152904, 2005.
[9] C. L. Hinkle, A. M. Sonnet, E. M. Vogel, S. McDonnell, G. J. Hughes, M.
Milojevic, B. Lee, F. S. Aguirre-Tostado, K. J. Choi, H. C. Kim, J. Kim, and R.
M. Wallace, “GaAs interfacial self-cleaning by atomic layer deposition,” Appl.
Phys. Lett., vol. 92, p. 071901, 2008.
[10] M. Milojevic, C. L. Hinkle, F. S. Aguirre-Tostado, H. C. Kim, E. M. Vogel, J.
Kim, and R. M. Wallace, “Half-cycle atomic layer deposition reaction studies of Al2O3 on (NH4)2S passivated GaAs(100) surfaces,” Appl. Phys. Lett., vol. 93, p.
252905, 2008.
[11] M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, “Surface passivation of III-V compound semiconductors using atomic-layer-deposition-grown Al2O3,” Appl. Phys. Lett., vol. 87, p. 252104, 2005.
[12] C. H. Chang, Y. K. Chiou, Y. C. Chang, K. Y. Lee, T. D. Lin, T. B. Wu, M. Hong, and J. Kwo, “Interfacial self-cleaning in atomic layer deposition of HfO2 gate dielectric on In0.15Ga0.85As,” Appl. Phys. Lett., vol. 89, p. 242911, 2006.
[13] C. H. Hou, M. C. Chen, C. H. Chang, T. B. Wu, and C. D. Chiang, “Interfacial Cleaning Effects in Passivating InSb with Al2O3 by Atomic Layer Deposition,”
Electrochem. Solid-State Lett., vol. 11, p. D60, 2008.
[14] C. H. Hou, M. C. Chen, C. H. Chang, T. B. Wu, C. D. Chiang, and J.J. Luo,
“Effects of Surface Treatments on Interfacial Self-Cleaning in Atomic Layer Deposition of Al2O3 on InSb,” J. Electrochem. Soc., vol. 155, p. G180, 2008.
[15] H.-S. Kim, I. Ok, M. Zhang, F. Zhu, S. Park, J. Yum, H. Zhao, J. C. Lee, P. majhi, N. Goel, W. Tsai, C. K. Gaspe, and M. B. Santos, “A study of metal-oxide-semiconductor capacitors on GaAs, In0.53Ga0.47As, InAs, and InSb substrates using a germanium interfacial passivation layer,” Appl. Phys. Lett., vol.
93, p. 062111, 2008.
[16] N. Li, E. S. Harmon, J. Hyland, D. B. Salzman, T. P. Ma, Y. Xuan, and P. D. Ye,
“Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 Dielectric,” Appl. Phys. Lett., vol. 92, p. 143507, 2008.
[17] Y. Yuan, L. Wang, B. Yu, B. Shih, J. Ahn, P. C. McIntyre, P. M. Asbeck, M. J.
W. Rodwell, and Y. Taur, “A Distributed Model for Border Traps in Al2O3 – InGaAs MOS Devices,” IEEE Electron Device Lett., vol. 32, p. 485, 2011.
[18] Y. Yuan, B. Yu, J. Ahn, P. C. McIntyre, P. M. Asbeck, M. J. W. Rodwell, and Y.
Taur, “A distributed Bulk-Oxide Trap Model for Al2O3 InGaAs MOS Devices,”
IEEE Trans. Electron Devices, vol. 59, p. 2100, 2012.
Wafer preparation - n(100)InAs
Wafer clean
- acetone (5min.) - isopropanol (5min.) - HCl:H
2O=1:10 (2min.)
TMA 10cyc. pretreatment
Al
2O
3100cyc. deposited by ALD system (250˚C dep.)
PDA (400˚C/120s)
Gate electrode formation (Ti/Pt)
Backside-contact deposition (Au/Ge/Ni)
FGA (300˚C/30min.)
Fig. 2.1 The process flow of the capacitors with different post-deposition thermal treatments.
Fig. 2.2 The device structure with ALD-TMA/Al2O3.
Wafer preparation - n(100)InAs
Wafer clean
- acetone (5min.) - isopropanol (5min.) - HCl:H
2O=1:10 (2min.)
TEMAH 10cyc. pretreatment
HfO
2100cyc. deposited by ALD system (250˚C dep.)
PDA (400˚C/120s)
Gate electrode formation (Ti/Pt)
Backside-contact deposition (Au/Ge/Ni)
FGA (300˚C/30min.)
Fig. 2.3 The process flow of the capacitors with different post-deposition thermal treatments.
Fig. 2.4 The device structure with ALD-TEMAH/HfO2.
Wafer preparation - n(100)InAs
Wafer clean
- acetone (5min.) - isopropanol (5min.) - HCl:H
2O=1:10 (2min.)
TMA 10cyc. pretreatment
HfO
2100cyc. deposited by ALD system (250˚C dep.)
PDA (400˚C/120s)
Gate electrode formation (Ti/Pt)
Backside-contact deposition (Au/Ge/Ni)
FGA (300˚C/30min.)
Fig. 2.5 The process flow of the capacitors with different post-deposition thermal treatments.
Fig. 2.6 The device structure with ALD-TMA/HfO2.
(a)
(b)
Fig. 2.7 (a)(b) Cross-sectional TEM images of as-deposited Pt/Ti/TMA+HfO2/n-InAs gate stack.
InAs Ti/Pt
~ 10nm TMA/HfO
2Ti/Pt TMA/HfO
2~ 10nm
InAs
(a) (b)
(a) (b)
(c) (d)
Fig. 2.9 Multi-frequency C-V maps of Pt/Ti/TMA+Al2O3/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA;
(c) w/ FGA; (d) w/ PDA+FGA.
(a) (b)
(c) (d)
Fig. 2.10 G/Aq0ω-V (a unit of eV-1cm-2) contours of Pt/Ti/TMA+Al2O3/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/ PDA+FGA.
(a) (b)
(c) (d)
Fig. 2.11 Multi-frequency C-V curves of Pt/Ti/TEMAH+HfO2/n-InAs capacitors measured in 100Hz, 1kHz, 10kHz, and 100kHz, at the temperature of
(100), TEMAH/HfO2 100cyc.
as-dep.
(100), TEMAH/HfO2 100cyc.
w/ FGA
(100), TEMAH/HfO2 100cyc.
w/ PDA+FGA
(a) (b)
(c) (d)
Fig. 2.12 Multi-frequency C-V maps of Pt/Ti/TEMAH+HfO2/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a)
(100), TEMAH/HfO2 100cyc.
as-dep.
(100), TEMAH/HfO2 100cyc.
w/ PDA
(100), TEMAH/HfO2 100cyc.
w/ FGA
(100), TEMAH/HfO2 100cyc.
w/ PDA+FGA
Capacitance, C(F/cm2 )
Gate Voltage, Vg (volt) 100 Hz
1 MHz
(a) (b)
(c) (d)
Fig. 2.13 G/Aq0ω-V (a unit of eV-1cm-2) contours of Pt/Ti/TEMAH+HfO2/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/ PDA+FGA.
(a) (b)
(c) (d)
Fig. 2.14 Multi-frequency C-V curves of Pt/Ti/TMA+HfO2/n-InAs capacitors measured in 100Hz, 1kHz, 10kHz, and 100kHz, at the temperature of
(100), TMA/HfO2 100cyc.
as-dep.
(100), TMA/HfO2 100cyc.
w/ PDA
(100), TMA/HfO2 100cyc.
w/ FGA (100), TMA/HfO2 100cyc.
w/ PDA+FGA
(a)
(b) (c)
Fig. 2.15 Multi-frequency C-V maps of Pt/Ti/TMA+HfO2/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) w/ PDA; (b) w/ FGA; (c)
(100), TMA/HfO2 100cyc.
w/ PDA
(100), TMA/HfO2 100cyc.
w/ FGA
(100), TMA/HfO2 100cyc.
w/ PDA+FGA
Capacitance, C(F/cm2 )
Gate Voltage, Vg (volt) 100 Hz
1 MHz
(a)
(b) (c)
Fig. 2.16 G/Aq0ω-V (a unit of eV-1cm-2) contours of Pt/Ti/TMA+HfO2/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) w/ PDA; (b) w/ FGA; (c) w/ PDA+FGA.
(a)
(b) (c)
Fig. 2.17 Multi-frequency C-V maps of different MOS capacitors w/ FGA measured in 100Hz to 1MHz, at the temperature of 300K: (a) TMA/Al2O3; (b)
(100), TEMAH/HfO2 100cyc.
w/ FGA
(100), TMA/HfO2 100cyc.
w/ FGA
Capacitance, C(F/cm2 )
Gate Voltage, Vg (volt)
100 Hz
1 MHz
Table 2.1 The overview of all of the capacitors in frequency dispersionΔC(@Vg = 3V) are compared.
Table 2.2 The overview of all of the capacitors in comparison with Cmax and frequency dispersion ΔC are compared.
Chapter 3
InAs MOSCAPs with TMA/HfO
2High-κ Dielectrics by Various O
2-plasma Treatments during Atomic-Layer-Deposition (ALD) Process
3.1 Introduction
High-k materials have been researched as the alternative gate dielectrics to replace conventional SiO2 in the scaled Si-based device technological generation on account of the exccesive leakage current and degraded reliability [1-5]. HfO2 is a potential gate dielectric for its high dielectric constant (k ~ 25), a relatively wide bandgap (Eg ~ 5.7eV), and good thermal stability in contacting with Si and related materials. In ultrathin regime, for capacitance equivalent thickness (CET), HfO2 has been demonstrated to be compatible with poly-SiGe and TaN gate materials so on [6].
Lately, using NH3 to thermally nitrogenize of Si-based material prior to the atomic-layer-deposition (ALD) of high-k dielectric has been introduced to be effectual in accomplishing low CET and fine reaction barrier between HfO2 and Si-based material [6, 7]. Lai et al. demonstrated the interfacial layer properties of thin Ta2O3 films on bare, NH3, and N2O nitrided Si substrates [8]. Incorporating nitrogen in the interfacial layer utilizing N2O is a promising way to be gate dielectric for scaled-Si MOSFET device techniques as a result of its excellent electrical characteristic and improved reliability compared to the conventional SiO2 film [9]. Also, Kim et al.
reported that nitridated Ge thermally, which formed a germanium oxynitride (GeON)
layer, is an efficacious passivation on Ge surface prior to atomic-layer-deposition (ALD) of HfO2 high-k dielectric [10]. The results revealed that incorporating nitrogen into germanium oxides effectually repress inter-diffusion of components across high-k dielectric/substrate interface during atomic-layer-deposition (ALD) and post-deposition thermal processes [11]. Neverthless, the thermal instability of gemanium oxide limits the process window for the nitridation method of Ge substrate [12]. Moreover, nitridation and PH3 passivation with thermal or plasma process had been utilized in IV-group materials to improve high-k dielectric/substrate interface quality [13].
Up to date, plasma nitridation process is a promising technique to form silicon oxynitride (SiON) as gate dielectric films. The particular characteristic of the process is the marvelous control of the nitrogen concentration and profile at low temperature of substrate (‹400°C) [14,15]. On the other hand, plasma nitridation process and PH3
passivation also had been applied to GaAs MOS structures [16, 17]. But, the effect of any plasma treatment process on the III-Vs surface is not been sufficiently studied.
In this chapter, we report for the first time, in combination with the aforementioned trimethyl aluminum [TMA, Al(CH3)3] precursor pre-deposition treatment and O2-plasma treatment during atomic-layer-deposition (ALD) thin HfO2
high-k dielectric films process displays a manifestly improvement of electrical properties for InAs MOSCAPs.
3.2 Experimental Procedures of Pt/Ti/TMA+HfO
2/n-InAs w/
or w/o O
2-Plasma Treatment
As same as the chapter 2 we mentioned, (100)-oriented n-InAs substrates are prepared with doping concentration of ca. 1x 1017 cm-3 (resistivity ca. 0.002Ω·cm).
Before gate dielectric formation, all of the wafers were pre-cleaned by acetone (ACE), isopropanol (IPA), and dilute HCl (1:10) for 5, 5, 2 min., respectively, to remove the native oxide, the treated wafers were loaded into ALD chamber. In situ trimethyl aluminum [TMA, Al(CH3)3] precursor pre-deposition treatment was done by using 10cycles of TMA/N2 with a period of 0.06s for a TMA pulse and 10s for a N2 pulse.
After that, the HfO2 thin film (TEMAH/N2/H2O/N2 with durations of 0.1/10/0.04/10 s) was grown over 60cycles (which is not same as the previous condition in order to obtain lower EOT for future device) on the bulk InAs at substrate temperature of 250°C. The wafers were kept at the temperature of 250°C during both precursor pretreatment and dielectric deposition process. Tetrakis(ethylmethylamino)hafnium [TEMAH, Hf(N(C2H5)(CH3))4]] and H2O were selected as the Hf metal source and oxidant, respectively. High-purity N2 was applied as a purging gas to remove redundant reactants. As depositing thin HfO2 film in combination with various O2-plasma treatments are investigated in this chapter, which are per 2, 4, 8cycles once 20sec. O2-plasma, and post-deposition O2-plasma treatment (duration of 10min.), and the power of O2-plasma is 300W. The thickness of the HfO2 film estimated from the number of the growth cycles, is approximate 5nm. Then, 50/500 Å Ti/Pt was deposited using sputter system to pattern gate electrode by shadow mask, and then a 500/700/300-Å -thick Au/Ge/Ni layer was deposited as the backside ohmic contact.
Two post-deposition thermal process were similarly examined: (i) post deposition annealing (PDA) by rapid thermal annealing (RTA) at 400°C in a N2
ambient for 120s and (ii) forming gas annealing (FGA) at 300°C in a H2/N2 (5%)
mixed ambient for 30 min.. Optical microscopy exhibited that the gate electrode area of the capacitor was ca. 4 x 10-4 cm2.
The process flow and device structure are displayed in Fig. 3.1, Fig. 3.2.
3.3 Capacitor Characteristics of InAs nMOSCAPs with Various O
2-Plasma Treatments via Different Post-Deposition Thermal Process
The capacitance-voltage and conductance-voltage characteristics of all the capacitors were still measured by using HP4284A LCR meter at the temperature of 300K. Fig. 3.3 displays the multi-frequency C-V properties, Fig. 3.4 presents the multi-frequency C-V maps, and Fig. 3.5 shows the G/Aq0ω-V contours, of w/o O2-plasma treated capacitors, w/o or w/ PDA (400°C/120s) and before or after FGA (300°C/30min.), respectively. Similarly, Fig. 3.6, Fig. 3.7, Fig. 3.8 exhibit the multi-frequency C-V properties, the multi-frequency C-V maps, and the G/Aq0ω-V contours, of 2cyc./plasma treated capacitors, w/o or w/ PDA (400°C/120s) and before or after FGA (300°C/30min.), respectively; Fig. 3.9, Fig. 3.10, Fig. 3.11 present the multi-frequency C-V properties, the multi-frequency C-V maps, and the G/Aq0ω-V contours, of 4cyc./plasma treated capacitors, w/o or w/ PDA (400°C/120s) and before or after FGA (300°C/30min.), respectively; Fig. 3.12, Fig. 3.13, Fig. 3.14 demonstrate the multi-frequency C-V properties, the multi-frequency C-V maps, and the G/Aq0ω-V contours, of 8cyc./plasma treated capacitors, w/o or w/ PDA (400°C/120s) and before or after FGA (300°C/30min.), respectively; and finally, Fig. 3.15, Fig. 3.16, Fig. 3.17 illustrate the multi-frequency C-V properties, the multi-frequency C-V maps, and the
G/Aq0ω-V contours, of post-deposition O2-plasma treated capacitors, w/o or w/ PDA (400°C/120s) and before or after FGA (300°C/30min.), respectively.
As well as we qualitatively define one of the capacitor characteristics through the frequency dispersion ΔC as follows:
ΔC(@Vg = Vmax) = {[Cacc(@100Hz) – Cacc(@1MHz)] / Cacc(@1MHz)} x 100% (3.1) Where ΔC(@Vg = 1.3V) is for w/o O2-plasma treatment, ΔC(@Vg = 2V) is for 2, 4, 8cyc./plasma treatment, and ΔC(@Vg = 1.5V) is for post-deposition O2-plasma treatment. The overview of all of the capacitors in frequency dispersion is shown in Table. 3.1 – Table. 3.3.
3.3.1 C-V and G-V properties of InAs nMOSCAPs w/ PDA
In the beginning, we desire to infer the effect of adopting post deposition annealing. From Fig. 3.3 (a)(b), for w/o O2-plasma treatment, comparing the as-deposited one with w/ PDA one, we find that the capacitance characteristics of w/
PDA one is unapparent, which is mainly due to large gate leak. So, we deduce that there is a critical problem of performing post deposition annealing at 400°C/120s.
Then, from Fig. 3.5 (b), the conductance at low frequency with highly positive and negative Vg of as-deposited one is large. We suppose that the high conductance signal at low frequency with highly positive Vg is due to a huge number of border traps in the high-k dielectrics, and one with highly positive Vg is owing to a high distribution of interface traps. The frequency dispersion ΔC of as-deposited one is 8.42%, is shown in Table. 3.1.
Moreover, from Fig. 3.6 (a)(b), Fig. 3.7 (a)(b), for 2cyc./plasma treatment, contrasting the as-deposited one with to w/ PDA one, we observe that the
than that of w/ PDA one, but the minimum of capacitance Cmin of the as-deposited one is lower than w/ PDA one, that is to say, the gate control of the as-deposited one is much better than that of w/ PDA one. And from Fig. 3.8 (a)(b), the conductance at low frequency with highly positive and negative Vg of as-deposited one is larger than that of w/ PDA one, and we conclude the contours map displays that there are a stronger interface trap response Git and border traps response Gbor for as-deposited one than w/ PDA one. We also note that the minority carrier responses of the two are almost weak. According to the foregoing results, it is probably implied that the higher contribution of interface traps and border traps in as-deposited one than w/ PDA one.
However, it should be examined deeply, too. The frequency dispersion ΔC of as-deposited one (13.2%) is stronger than w/ PDA one (12.7%), is shown in Table.
3.2., which is concordant with the aforesaid.
Furthermore, from Fig. 3.9 (a)(b), Fig. 3.10 (a)(b), for 4cyc./plasma treatment, as-deposited one in comparison with w/ PDA one, is slightly higher in the accumulation capacitance but lower in the inversion capacitance. And the minimum of the capacitance Cmin of as-deposited one is lower than w/ PDA one, which are suggested that the ability of gate control for as-deposited one is greater than w/ PDA one. Then from Fig. 3.11 (a)(b), the conductance at low frequency with highly positive Vg of as-deposited one is larger but lower with negative Vg than w/ PDA one.
We conclude the contours map presents that there are a stronger border traps response Gbor but weaker interface trap response Git for as-deposited one than w/ PDA one. We still note that the minority carrier responses are nearly weak of the two. The frequency dispersion ΔC of as-deposited one (15.1%) is weaker than w/ PDA one (16.2%), is shown in Table. 3.2., which is a little contradictory with the aforesaid. The contradiction is in account of my rough definition of ΔC.
Besides, from Fig. 3.12 (a)(b), Fig. 3.13 (a)(b), for 8cyc./plasma treatment, to make a contrast between as-deposited one and w/ PDA one, the capacitance in the accumulation region of as-deposited one is higher but lower in the inversion region than w/ PDA one. The minimums of the capacitance Cmin are just about the same of the two, which are suggested that the ability of gate control for as-deposited one is greater than w/ PDA one. And from Fig. 3.14 (a)(b), the conductance at low frequency with highly positive Vg of as-deposited one is larger but lower with negative Vg than w/ PDA one. We may judge the contours map exhibits that there are a stronger border traps response Gbor but weaker interface trap response Git for as-deposited one than w/ PDA one. We notice that the minority carrier responses of as-deposited one is weaker than w/ PDA one. The frequency dispersion ΔC of as-deposited one (17.9%) is weaker than w/ PDA one (19.9%), is shown in Table. 3.2., which is still a little contradictory with the foresaid.
Finally, from Fig. 3.15 (a)(b), Fig. 3.16 (a)(b), for post-deposition O2-plasma treatment, to compare as-deposited one with w/ PDA one, we heed that the capacitance in the accumulation regime of as-deposited one is slightly lower but much lower in the inversion regime than w/ PDA one. The minimums of the capacitance Cmin for as-deposited one still much lower than w/ PDA one, which are hinted that the ability of gate control for as-deposited one is greater than w/ PDA one. After that, from Fig. 3.17 (a)(b), the conductance at low frequency with highly positive Vg of as-deposited one is lower than w/ PDA one, which we think the contours map demonstrates that there are a weaker border traps response Gbor for as-deposited one than w/ PDA one. We observe that the minority carrier responses of as-deposited one is weaker than w/ PDA one. The frequency dispersion ΔC of as-deposited one (16.1%) is stronger than w/ PDA one (15.4%), is shown in Table. 3.3., which is still a
We can conclude the effect of post deposition annealing is degrading the ability of gate control apparently, but some samples own better inversion characteristics. So the trend of performing post deposition annealing on our samples is unobvious, then we still proceed to apply another post-deposition thermal process --- forming gas annealing.
3.3.2 The Effect of Forming Gas Annealing on Electrical Characteristics
We applied low temperature 300°C forming gas annealing in a H2/N2 (5%) mixed ambient for 30 minutes to expectably improve the high-k dielectric/interface quality of all the capacitors as well.
In the first instance, from Fig. 3.3 (a)(c), Fig. 3.4 (a)(b), w/ FGA one is slightly higher capacitance in the accumulation regime, and higher in the inversion regime than as-deposited one. Also, w/ FGA one exhibits the better gate control than as-deposited one. And then, from Fig. 3.5 (a)(b), the presence of conductance signal at high frequency with negative Vg of w/ FGA one is much faster than that of w/ PDA one, and we suppose the contours shows that there is a stronger minority carrier response. However, at low frequency with highly positive and negative bias, the conductance of w/ FGA one is larger than as-deposited one. So we observe that the capacitance of w/ FGA one at the inversion bias is larger than the as-deposited one.
The frequency dispersion ΔC of w/ FGA one (9.30%) is stronger than as-deposited one (8.42%), is shown in Table. 3.1, which may reveal the higher number of border traps for w/ FGA one and Fig. 3.5 (a)(b) is also shown to represent it.
Moreover, from Fig. 3.6 (a)(c), Fig. 3.7 (a)(c), Fig. 3.9 (a)(c), Fig. 3.10 (a)(c), Fig. 3.12 (a)(c), Fig. 3.13 (a)(c), of 2, 4, 8 cyc./plasma, respectively, w/ FGA one are
similar Cmax in the accumulation regime and Cmin in the inversion regime. That is to say, the gate control of w/ FGA one is about the same with as-deposited one. But, we find that the dispersion in the accumulation and depletion regimes of w/ FGA one is weaker than as-deposited one, for the capacitors of the three. After that, from Fig. 3.8 (a)(c), Fig. 3.11 (a)(c), Fig. 3.14 (a)(c), the conductance at near zero bias and positive Vg at low frequency of w/ FGA one is smaller than that of as-deposited one, and we suppose the contours shows that the interface traps and oxide traps are reduced, which is consistent with above mentioned phenomenon. The frequency dispersion ΔC of w/ FGA one (12.8%) for 2cyc./plasma is weaker than as-deposited one (13.2%), is shown in Table. 3.2, which may reveal the lower number of border traps for w/ FGA one. The frequency dispersion ΔC of w/ FGA one (14.3%) for 4cyc./plasma is also weaker than as-deposited one (15.1%), and The frequency dispersion ΔC of w/ FGA one (15.8%) for 8cyc./plasma is still weaker than as-deposited one (17.9%), are shown in Table. 3.2 as well.
Besides, from Fig. 3.15 (a)(c), Fig. 3.16 (a)(c), w/ FGA one is slightly higher Cmax in the accumulation regime, but much higher Cmin in the inversion regime, so the gate control of w/ FGA one is worse than as-deposited one. As well w/ FGA one shows weaker frequency dispersion in both the accumulation and depletion bias than as-deposited one, which reveals the oxide and interface quality are improved. From
Besides, from Fig. 3.15 (a)(c), Fig. 3.16 (a)(c), w/ FGA one is slightly higher Cmax in the accumulation regime, but much higher Cmin in the inversion regime, so the gate control of w/ FGA one is worse than as-deposited one. As well w/ FGA one shows weaker frequency dispersion in both the accumulation and depletion bias than as-deposited one, which reveals the oxide and interface quality are improved. From