The Effect of Plasma Treatments on Electrical Characteristics

3.4 Comparison of Different Plasma Treatments

3.4.2 The Effect of Plasma Treatments on Electrical Characteristics

From Fig. 3.26, in contrast of w/ FGA condition and 1 MHz ~ 1 kHz, we note that w/o plasma one has the worst transition ability of C_max to C_min, however, the inversion characteristic is the best. For the post-deposition plasma treatment, it resulted in the large C_max of the capacitor, but the worst inversion properties and frequency dispersion in accumulation (9.73%). The plasma treatment during atomic-layer-deposition process (2cyc./plasma) has the optimum InAs MOS characteristics due to great ability of gate control, weaker frequency dispersion at the bias of accumulation (6.97%), depletion, and inversion region. The frequency dispersion is compared in Table. 3.4.

The effect of plasma treatment on capacitors electrical properties is improving the oxide and interface quality, especially for high number of times in plasma during the process of atomic-layer-deposition.

3.5 Summary

We have investigated the effects on the HfO2/InAs MOS capacitors by utilizing different plasma treatments during or post the process of atomic-layer-deposition. It is observed that there are weak frequency dispersion in the regions of accumulation, depletion, and inversion, for higher number of times in plasma treatment, i.e., 2cy/plasma treatment. This represented that the ability of improving high-k dielectrics

and high-k dielectric/InAs interface quality is great for high number of plasma treatment. By forming gas annealing (300°C/30min.), the high-k dielectrics and high-k dielectric/InAs interface quality were further improved, and InAs MOS capacitors have the good electrical characteristics such as optimum gate control.

References (Chapter 3)

[1] C. H. Lee, H. F. Luan, W. P. Bai, S. J. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L. Kwong, “MOS characteristics of ultra thin rapid thermal CVD ZrO2

and Zr silicate gate dielectrics,” IEEE Int. Electron Device Meet. Tech. Dig., p.

27, 2000.

[2] W. J. Qi, R. Nieh, B. H. Lee, L. Kang, Y. Jeon, K. Onishi, T. Ngai, S. Banerjee, and J. C. Lee, “MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si,” IEEE Int. Electron Device Meet. Tech. Dig., p. 145, 1999.

[3] M. Houssa, V. V. Afanas’ev, A. Stesmans, and M. M. Heyns, “Variation in the fixed charge density of SiOx/ZrO2 gate dielectric stacks during postdeposition oxidation,” Appl. Phys. Lett., vol. 77, p. 1885, 2000.

[4] C. M. Perkins, B. B. Triplett, P. C. Mclntyre, K. C. Saraswat, S. Haukka, and M.

Tuominen, “Electrical and materials properties of ZrO₂ gate dielectrics grown by atomic layer chemical vapor deposition,” Appl. Phys. Lett., vol. 78, p. 2357, 2001.

[5] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations,” J. Appl. Phys., vol. 89, p. 5243, 2001.

[6] R. Choi, C. S. Kang, B. H. Lee, K. Onishi, R. Nieh, S. Gopalan, E. Dharmarajan, and J. C. Lee, “High-quality ultra-thin HfO2 gate dielectric MOSFETs with TaN electrode and nitridation surface preparation,” IEEE Symposium on VLSI Technology, p. 15, 2001.

[7] J. C. Lee, H. J. Cho, C. S. Kang, S. J. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C.

Choi, and M. Abkar, “High-k dielectrics and MOSFET characteristics,” IEEE Int.

Electron Device Meet. Tech. Dig., p. 95, 2003.

[8] Y.-S. Lai, K.-J. Chen, and J. S. Chen, “Investigation of the interlayer characteristics of Ta₂O₅ thin films deposited on bare, N₂O, and NH₃ plasma nitridated Si substrates,” J. Appl. Phys., vol. 91, p. 6428, 2002.

[9] S. Maikap, J.-H. Lee, R. Mahapatra, Samik Pal, Y.S. No, W.-K. Choi, S.K. Ray, and D.-Y. Kim, “Effects of interfacial NH3/N2O-plasma treatment on the structural and electrical properties of ultra-thin HfO2 gate dielectrics on p-Si substrates,” Solid-State Electron., vol. 49, p. 524, 2005.

[10] H. Kim, C. O. Chui, K. C. Saraswat, M.-H. Cho, and P. C. McIntyre, “Interfacial characteristics of HfO2 grown on nitrided Ge (100) substrates by atomic-layer deposition,” Appl. Phys. Lett., vol. 85, p. 2902, 2004.

[11] N. Lu, W. Bai, A. Ramirez, C. Mouli, A. Ritenour, M. L. Lee, D. Antoniadis, and D. L. Kwong, “Ge diffusion in Ge metal oxide semiconductor with chemical vapor deposition HfO2 dielectric,” Appl. Phys. Lett., vol. 87, p. 051922, 2005.

[12] K. Prabhakaran, F. Maeda, Y. Watanabe, and T. Ogino, “Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces,”

Appl. Phys. Lett., vol. 76, p. 2244, 2000.

[13] S. J. Whang, S. J. Lee, F. Gao, N. Wu, C. X. Zhu, L. J. Tang, L. S. Pan, and D. L.

Kwong, “Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH3 and AlN) and HfO2/TaN gate stack,” IEEE Int. Electron Device Meet. Tech. Dig., p. 307, 2004.

[14] H. Niimi and G. Lucovsky, “Monolayer-level controlled incorporation of nitrogen at Si–SiO₂ interfaces using remote plasma processing,” J. Vac. Sci.

Technol. A, vol. 17, p. 3185, 1999.

[15] T. Sugawara, Y. Oshima, R. Sreenivasan, and P. C. McIntyre, “Electrical

grown hafnium-dioxide and plasma-synthesized interface layers,” Appl. Phys.

Lett., vol. 90, p. 112912, 2007.

[16] Y.-H. Jeong, S. Takagi, F. Arai, and T. Sugano, “Effects on InP surface trap states of in situ etching and phosphorus-nitride deposition,” J. Appl. Phys., vol.

62, p. 2370, 1987.

[17] F. Gao, S. J. Lee, R. Li, S. J. Whang, S. Balakumar, D. Z. Chi, C. C. Kean, S.

Vicknesh, C. H. Tung, and D. L. Kwong, “GaAs p- and n-MOS Devices Integrated with Novel passivation (Plasma Nitridation and AlN-surface passivation) techniques and ALD-HfO₂/TaN gate stack,” IEEE Int. Electron Device Meet. Tech. Dig., p. 833, 2006.

 Wafer preparation - n(100)InAs

 Wafer clean

- acetone (5min.) - isopropanol (5min.) - HCl:H

O=1:10 (2min.)

 TMA 10cyc. pretreatment

 HfO

60cyc. deposition in combination with w/o, 2, 4, 8, cyc./20s O

-plasma and post-deposition O

-plasma treatment by ALD system (250˚C dep.)

 PDA (400˚C/120s)

 Gate electrode formation (Ti/Pt)

 Backside-contact deposition (Au/Ge/Ni)

 FGA (300˚C/30min.)

Fig. 3.1 The process flow of the capacitors with different O₂-plasma treatments and post-deposition thermal treatments.

Fig. 3.2 The device structure with ALD-TMA/HfO

(a) (b)

(100), TMA/HfO₂ 60cyc.

w/o O

(100), TMA/HfO₂ 60cyc.

w/o O

(100), TMA/HfO₂ 60cyc.

w/o O

(100), TMA/HfO₂ 60cyc.

w/o O

(a)

(b) (c)

Fig. 3.4 Multi-frequency C-V maps of Pt/Ti/TMA+HfO2/n-InAs capacitors (w/o O2-plasmatreatment) measured in 1kHz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ FGA; (c) w/ PDA+FGA.

(100), TMA/HfO₂ 60cyc.

w/o O

(100), TMA/HfO₂ 60cyc.

w/o O

(a)

(b) (c)

Fig. 3.5 G/Aq0ω-V (a unit of eV^-1cm^-2) contours of Pt/Ti/TMA+HfO2/n-InAs capacitors (w/o O2-plasma treatment) measured in 1kHz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ FGA; (c) w/ PDA+FGA.

(a) (b)

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma as-dep.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ PDA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ PDA+FGA

(a) (b)

(c) (d)

Fig. 3.7 Multi-frequency C-V maps of Pt/Ti/TMA+HfO2/n-InAs capacitors (w/

2cyc./plasma) measured in 100Hz to 1MHz, at the temperature of 300K:

(a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/ PDA+FGA.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma as-dep.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ PDA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ PDA+FGA

Capacitance, C(F/cm2 )

Gate Voltage, V_g (volt) 100 Hz

1 MHz

(a) (b)

(c) (d)

Fig. 3.8 G/Aq₀ω-V (a unit of eV^-1cm^-2) contours of Pt/Ti/TMA+HfO₂/n-InAs capacitors (w/ 2cyc./plasma) measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/

PDA+FGA.

(a) (b)

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma as-dep.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma w/ PDA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma w/ FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma w/ PDA+FGA

(a) (b)

(c) (d)

Fig. 3.10 Multi-frequency C-V maps of Pt/Ti/TMA+HfO2/n-InAs capacitors (w/

4cyc./plasma) measured in 100Hz to 1MHz, at the temperature of 300K:

(a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/ PDA+FGA.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma as-dep.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma w/ PDA

w/ O2 plasma_4cyc./plasma w/ FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma w/ PDA+FGA

Capacitance, C(F/cm2 )

Gate Voltage, V_g (volt) 100 Hz

1 MHz

(a) (b)

(c) (d)

Fig. 3.11 G/Aq₀ω-V (a unit of eV^-1cm^-2) contours of Pt/Ti/TMA+HfO₂/n-InAs capacitors (w/ 4cyc./plasma) measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/

PDA+FGA.

(a) (b)

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma as-dep.

w/ O2 plasma_8cyc./plasma w/ PDA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma w/ FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma w/ PDA+FGA

(a) (b)

(c) (d)

Fig. 3.13 Multi-frequency C-V maps of Pt/Ti/TMA+HfO2/n-InAs capacitors (w/

8cyc./plasma) measured in 100Hz to 1MHz, at the temperature of 300K:

(a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/ PDA+FGA.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma as-dep.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma w/ PDA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma w/ FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma w/ PDA+FGA

Capacitance, C(F/cm2 )

Gate Voltage, V_g (volt) 100 Hz

1 MHz

(a) (b)

(c) (d)

Fig. 3.14 G/Aq₀ω-V (a unit of eV^-1cm^-2) contours of Pt/Ti/TMA+HfO₂/n-InAs capacitors (w/ 8cyc./plasma) measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/

PDA+FGA.

(a) (b)

(c) (d)

Fig. 3.15 Multi-frequency C-V curves of Pt/Ti/TMA+HfO2/n-InAs capacitors (post-deposition O2-plasma treatment for 10min.) measured in 100Hz, 1kHz, 10kHz, and 100kHz, at the temperature of 300K: (a) as-deposited;

(b) w/ PDA; (c) w/ FGA; (d) w/ PDA+FGA.

(100), TMA/HfO₂ 60cyc.

w/ post-dep._O

(100), TMA/HfO₂ 60cyc.

w/ post-dep._O

(100), TMA/HfO₂ 60cyc.

w/ post-dep._O

(a) (b)

(c) (d)

Fig. 3.16 Multi-frequency C-V maps of Pt/Ti/TMA+HfO2/n-InAs capacitors (post-deposition O2-plasma treatment for 10min.) measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA; (c) w/

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

(100), TMA/HfO₂ 60cyc.

w/ post-dep._O

(100), TMA/HfO₂ 60cyc.

w/ post-dep._O

(100), TMA/HfO₂ 60cyc.

w/ post-dep._O

(100), TMA/HfO₂ 60cyc.

w/ post-dep._O

(a) (b)

(c) (d)

Fig. 3.17 G/Aq₀ω-V (a unit of eV^-1cm^-2) contours of Pt/Ti/TMA+HfO₂/n-InAs capacitors (post-deposition O₂-plasma treatment for 10min.) measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/

PDA; (c) w/ FGA; (d) w/ PDA+FGA.

(a)

(b) (c)

Fig. 3.18 Multi-frequency C-V maps of as-deposited Pt/Ti/TMA+HfO2/n-InAs capacitors in comparison with various O2-plasma density treatments measured in 100Hz to 1MHz, at the temperature of 300K: (a)

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma as-dep.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma as-dep.

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma as-dep.

Capacitance, C(F/cm2 )

Gate Voltage, V_g (volt) 100 Hz

1 MHz

(a)

(c) (d)

Fig. 3.19 G/Aq₀ω-V (a unit of eV^-1cm^-2) contours of as-deposited Pt/Ti/TMA+HfO₂/n-InAs capacitors with various O₂-plasma density treatments measured in 100Hz to 1MHz, at the temperature of 300K: (a) 2cyc./plasma; (b) 4cyc./plasma; (c) 8cyc./plasma.

(a)

(a) (c)

Fig. 3.20 Multi-frequency C-V maps of w/ PDA Pt/Ti/TMA+HfO2/n-InAs capacitors with various O2-plasma density treatments measured in 100Hz to 1MHz, at the temperature of 300K: (a) 2cyc./plasma; (b) 4cyc./plasma; (c)

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ PDA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma w/ PDA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma w/ PDA

Capacitance, C(F/cm2 )

Gate Voltage, V_g (volt)

100 Hz

1 MHz

(a)

(b) (c)

Fig. 3.21 G/Aq₀ω-V (a unit of eV^-1cm^-2) contours of w/ PDA Pt/Ti/TMA+HfO₂/n-InAs capacitors with various density O₂-plasma treatments measured in 100Hz to 1MHz, at the temperature of 300K: (a) 2cyc./plasma; (b) 4cyc./plasma; (c) 8cyc./plasma.

(a)

(b) (c)

Fig. 3.22 Multi-frequency C-V maps of w/ FGA Pt/Ti/TMA+HfO2/n-InAs capacitors with various O2-plasma density treatments measured in 100Hz to 1MHz, at the temperature of 300K: (a) 2cyc./plasma; (b) 4cyc./plasma; (c)

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma w/ FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma w/ FGA

Capacitance, C(F/cm2 )

Gate Voltage, V_g (volt) 100 Hz

1 MHz

(a)

(b) (c)

Fig. 3.23 G/Aq₀ω-V (a unit of eV^-1cm^-2) contours of w/ FGA Pt/Ti/TMA+HfO₂/n-InAs capacitors with various O₂-plasma density treatments measured in 100Hz to 1MHz, at the temperature of 300K: (a) 2cyc./plasma; (b) 4cyc./plasma; (c) 8cyc./plasma.

(a)

(b) (c)

Fig. 3.24 Multi-frequency C-V maps of w/ PDA+FGA Pt/Ti/TMA+HfO2/n-InAs capacitors with various O2-plasma density treatments measured in 100Hz to 1MHz, at the temperature of 300K: (a) 2cyc./plasma; (b) 4cyc./plasma;

-2 -1 0 1 2

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ PDA+FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_4cyc./plasma w/ PDA+FGA

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_8cyc./plasma w/ PDA+FGA

Capacitance, C(F/cm2 )

Gate Voltage, V_g (volt)

100 Hz

1 MHz

(a)

(b) (c)

Fig. 3.25 G/Aq₀ω-V (a unit of eV^-1cm^-2) contours of w/ PDA+FGA Pt/TMA+HfO₂/n-InAs capacitors with various O₂-plasma density treatments measured in 100Hz to 1MHz, at the temperature of 300K: (a) 2cyc./plasma; (b) 4cyc./plasma; (c) 8cyc./plasma.

Table. 3.1 The overview of Pt/Ti/TMA+HfO2/n-InAs capacitors (w/o O2-plasma treatment) with different post-deposition thermal processes in frequency dispersionΔC(@Vg = 1.3V) is compared.

Table. 3.2 The overview of Pt/Ti//TMA+HfO2/n-InAs capacitors (w/ various O2-plasma treatment) with different post-deposition thermal processes in frequency dispersionΔC(@Vg = 2V) is compared.

Table. 3.3 The overview of Pt/Ti/TMA+HfO₂/n-InAs capacitors (w/ post-deposition O₂-plasma treatment) with different post-deposition thermal processes in frequency dispersionΔC(@Vg = 1.5V) is compared.

(a)

(b) (c)

Fig. 3.26 Multi-frequency C-V maps of w/ FGA Pt/Ti/TMA+HfO₂/n-InAs capacitors with various O₂-plasma treatments measured in 1 kHz to 1 MHz, at the

(100), TMA/HfO₂ 60cyc.

w/o O

(100), TMA/HfO₂ 60cyc.

w/ post-dep._O

(100), TMA/HfO₂ 60cyc.

w/ O2 plasma_2cyc./plasma w/ FGA

Capacitance, C(F/cm2 )

Gate Voltage, V_g (volt)

1 MHz 1 kHz

Table. 3.4 The overview of w/ FGA Pt/Ti/TMA+HfO2/n-InAs capacitors with various O₂-plasma treatments measured at 1 kHz to 1 MHz in frequency dispersion ΔC(@Vg = 1.5V) is compared.

Chapter 4 The Extraction of Border Traps for InAs MOS Devices by a Distributed Bulk-Oxide Traps Model

4.1 Introduction

In many publications in the literature [1-6], dispersive frequency is observed in the capacitance-voltage (C-V) and conductance-voltage (G-V) data of high-κ/III-V metal-oxide-semiconductor (MOS) devices commonly. The frequency dispersion in the strong accumulation region can’t be clarified by the conventional interface states whose time constant in such bias regime is much shorter than the period of typical measurement frequencies, i.e., 1 kHz - 1 MHz [7], [8]. On the other hand, the trap states inside the high-κ dielectric, which are called border traps or bulk-oxide traps, have long time constants when they interact with the conduction band by way of tunneling [9]. Moreover, as the conventional conductance method [7] for the interface states is adopted to the high to low transition (the maximum slope) of the capacitance-voltage (C-V) data, the dispersive frequency of conductance doesn’t keep up with the well-known peak action. Furthermore, the stretch-out C-V curve comparing with the ideal C-V curve shows that the interface state density far surpass which is extracted from the frequency in such region. Such inconsistency can be resolved by a bulk-oxide trap model in which the low frequency part resulting in C-V curve stretch-out is stronger than the high-frequency part for the frequency dispersion.

In this chapter, the bulk-oxide trap model is completed by superadding integration of bulk-oxide traps density with respect to whole energy for computing the

equivalent admittance. A differential equation is derived and numerically solved to yield frequency-dependent capacitance and conductance of the InAs metal-oxide-semiconductor (MOS) devices. The model is validated and calibrated by HfO2/n(100) InAs MOS experiment data in strong accumulation and depletion regions.

The model can be also applied to explain the stretch-out C-V curve in the MOS devices.

在文檔中利用介面鈍化與電漿處理對原子層沉積二氧化鉿/砷化銦金氧半電容之研究 (頁 74-107)