2.2 Experimental Procedures of InAs nMOSCAPs
2.2.3 ALD-TMA/HfO 2 Growth and Capacitor Fabrication
(100)-oriented n-InAs substrates are prepared with doping concentration of ca. 1 x 1017 cm-3 (resistivity ca. 0.002Ω·cm). Before gate dielectric formation, all of the wafers were pre-cleaned by acetone (ACE), isopropanol (IPA), and dilute HCl (1:10) for 5, 5, 2 min., respectively, to remove the native oxide, the treated wafers were loaded into ALD chamber. In situ trimethyl aluminum [TMA, Al(CH3)3] precursor pre-deposition treatment was done by using 10cycles of TMA/N2 with a period of 0.06s for a TMA pulse and 10s for a N2 pulse. After that, the HfO2 thin film (TEMAH/N2/H2O/N2 with durations of 0.1/10/0.04/10 s) was grown over 100cycles on the bulk InAs at substrate temperature of 250°C. The wafers were kept at the temperature of 250°C during both precursor pretreatment and dielectric deposition process. Tetrakis(ethylmethylamino)hafnium [TEMAH, Hf(N(C2H5)(CH3))4]] and H2O were selected as the Hf metal source and oxidant, respectively. High-purity N2
was applied as a purging gas to remove redundant reactants. The thickness of the HfO2 film estimated from the number of the growth cycles, is approximate 10nm.
Then, 50/500 Å Ti/Pt was deposited using sputter system to pattern gate electrode by shadow mask, and then a 500/700/300-Å -thick Au/Ge/Ni layer was deposited as the backside contact.
Two post-deposition thermal process were examined: (i) post deposition annealing (PDA) by rapid thermal annealing (RTA) at 400°C in a N2 ambient for 120s and (ii) forming gas annealing (FGA) at 300°C in a H2/N2 (5%) mixed ambient for 30 min.. Optical microscopy exhibited that the gate electrode area of the capacitor was ca.
4 x 10-4 cm2.
The process flow and device structure are shown in Fig. 2.5, Fig. 2.6. The cross-sectional TEM images of as-deposited Pt/Ti/TMA+HfO2/n-InAs capacitor are shown in Fig. 2.7.
2.3 Capacitor Characteristics of InAs nMOSCAPs with Different Post-Deposition Thermal Processes
The capacitance-voltage and conductance-voltage characteristics of all the capacitors were measured by using HP4284A LCR meter at the temperature of 300K.
Fig. 2.8 displays the multi-frequency C-V properties, Fig. 2.9 presents the multi-frequency C-V maps, and Fig. 2.10 shows the G/Aq0ω-V contours, of Pt/Ti/TMA+Al2O3/n-InAs capacitors, w/o or w/ PDA (400°C/120s) and before or after FGA (300°C/30min.), respectively. Similarly, Fig. 2.11, Fig. 2.12, Fig. 2.13 exhibit the multi-frequency C-V properties, the multi-frequency C-V maps, and the G/Aq0ω-V contours, of Pt/Ti/TEMAH+HfO2/n-InAs capacitors, w/o or w/ PDA (400°C/120s) and before or after FGA (300°C/30min.), respectively; Fig. 2.14, Fig.
2.15, Fig. 2.16 exhibit the multi-frequency C-V properties, the multi-frequency C-V maps, and the G/Aq0ω-V contours, of Pt/Ti/TMA+HfO2/n-InAs capacitors, w/o or w/
PDA (400°C/120s) and before or after FGA (300°C/30min.), respectively.
We qualitatively define one of the capacitor characteristics through the variation of the capacitance ΔC as follows:
ΔC(@Vg = 3V) = {[Cacc(@100Hz) – Cacc(@1MHz)] / Cacc(@1MHz)} x 100% (2.1) Where ΔC is the frequency dispersion of the accumulation capacitance measured in 1MHz and 100Hz for the Vg = 3V. The overview of all of the capacitors in frequency dispersion is shown in Table. 2.1.
2.3.1 C-V and G-V properties of InAs nMOSCAPs w/ PDA
At first, we confer the effect of applying post deposition annealing. From Fig.
2.8 (a)(b), Fig. 2.9 (a)(b), for TMA/Al2O3, comparing the as-deposited one with w/
PDA one, we find that the capacitance characteristics is similar, but the gate control of as-deposited one is better than w/ PDA one due to its smaller stretch-out curve. Then, from Fig. 2.10 (a)(b), the conductance at high frequency with highly negative Vg of as-deposited one is larger than that of w/ PDA one. We suppose that the conductance at high frequency with highly negative Vg is minority carrier (hole) response (Ginv).
Also, the conductance at low frequency with highly positive Vg of as-deposited one and w/ PDA one are both supposed to the border trap response of the high-k dielectrics. The frequency dispersion ΔC of as-deposited one (8.05%) is weaker than w/ PDA one (8.70%), is shown in Table. 2.1., which may reveal the lower number of border traps for as-deposited one.
Moreover, from Fig. 2.11 (a)(b), Fig. 2.12 (a)(b), for TEMAH/HfO2 contrasting the as-deposited one with to w/ PDA one, we observe that the accumulation and inversion capacitance of as-deposited one at Vg = 3V is much larger than that of w/
PDA one, and minimum of capacitance of the two are about the same, that is to say, the gate control of the as-deposited one is much better than that of w/ PDA one. And from Fig. 2.13 (a)(b), the conductance at high frequency with highly negative Vg of as-deposited one is much larger than that of w/ PDA one, and we suppose the contours shows that there is a strong interface trap response (Git) with Ginv. In other words, the response of Ginv accompanying with Git of as-deposited one is larger than that of w/
PDA one which is consistent with aforementioned one. We also note that there is a stronger frequency dispersion in the inversion regime of as-deposited one than that of
However, it should be examined deeply. The frequency dispersion Δ C of as-deposited one (16.2%) is stronger than w/ PDA one (10.3%), is shown in Table.
2.1., which may reveal the higher number of border traps for as-deposited one.
Furthermore, from Fig. 2.14 (a)(b), for TMA/HfO2, as-deposited one in comparison with w/ PDA one, is lower in the accumulation capacitance and inversion capacitance, but the similar property of band bending transition from Cmax to Cmin, that is to say, the gate control of as-deposited one is better than w/ PDA one. The frequency dispersion ΔC of w/ PDA one is 11.2%, which is presented in Table. 2.1..
But the effect of post deposition annealing is no obvious trend, so we resort to adopt another post-deposition thermal process --- forming gas annealing.
2.3.2 The Effect of Forming Gas Annealing on Electrical Characteristics
We applied low temperature 300°C forming gas annealing in a H2/N2 (5%) mixed ambient for 30 minutes to expectably improve the high-k dielectric/interface quality of all the capacitors.
First of all, from Fig. 2.8 (a)(c), Fig. 2.9 (a)(c), although w/ FGA one is lower capacitance in the accumulation regime, but higher in the inversion regime than as-deposited one. Also, w/ FGA one exhibits a lower value of depletion capacitance Cdep in the depletion regime than as-deposited one, which reveals a smaller value of interface trap capacitance Cit, in another word, the gate control of w/ FGA one is better than as-deposited one. And then, from Fig. 2.10 (a)(c), the presence of conductance signal at high frequency with negative Vg of w/ FGA one is much faster than that of w/ PDA one, and we suppose the contours shows that there is a strong inversion response Ginv. In other words, the larger response of Ginv accompanying with
quicker transition of conductance for w/ FGA one also implies that w/ FGA one has better gate control which is consistent with aforementioned one. The frequency dispersion ΔC of w/ FGA one (5.92%) is weaker than as-deposited one (8.05%), is shown in Table. 2.1., which may reveal the lower number of border traps for w/ FGA one.
Moreover, from Fig. 2.11 (a)(c), Fig. 2.12 (a)(c), w/ FGA one is lower capacitance in the accumulation regime, but about the same in the inversion regime.
And, w/ FGA one shows a lower value of depletion capacitance Cdep in the depletion regime than as-deposited one, which reveals a smaller value of interface trap capacitance Cit, that is to say, the gate control of w/ FGA one is better than as-deposited one. After that, from Fig. 2.13 (a)(c), the conductance at high frequency with negative Vg of w/ FGA one is smaller than that of as-deposited one, and we previously suppose the contours shows that there is interface trap response (Git) with Ginv. So, the response of Ginv accompanying with Git of w/ FGA one is smaller than that of as-deposited one, even the larger response of minority carrier accompanying with quicker transition of conductance for w/ FGA one also implies that w/ FGA one has better gate control which is consistent with aforementioned one. The frequency dispersion ΔC of w/ FGA one (14.2%) is weaker than as-deposited one (16.2%), is shown in Table. 2.1, which may reveal the lower number of border traps for w/ FGA one.
Besides, from Fig. 2.14 (a)(c), w/ FGA one is still lower capacitance in the accumulation regime, but about the same in the inversion regime. As well w/ FGA one shows a lower value of depletion capacitance Cdep in the depletion regime than as-deposited one, which reveals a smaller value of interface trap capacitance Cit, in other words, the gate control of w/ FGA one is better than as-deposited one. The frequency dispersion ΔC of w/ FGA one is 8.89%, which is presented in Table. 2.1.
Overall, the effect of forming gas annealing may improve the performance in reducing the interface traps density and the number of border traps. The exact influence on the capacitor performances is examined later.
2.3.3 The Effect of PDA+FGA on Electrical Characteristics
Then we combine the two post-deposition thermal processes, post deposition annealing (400°C/120s) and forming gas annealing (300°C/30min.). From Fig.
2.8(b)(d), Fig. 2.9 (b)(d), it is observed that w/ PDA+FGA one is lower capacitance in the accumulation region, but higher in the inversion region than w/ PDA one. Also, w/ PDA+FGA one exhibits a lower value of depletion capacitance Cdep in the depletion region and smaller stretch-out curve than w/ PDA one, which reveals a smaller value of interface trap capacitance Cit, that is to say, the gate control of w/
PDA+FGA one is better than w/ PDA one. And then, from Fig. 2.10 (b)(d), the presence of conductance signal at high frequency with negative Vg of w/ PDA+FGA one is much faster than that of w/ PDA one, and we suppose the contours shows that there is a strong minority carrier response. In another word, the larger response of minority carrier accompanying with quicker transition of conductance for w/
PDA+FGA one also implies that w/ PDA+FGA one has better gate control which is consistent with aforementioned one. The frequency dispersion ΔC of w/ PDA+FGA one (6.55%) is weaker than w/ PDA one (8.70%), is shown in Table. 2.1, which may exhibit the lower number of border traps for w/ PDA+FGA one.
In addition, from Fig. 2.11 (b)(d), Fig. 2.12 (b)(d), comparing w/ PDA+FGA one with w/ PDA one, is about the same capacitance in the accumulation area as well as in the inversion area. But, w/ PDA+FGA one still displays a lower value of depletion capacitance Cdep and smaller stretch-out curve in the depletion area than w/
PDA one, which reveals a smaller value of interface trap capacitance Cit, in other words, the gate control of w/ PDA+FGA one is better than w/ PDA one. And then, from Fig. 2.13 (b)(d), the conductance at high frequency with highly negative Vg of w/ PDA+FGA one is approximately the same as that of w/ PDA one, and we can suppose the contours shows that the minority carrier response of w/ PDA+FGA one is around the same as that of w/ PDA one. However, quicker transition of conductance for w/ PDA+FGA one implies that w/ PDA+FGA one has better gate control which is consistent with aforementioned one. The frequency dispersion ΔC of w/ PDA+FGA one (9.80%) is weaker than w/ PDA one (10.3%), is shown in Table. 2.1., which may reveal the lower number of border traps for w/ PDA+FGA one, too.
Furthermore, from Fig. 2.14 (b)(d), Fig. 2.15 (b)(d), w/ PDA+FGA one is still lower capacitance in the accumulation regime, but about the same in the inversion regime. Nevertheless, w/ PDA+FGA one shows a lower value of depletion capacitance Cdep and smaller stretch-out curve in the depletion regime than w/ PDA one, which reveals a smaller value of interface trap capacitance Cit as well, in other words, the gate control of w/ PDA+FGA one is better than w/ PDA one. Finally, from Fig. 2.16 (b)(d), the conductance at high frequency with highly negative Vg of w/
PDA+FGA one is approximately the same as that of w/ PDA one, and we still suppose the contours shows that the Ginv response of w/ PDA+FGA one is around the same as that of w/ PDA one. However, quicker transition of conductance for w/ PDA+FGA one implies that w/ PDA+FGA one has better gate control which is consistent with aforementioned one. The frequency dispersion ΔC of w/ PDA+FGA one (10.5%) is weaker than w/ PDA one (11.2%), is shown in Table. 2.1, which may show the lower number of border traps for w/ PDA+FGA one, too.
In conclusion, we can resolve the effect of forming gas annealing on the
annealing is comparatively unapparent. In order to acquire quantitative definition of border traps density, we resort to a distributed bulk-oxide traps model [17], [18], which is introduced in Chapter 4.
2.4 Comparison of Different High-κ Dielectrics on Electreical Characteristics
From Fig. 2.17 (a)~(c), to compare with the introduced high-κ dielectrics, after forming gas annealing, TMA/Al2O3 has the weakest frequency dispersion in accumulation, depletion, and inversion regions, however, the low κ value brings about the lowest Cmax. Although TEMAH/HfO2 has the highest Cmax and good ability of gate conrtrol due to its high κ value, the frequency dispersion in accumulation, depletion, and inversion regimes is the strongest. As shown in Table. 2.2, TMA/ HfO2 is the optimum dielectric for our MOS device due to its not only high Cmax and good ability of gate conrtrol due to its high κ value, but weak frequency dispersion in accumulation, depletion, and inversion bias condition.
2.5 Summary
The effect of post-deposition annealing in the condition of 400°C/120s is not clear. But forming gas annealing (300°C/30min.) is a key process to effective reduce frequency dispersion in strong accumulation and depletion regions and improve the interface quality for all the capacitors.
Overall, TMA/ HfO2 gate dielectric owns the optimumly electrical characteristics because of its high Cmax and weak frequency dispersion in accumulation, depletion, and inversion regimes.
References (Chapter 2)
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Wafer preparation - n(100)InAs
Wafer clean
- acetone (5min.) - isopropanol (5min.) - HCl:H
2O=1:10 (2min.)
TMA 10cyc. pretreatment
Al
2O
3100cyc. deposited by ALD system (250˚C dep.)
PDA (400˚C/120s)
Gate electrode formation (Ti/Pt)
Backside-contact deposition (Au/Ge/Ni)
FGA (300˚C/30min.)
Fig. 2.1 The process flow of the capacitors with different post-deposition thermal treatments.
Fig. 2.2 The device structure with ALD-TMA/Al2O3.
Wafer preparation - n(100)InAs
Wafer clean
- acetone (5min.) - isopropanol (5min.) - HCl:H
2O=1:10 (2min.)
TEMAH 10cyc. pretreatment
HfO
2100cyc. deposited by ALD system (250˚C dep.)
PDA (400˚C/120s)
Gate electrode formation (Ti/Pt)
Backside-contact deposition (Au/Ge/Ni)
FGA (300˚C/30min.)
Fig. 2.3 The process flow of the capacitors with different post-deposition thermal treatments.
Fig. 2.4 The device structure with ALD-TEMAH/HfO2.
Wafer preparation - n(100)InAs
Wafer clean
- acetone (5min.) - isopropanol (5min.) - HCl:H
2O=1:10 (2min.)
TMA 10cyc. pretreatment
HfO
2100cyc. deposited by ALD system (250˚C dep.)
PDA (400˚C/120s)
Gate electrode formation (Ti/Pt)
Backside-contact deposition (Au/Ge/Ni)
FGA (300˚C/30min.)
Fig. 2.5 The process flow of the capacitors with different post-deposition thermal treatments.
Fig. 2.6 The device structure with ALD-TMA/HfO2.
(a)
(b)
Fig. 2.7 (a)(b) Cross-sectional TEM images of as-deposited Pt/Ti/TMA+HfO2/n-InAs gate stack.
InAs Ti/Pt
~ 10nm TMA/HfO
2Ti/Pt TMA/HfO
2~ 10nm
InAs
(a) (b)
(a) (b)
(c) (d)
Fig. 2.9 Multi-frequency C-V maps of Pt/Ti/TMA+Al2O3/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA;
(c) w/ FGA; (d) w/ PDA+FGA.
(a) (b)
(c) (d)
Fig. 2.10 G/Aq0ω-V (a unit of eV-1cm-2) contours of Pt/Ti/TMA+Al2O3/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/ PDA+FGA.
(a) (b)
(c) (d)
Fig. 2.11 Multi-frequency C-V curves of Pt/Ti/TEMAH+HfO2/n-InAs capacitors measured in 100Hz, 1kHz, 10kHz, and 100kHz, at the temperature of
(100), TEMAH/HfO2 100cyc.
as-dep.
(100), TEMAH/HfO2 100cyc.
w/ FGA
(100), TEMAH/HfO2 100cyc.
w/ PDA+FGA
(a) (b)
(c) (d)
Fig. 2.12 Multi-frequency C-V maps of Pt/Ti/TEMAH+HfO2/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a)
(100), TEMAH/HfO2 100cyc.
as-dep.
(100), TEMAH/HfO2 100cyc.
w/ PDA
(100), TEMAH/HfO2 100cyc.
w/ FGA
(100), TEMAH/HfO2 100cyc.
w/ PDA+FGA
Capacitance, C(F/cm2 )
Gate Voltage, Vg (volt) 100 Hz
1 MHz
(a) (b)
(c) (d)
Fig. 2.13 G/Aq0ω-V (a unit of eV-1cm-2) contours of Pt/Ti/TEMAH+HfO2/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) as-deposited; (b) w/ PDA; (c) w/ FGA; (d) w/ PDA+FGA.
(a) (b)
(c) (d)
Fig. 2.14 Multi-frequency C-V curves of Pt/Ti/TMA+HfO2/n-InAs capacitors measured in 100Hz, 1kHz, 10kHz, and 100kHz, at the temperature of
(100), TMA/HfO2 100cyc.
as-dep.
(100), TMA/HfO2 100cyc.
w/ PDA
(100), TMA/HfO2 100cyc.
w/ FGA (100), TMA/HfO2 100cyc.
w/ PDA+FGA
(a)
(b) (c)
Fig. 2.15 Multi-frequency C-V maps of Pt/Ti/TMA+HfO2/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) w/ PDA; (b) w/ FGA; (c)
(100), TMA/HfO2 100cyc.
w/ PDA
(100), TMA/HfO2 100cyc.
w/ FGA
(100), TMA/HfO2 100cyc.
w/ PDA+FGA
Capacitance, C(F/cm2 )
Gate Voltage, Vg (volt) 100 Hz
1 MHz
(a)
(b) (c)
Fig. 2.16 G/Aq0ω-V (a unit of eV-1cm-2) contours of Pt/Ti/TMA+HfO2/n-InAs capacitors measured in 100Hz to 1MHz, at the temperature of 300K: (a) w/ PDA; (b) w/ FGA; (c) w/ PDA+FGA.
(a)
(b) (c)
Fig. 2.17 Multi-frequency C-V maps of different MOS capacitors w/ FGA measured in 100Hz to 1MHz, at the temperature of 300K: (a) TMA/Al2O3; (b)
(100), TEMAH/HfO2 100cyc.
w/ FGA
(100), TMA/HfO2 100cyc.
w/ FGA
Capacitance, C(F/cm2 )
Gate Voltage, Vg (volt)
100 Hz
1 MHz
Table 2.1 The overview of all of the capacitors in frequency dispersionΔC(@Vg = 3V) are compared.
Table 2.2 The overview of all of the capacitors in comparison with Cmax and frequency dispersion ΔC are compared.
Chapter 3
InAs MOSCAPs with TMA/HfO
2High-κ Dielectrics by Various O
2-plasma Treatments during Atomic-Layer-Deposition (ALD) Process
3.1 Introduction
High-k materials have been researched as the alternative gate dielectrics to replace conventional SiO2 in the scaled Si-based device technological generation on account of the exccesive leakage current and degraded reliability [1-5]. HfO2 is a potential gate dielectric for its high dielectric constant (k ~ 25), a relatively wide bandgap (Eg ~ 5.7eV), and good thermal stability in contacting with Si and related materials. In ultrathin regime, for capacitance equivalent thickness (CET), HfO2 has been demonstrated to be compatible with poly-SiGe and TaN gate materials so on [6].
Lately, using NH3 to thermally nitrogenize of Si-based material prior to the atomic-layer-deposition (ALD) of high-k dielectric has been introduced to be effectual in accomplishing low CET and fine reaction barrier between HfO2 and Si-based material [6, 7]. Lai et al. demonstrated the interfacial layer properties of thin Ta2O3 films on bare, NH3, and N2O nitrided Si substrates [8]. Incorporating nitrogen in the interfacial layer utilizing N2O is a promising way to be gate dielectric for scaled-Si
Lately, using NH3 to thermally nitrogenize of Si-based material prior to the atomic-layer-deposition (ALD) of high-k dielectric has been introduced to be effectual in accomplishing low CET and fine reaction barrier between HfO2 and Si-based material [6, 7]. Lai et al. demonstrated the interfacial layer properties of thin Ta2O3 films on bare, NH3, and N2O nitrided Si substrates [8]. Incorporating nitrogen in the interfacial layer utilizing N2O is a promising way to be gate dielectric for scaled-Si