In metal-oxide-semiconductor (MOS) device, traps in the bulk gate insulator film can interact with mobile carrier in the semiconductor bands via tunneling mechanism.
Fig. 4.1 schematically demonstrates the tunneling mechanism between border traps and conduction band of n-type semiconductor in the accumulation bias. The time constant associated with charge exchange between border traps and semiconductor is dominated by tunneling mechanism that has exponential dependence on the trap distance x from the gate dielectric/semiconductor interface [9-13].
𝜏(𝑥) = 𝑓0𝜏0𝑒2𝜅𝑥
Here, 𝜏0 = (𝑛𝑠𝜎𝑣𝑡ℎ)−1 is the time constant of the interface trap inversely proportional to the carrier density of the semiconductor surface 𝑛𝑠, 𝜎 is the cross-sectional area of the trap, and vth is the carrier thermal velocity. For the other parameters in (3.1) as follows: f0 is the Fermi-Dirac function which a trap occupied by an electron at energy E, and κ is the attenuation coefficient for an energey E wavefunction of an electron decaying due to an energy barrier Ec,ox > E
𝜅 = √2𝑚∗(𝐸𝑐,𝑜𝑥 − 𝐸)/ℏ
(3.1)
(3.2)
m* is the electron effective mass in the gate dielectric film, and Ec,ox is the top energy of the gate dielectric band (tunneling barrier), as shown in Fig. 4.1.
For a given DC bias, the bulk-oxide traps at a certain distance x and energy E change occupancy respond with a small-signal AC modulation. The bulk-oxide traps at energy E ~ Ef are most accountable for the small-signal response in capacitance and conductance. We find that the effects of the bulk-oxide traps at particular depth and energy on the small-signal MOS admittance can be modeled by a series of combining capacitance and conductance. Bulk-oxide traps in an incremental depth Δx at x and incremental energy ΔE at E are symbolized by the incremental capacitance ΔCbt(E, x) and the incremental conductanceΔGbt(E, x) which are linked in series. If the bulk-oxide traps density per volume per energy is Nbt in units of eV-1cm-3, then [7], [9]
Δ𝐶bt(𝐸, 𝑥) = 𝑓0(1 − 𝑓0)𝑞2𝑁bt
𝑘𝑇 𝛥𝐸 𝛥𝑥
ΔCbt(E, x) andΔGbt(E, x) have the relationship in time constant 𝜏(𝑥) Δ𝐶𝑏𝑡(𝐸, 𝑥) / Δ𝐺𝑏𝑡(𝐸, 𝑥) = 𝜏(𝑥) = 𝑓0𝜏0𝑒2𝜅𝑥
In order to integrate for a continuous energy distribution of bulk-oxide traps, incremental capacitanceΔCbt(E, x) and incremental conductanceΔGbt(E, x) in serial connection at a given depth x and energy E must be transfer to the incremental admittanceΔYbt(E, x). For the factor f0(1-f0) is peaked sharply at E = Ef, So the total incremental admittance at depth x is
𝛥𝑌bt(𝑥) = ∫ 1 1
𝑗𝜔𝛥𝐶bt(𝐸,𝑥)+ 1
𝛥𝐺bt(𝐸,𝑥) 𝐸
=𝑞2𝑁btln (1 + 𝑗𝜔𝜏0𝑒2𝜅𝑥) 𝜏0𝑒2𝜅𝑥 𝛥𝑥
Due to a continuous energy distribution of the bulk-oxide trap throughout the gate dielectric thickness, the equivalent circuit of the distributed model in the MOS device (3.3)
(3.4)
(3.5)
is introduced in Fig. 4.2, where the gate dielectric capacitance is divided into an infinite number of serial slices with branches ofΔYbt(x) at different depth x in connection. And here, 𝜖𝑜𝑥 is the permittivity of the gate dielectric and Cs is the semiconductor capacitance.
If we define Y(x) to be the equivalent admittance at the arbitrary point x looking into the semiconductor in Fig. 4.2, the admittance of the next point x +Δx is
𝑌(𝑥 + 𝛥𝑥) = 𝛥𝑌bt(𝑥) + 1 𝑗𝜔𝜖𝛥𝑥𝑜𝑥+ 1
𝑌(𝑥)
To substitute (3.5) forΔYbt(x), the first order terms in Δx then yield a differential equation for Y(x)
𝑑𝑌
𝑑𝑥 = − 𝑌2
𝑗𝜔𝜖𝑜𝑥+𝑞2𝑁btln (1 + 𝑗𝜔𝜏0𝑒2𝜅𝑥) 𝜏0𝑒2𝜅𝑥
There are two boundary conditions, as follows two equations:
{ 𝑌(𝑥 = 0) = 𝑗𝜔𝐶𝑠 𝑌(𝑥 = 𝑡𝑜𝑥) ≡ 𝐺tot+ 𝑗𝜔𝐶tot
Generally, (3.7) needs to be solved numerically to acquire the total admittance seen into semiconductor by gate terminal, that is (3.8).
For typical measurement frequencies of 1 kHz - 1 MHz, 1.4 x 10-6 < 𝜔𝜏0 < 1.4 x 10-3, Ctot varies with ln(1/𝜔) linearly, and Gtot varies with 𝜔, i.e., Gtot / 𝜔 ~ constant.
Constant Gtot / 𝜔 indicate that, for a given bias, the response of the bulk-oxide traps cause a wide dispersive spectrum of frequency in account of their various depth distribution, that is, an obvious distinction from conventional interface traps [7]. For a given frequency of 𝜔 < 1/𝜏0, the depth of the bulk-oxide traps that respond to the AC small-signal can be estimated by making the factor 𝜔𝜏0𝑒2𝜅𝑥 in (3.7) to be unity, that is, 𝑥 ~ (2𝜅)−1ln(1/𝜔𝜏0), which is almost in the range of 0.1~1nm typically.
For 𝜔 = 0 or DC, Fig. 4.2 becomes a purely capacitive circuit model, and (3.7) is reduced to a real part equation for C(x), that is
(3.6)
(3.7)
(3.8) (3.9)
𝑑𝐶
𝑑𝑥= −𝜖𝐶2
𝑜𝑥+ 𝑞2𝑁bt
The boundary condition is C(x=0) = Cs. For uniform distribution of Nbt, (3.10) can be analytically resolved to yield
𝐶(𝑥) = 𝐶0
(𝐶𝑠+ 𝐶0) exp (2𝑞𝑥√𝑁𝜖𝑜𝑥bt) + (𝐶𝑠− 𝐶0) (𝐶𝑠+ 𝐶0) exp (2𝑞𝑥√𝑁𝜖𝑜𝑥bt) − (𝐶𝑠− 𝐶0)
Here, 𝐶0 = 𝑞√𝜖𝑜𝑥𝑁bt. If 2𝑞√𝜖𝑜𝑥𝑁bt >> 1, then C(x = tox) ≈ √𝑞2𝜖𝑜𝑥𝑁bt, which is insensitive to Cs. Of course, this is just only a matter of theoretical interest, however, it would take much longer than the age of the universe to charge up all the bulk-oxide traps in the gate dielectric in practice.
Another interest of the case is in strong accumulation where Cs is very high.
From (3.11), Ctot(DC) ≈ C0coth(C0/Cox), is higher than Cox always. This result is in comparison of the interface state or lumped-circuit border traps model, which don’t generate dispersive spectrum as shorted out by large semiconductor capacitance (Cs).
Therefore, frequency dispersion of capacitance-voltage and conductance-voltage characteristics in accumulation region is a great indicator of distributed bulk-oxide traps.
It is introduced that the parasitic series resistance with the capacitor might let the apparent Ctot lower at high frequencies regions, e.g., 1 MHz so on. We exclude it out as the cause of the frequency dispersion in the measured C-V curve for the dispersive curve still exist as low frequencies as a few kHz, where the parasitic series resistance has no effect on it. Moreover, the estimated spreading resistance in the substrate for about 100μm dot size is less than a few ohms, which is several orders of magnitude smaller than the capacitive reactance at around 1 MHz.
(3.10)
(3.11)