In the beginning, we have discussed the MOSFETs operated in the subtrhesold region. We have found that back-gate reverse bias may cause unexpected large variations of the circuit specifications. The extracted variations in the associated process parameters have been found to follow the inverse square root of the device area.
Step by step, we have found that the mismatch coefficient can be written as a combination of
Vth
A Aγ and . Here the
Vfb
A Aγ and have been already determined according to the mismatch model in subthreshold region. We have also discussed the impact of short channel devices. Because of the importance of series resistance and overlap length, we have taken such parameters into account and have employed specific methods to gain values for both the series resistance and overlap length. Series resistance will be slightly different among the samples due to the variations of the process, especially for large channel width. The overlap length is a rough approximation to stand for the impact on the effective length. Finally, the devices operated in above threshold voltage have been addressed based on the backscattering theory. We have used this theory to establish a new mismatch model. The key point for this model is that how to determine the relationship between r
Vfb
A
c and device size.
Fortunately, we have a reasonable method to explain the mismatch model.
A more suitable model is used for our mismatch model. Indeed, we can find a satisfying result from the figure previously. The drain current model in saturation based on backscattering theory is performed more accurately than the traditional drain current model in nanoscale devices. We successfully use the new mismatch model to reproduce the experimental current mismatch.
References
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[4] M.-J. Chen, J.-S. Ho, and T.-H. Huang, “Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling,” IEEE J. Solid-State Circuits, vol. 31, pp 259-262, 1996.
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“Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE Journal of Solid-State Circuits, vol. sc-21, no. 6, pp.1057-1066, December 1986.
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Electron Devices, vol. 47, no. 4, pp.756-761 ,2000.
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IEDM97-841, 1997.
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Diaz, “Separation of Channel Backscattering Coefficients in Nanoscale MOSFETs.” IEEE Trans. Electron Devices, vol. 51, pp. 1409-1415, September 2004.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 10-9
10-8 10-7 10-6
Vbs=-0.8V Vbs=-0.4V Vbs= 0 V Vbs= 0.4V
Vgs(V) Mean Ids(A)
W=0.13μm L=0.1μm Vds=0.01V
0.0 0.2 0.4 0.6 0.8 1.0 1.2
10-9 10-8 10-7 10-6
Vbs=-0.8V Vbs=-0.4V Vbs= 0 V Vbs= 0.4V W=0.24μm L=0.1μm V
ds=0.01V
Vgs(V) Mean I ds(A)
Fig.1 The drain current versus gate voltage characteristics with back-gate bias as parameter.
10-8 10-7 10-6 10-3
10-2 10-1 100
Standard deviation (I ds)/Mean(I ds)
W=0.13μm L=0.1μm W=0.24μm L=0.1μm W=0.6 μm L=0.1μm W= 1 μm L=0.1μm W= 10 μm L=0.1μm
ID
/(W/L) (A)
Vbs=0V
Fig. 2 Measured standard deviation versus the drain current divided by gate width to length ratio for zero back-gate bias.
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4
Fig. 3 The measured drain current mismatch in weak inversion versus the back-gate bias.
10-9 10-8 10-7 10-6
Standard deviation (Ids)/Mean(Ids) Vbs=-0.8V
Vbs=-0.4V Vbs= 0 V Vbs= 0.4V
Fig. 4 The normalized standard deviation versus the reference current measured from different drawn gate width to length ratio with back-gate forward bias as parameter.
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.34
0.36 0.38 0.40 0.42 0.44 0.46 0.48
Standard deviation (I ds)/Mean(I ds)
W=0.6μm L=0.1μm V
ds=0.01V
σγ =7.55%
σVfb =2.11%
Vbs(V)
Ids
=
3*10-9AExperiment model
Fig. 5 The measured standard deviation in weak inversion versus the back-gate bias. The calculated results from Eq.(9) are also shown for comparison.
0 2 4 6 8 10 12 0.00
0.01 0.02 0.03 0.04 0.05 0.06 0.07
Experiment σV
fb=AVfb/Sqrt(WLeff)
AVfb=0.00534μm
σ Vf b(V/V)
1/Sqrt(WL
eff) (1/μm)
Fig. 6 The measured and calculated standard deviation of the flat-band voltage difference versus the inverse square root of the device area.
0 2 4 6 8 10 12 0.00
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18
Experiment σ γ
:
γ standard deviation / γ mean1/Sqrt(WL
eff) (1/μm) σγ=Aγ/Sqrt(WLeff)
Aγ= 0.01551μm
Fig. 7 The measured and calculated standard deviation of the body effect coefficient difference versus the inverse square root of the device area.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.000000
0.000001 0.000002 0.000003 0.000004 0.000005 0.000006 0.000007 0.000008
G m(mS)
Vgs(V)
Ids(A) W=0.6μm L=0.5μm Vbs=-0.4V
Vth
0.000000 0.000001 0.000002 0.000003 0.000004
Fig. 8-1 Using Gm maximum method to determine Vth and constant current method to determine the Vth1 and DIBL
Fig. 8-2 Mean threshold voltage versus the channel length for different back-gate biases.
0 2 4 6 8 10 12 0.000
0.005 0.010 0.015 0.020 0.025 0.030 0.035
Avth=0.00319 (V*μm)
Vth: Threshold Voltage at Vds
=
0.01VV th Standard Deviation(V)
1/sqrt(WLeff) μm-1 Experiment
Fig. 9 The measured and calculated standard deviation of threshold voltage difference versus the inverse square root of the device area.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V th Standard Deviation (V)
{Tinv(V
Fig. 11 The measured and calculated standard deviation of the difference in threshold
0.045
Fig. 12-1 Fitting under different biases with respect to the results from Eq. (22)
th
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.0000
0.0005 0.0010 0.0015 0.0020 0.0025 0.0030 0.0035 0.0040 0.0045 0.0050
Average for all sizes
STAR Data
A Vth(V*μm)
Vbs(V)
Fig. 12-2 versus V
Vth
A bs from Eq.(22) for each size. Error stars stand for the standard deviation of the distributions.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 10-8
10-7 10-6 10-5 10-4
Vth1
Vth
δVth W=0.6μm L=0.1μm Vbs=0V
Vgs(V) I ds(A)
Vds=0.01V Vds= 1 V
Fig. 13-1 Using constant subthreshold current method to determine the value of DIBL and threshold voltage at Vds=1V.
0.0 0.2 0.4 0.6 0.8 1.0 0.00
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28
W=0.13μm W=0.24μm W= 0.6 μm W= 1 μm W= 10 μm
Mean DIBL(V/V)
L(μm)
Fig. 13-2 Extracted DIBL versus L for different channel widths.
0.0 0.2 0.4 0.6 0.8 1.0 0.02
0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24
W=0.13μm W=0.24μm W= 0.6 μm W= 1 μm W= 10 μm
Mean V th1(V)
L(μm)
Fig. 13-3 Extracted threshold voltage versus L for Vds=1V.
Fig. 14 The histograms of the measured Vth, DIBL and Vth1 for Vbs=0V
0.20 0.21 0.22 0.23 0.24 0.25 0.26
0.00
0.065 0.070 0.075 0.080 0.085 0.090 0.095 0.100 0.105 0.110 0.115 0.00
0.11 0.12 0.13 0.14 0.15 0.16
0.00
0 2 4 6 8 10 12 0.0000
0.0005 0.0010 0.0015 0.0020 0.0025 0.0030
Experiment model
σ2 Vth1(V2 )
1/sqrt(WLeff) (μm-1)
Fig. 15 The measured and calculated square standard deviation of the difference in threshold voltage versus the inverse square root of the device area for Vds=1V.
0 2 4 6 8 10 12 0.00
0.01 0.02 0.03 0.04 0.05 0.06
0.00 0.01 0.02 0.03 0.04 0.05 0.06
Vth1: Threshold Voltage at Vds=1V
V th1 Standard Deviation(V)
1/sqrt(WLeff) μm-1 Experiment
model
Fig. 16 The measured and derived standard deviation of the difference in threshold voltage versus the inverse square root of the device area for Vds=1V.
0 2 4 6 8 10 12 0.00
0.01 0.02 0.03 0.04 0.05 0.06
Avth1=0.00438 (V*μm)---dot
Vth1: Threshold Voltage at Vds=1V
V th1 Standard Deviation(V)
1/sqrt(WLeff) μm-1 model
fitting line
Fig. 17 Fitting under different biases from Eq. (26)
1
Vth
A
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
region because Vgs is insufficiently high and the constant mobility criterion is not satisfied.
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 10-11
10-10 10-9 10-8 10-7
I EDT (A)
Vgs(V)
Model Experiment
Fig. 19 Experimental extraction of the edge direct tunneling current versus gate voltage.
2DEG(2-Dimensional Electron Gas)
n
+n
+l
0 x
k
BT E
C1(V
D= 0 V)
E
C2(V
D≠0V) F
+F
-T’F
-TF
+L
effJ
－(0) J
＋(0)
RF
+R’F
-Fig. 20 Schematic illustration of channel backscattering theory.
Fig. 21 A schematic flowchart for the procedure of extracting rc.
0 2 4 6 8 10 12 0.000
0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045
ADIBL= 0.00335μm
Experiment
DIBL standard deviation (V/V)
1/sqrt(WLeff)
Fig. 22 The experimentally extracted σDIBL versus the inverse square root of gate area.
0 2 4 6 8 10 12 0.00
0.02 0.04 0.06 0.08 0.10
Arc=0.00745 μm
data
σ rc:Standard Deviation(r c)/Mean(r c)
1/sqrt(WL
eff)
Fig. 23-1 The experimentally extracted σrc versus the inverse square root of gate area.
0 2 4 6 8 10 12 14 16 18 20 0.00
0.05 0.10 0.15
σ rc:Standard Deviation(r c)/Mean(r c)
Arc=0.00322 μm
Experiment
1/Leff(μm-1)
Fig. 23-2 The experimentally extracted σrc versus the inverse effective gate length.
0 10 20 30 40 50 60 0.00
0.02 0.04 0.06 0.08 0.10
Arc=0.00202 μm-1.5
σ rc(%)
Experiment
1/[LeffSqrt(W)]
Fig. 23-3 The experimentally extracted σrc versus 1 Leff W .
ig. 24 The measured drain current mismatch versus gate voltage from Eq.(43) and Eq.
Standard deviation (Ids)/Mean(Ids) AVth=0.00319V*μm
Arc=0.00745 μm
Standard deviation (Ids)/Mean(Ids) AVth=0.00319V*μm
Arc=0.00745 μm
ig. 25 The measured drain current mismatch versus gate voltage from Eq.(44) and Eq.
ig. 26 The measured drain current mismatch versus gate voltage from Eq.(45) and Eq.
Vita
姓 名： 周佳弘 Cha-Hon, Chou 性 別： 男
出生日期： 中華民國 七十二年 十二月 二十四日 出 生 地： 彰化市
住 址： 彰化縣彰化市南瑤路 321 號 學 歷： 國立交通大學 電子工程學系
(西元 2002 年 9 月~2006 年 6 月) 國立交通大學 電子所固態組 碩士班
(西元 2006 年 9 月~西元 2008 年 7 月) 經 歷： 大學部半導體元件物理助教
論文題目： 奈米金氧半場效電晶體匹配特性之研究 Matching Properties of Nanoscale MOSFETs