4.1 Constant Mobility Bias Conditions
With the devices scaling down to the deep sub-micrometer region, some phenomenon and factors can’t be neglected for the transport property of semiconductor physics. In this chapter, we will introduce some factors that were neglected in the past and now will be taken into account due to the short channel effect. So we need to extract parameters as source/drain series resistance and the gate-to-source/drain-extension overlap length. This chapter is based on the factors of series resistance and the gate-to-source/drain-extension overlap length.
These two factors really play dominant roles in our model are described below.
First, in order to build a new model, we should extract the value of source-and-drain series resistance. According to the result of the paper [16], a new model of extracting the MOSFET series resistance is cited. This method needs simple dc measurements on a single test device. Experimental demonstration is presented, and on the basis of the MOSFET equivalent circuit, the series resistance leads to excess potential drop, reducing the intrinsic voltage and degrading the drive capacity. As the gate length shrinks, the series resistance becomes a important factor of the total resistance. As the devices scale down, series resistance plays an important role in the circuits.
It is known that the use of previous methods is problematic, and this paper presents a mew method along with experimental demonstration and verification. We know that the relationship exists between the measured channel carrier mobility and the effective silicon vertical electrical field (Eeff) at the SiO2/Si interface [16]. The corresponding Eeff can be expressed as:
eff 1 d 1 i
Si
E Q
ε η
⎛ ⎞
= ⎜ +
⎝ Q ⎠⎟ (27) where εSi is the silicon permittivity, Qd is the depletion charge and Qi is the inversion layer
charge. η is an empirical factor with the values ~2 commonly used for electrons at room temperature. Based on the derivation procedure described elsewhere [17], Eq. (1) can be futher written as:
where Vfb is the flat-bandvoltage and φf is the potential difference between the Fermi level and the intrinsic Fermi level. Both Vfb and φf are essentially unchanged for a single device operated under different biases.
4.2 Extraction of Source/ Drain Series Resistance
By incorporating the constant mobility criterion into the current equation MOSFETs operated in the linear region, the results under different bias conditions are:
d(Vbs1) OX eff (Vbs1)
(
gs(Vbs1) th(Vbs1) 0.5 ds) (
ds ( bs1))
In this experiment, we assumed that the mobility is essentially the same under back-gate bias and considered mobility is the same under high Eeff condition.
In the above formula, the series resistance can be easily achieved. Fig. 18 shows satisfying results for the series resistance and a constant value about 220(Ω-μm) is determined for our model operated in above threshold region.
4.3 Results and Discussions of Extraction of Source/Drain Series Resistance
In order to obtain constant carrier mobility under different bias conditions, a sufficiently high Vgs is necessary to force the mobility to converge toward the universal curve. Then the extracted Rsd values approach constant and no dependency on the Vbs bias can be observed in the high Vgs region as depicted in Fig. 18.
Although the results of different sizes for extraction in the previous work will vary, we still view the results of the series resistant to be constant. This assumption is reasonable for the following model and the variation of series resistance only plays a minor role in the above threshold region. We can prove this by the results of mismatch model in the above threshold.
4.4 Extraction of Gate-to-Source/Drain-Extension Overlap Length
The edge direct tunneling (EDT) [10] of electron from n+ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs has ultrathin gate oxide thickness. It is found that for thinner oxide thickness, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT), and gate-to-substrate tunneling. As a result, the induced gate and drain leakage and drain leakage is better measured per unit gate width. According to [10], an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.
In this work, we explored a dominant off-state leakage component via edge direct tunneling of electron from n+ polysilicon to underlying n-type drain extension for ultrathin gate oxide thickness. With the effective edge-tunneling area (= ), the EDT I-V model reads
A LTN ×W
IEDT =AQfT =L WQfTN T (32) where is the sheet charge of the accumulation layer; is the electron impact frequency on the n
Q f
+ -poly/SiO2 interface; T is the modified transmission probability considering interface reflection factor. Finally, the extracted gate-to-source/drain overlapLTN is
EDT EDT
TN
J I
= L W (33) In order to gain the value of the the gate-to-source/drain-extension overlap length, we had run a simulator to extract the value of the edge direct tunneling current density. In the pursuit of overlap length, we measured the edge direct tunneling current. Straightforward, the value of gate-to-source/drain-extension overlap length can be obtained. The tunneling path extracted was 6nm [18] ( ) wide from the gate edge as can be corroborated in Fig. 19. This is confirmed from the process simulation.
LTN
4.5 Results
In order to confirm the validity of our model, we will take some parameters into consideration and think whether the results of our experiments are accurate or not. When we consider the effective channel length for the mismatch model, we will view the improved results, indicating a better condition than the past model that directly used the mask-level channel length. We will compare the results with those of other papers [18] to verify that the validity of hypotheses. Although the overlap length will be different for different sizes, we assume that an approximate value for LTN is reasonable.
Chapter 5 Mismatch in above Threshold Region
5.1 Backscattering Theory
In the backscattering theory, we use the wave concept to describe the carrier transport in the channel. As stated in backscattering theory [19]-[20], the nanoscale device performance is limited by the injection velocity and the backscattering coefficients. In this study, if the channel is under low electric field conditions, the width of the kBT layer calculated according to its definition is wide enough to be larger than the channel length L. The backscattering coefficient can be presented from
C( eff) L r low E
L λ
= + (34) where λ is the mean-free-path and L is the channel length. When the channel is under high electric field, <L, the backscattering coefficient can be estimated from
r high EC( eff)
= λ
+ (35) In our model, the channel is assumed to be operated under high electric field. In other words, we will discuss the devices operated in the saturation region. From Fig.20, we can derive the drain current easily and the drain current can be written
Ids =W J[ +(0)−J−(0)]=qW F[ +(1−R)−F−(1−R e) −qV kT/ ] (36) where R is the backscattering coefficient and T(=1-R) is the transmission coefficient. In the saturation region, the value of drain voltage will be higher than thermal voltage. So Eq. (36) can be modified as below
Ids =W J[ +(0)−J−(0)]=qWF+(1−rc) (37)