Chapter 2 Subthreshold Operation
2.2 Experimental Subthreshold Operation
In this thesis, we used the capacitance-voltage(C-V) fitting to obtain the parameters as follows: gate oxide thickness=1.27nm, n+ polysilicon doping concentration=1*1020cm-3, and the substrate doping concentration =4*1017 cm-3. The devices under study were n-channel MOSFETs with varying gate widths (W=0.13μm, 0.24μm, 0.6μm, 1μm, and 10μm), and mask gate lengths (LMK=0.065μm, 0.1μm, 0.5μm, and 1μm), fabricated using a state-of-the-art manufacturing process.
The measurement of the current mismatch for identical devices was achieved in terms of the dies on wafer. All dies on wafer contain many n-channel MOS transistors with the same structure. All the data were fabricated using a 65 nm CMOS process. The p-well-to-n+-source bias, Vbs, was fixed with the gate voltage sweeping from 0 V to 1.2 V in a step of 25 mV. Then we recorded and measured the drain current at the same time. All the procedure was performed under four different back-gate biases: -0.8 V, -0.4 V, 0 V, and 0.4 V [5]-[6]. And the drain voltage is fixed as high as 0.01 V in the subthreshold region. The measurement of the current mismatch in this study was achieved through the n-type MOSFET circuit.
The choice for the maximum forward bias is equal to 0.4 V in order to make sure of the action of the gated lateral bipolar transistors. The measured setup contained the HP4156B and a Faraday box was used for shielding the test wafer, all performed in an air-conditioned room with the temperature at 298K. Fig. 1 depicts typical measured I-V characteristic with back-gate bias as a parameter on a single n-channel MOSFET. We operated the MOS devices in the weak region [7].
2.3 Subthreshold Mismatch Model
When the semiconductor surface is in weak inversion (φf <φs< 2φf ) and the gate
voltage is below the threshold voltage, the drain current is based on the diffusion current. In this situation, the drain current is called the subthreshold current [6]:
2 2 The following weak inversion current expression is considered for the derivation of the above model [4]: concentration. From (1) the drain current I
ni
sub can be written as a function of the variances in the associated process parameters
2 ( ) (2 )2 2 ( ) (2 )2 The first and third terms of the right-hand side of (7) can not be neglected because the gate oxide thickness tox scales down and the channel effective doping concentration Na becomes large. Thus, we can obtain a mismatch model:
2 2 2 2
Fig. 2 shows experimental data in terms of
ID
σ versus Ids/(W/L) for zero bias, where
W/L is the gate width to length ratio. Above formulation describes the dependence of
ID
σ on Vbs, realizing that the current mismatch increases with more negatively substrate bias Vbs. On the other hand, an increase in the forward bias Vbs can improve the transistor matching. So the current mismatch in weak inversion [8] [9] is a function of the standard deviation of the difference in Vfb and γ. And we can know that the weak inversion mismatch is independent of the current. Here we can use the constant current to determine Eq. (7) and Eq. (8), as well as the values of current mismatch. The results can be shown in Fig. 3. In order to get the results of size proportionality constants Aγ and , we need to calculate the
Vfb
A σγ and
Vfb
σ for
each size. For instance, the calculated results based on Eq.(9) with σγ =7.55% and
Vfb
σ =2.11% have been found to be capable of appropriately reproducing the measured data as depicted in Fig. 5.
We concluded that the mismatch model for the subthreshold region can be affected by the back-gate bias and body effect coefficient. And we know that with the Vbs decreasing, the matching property would be gotten worse. This part can be proved from Fig. 4. Essentially, we assumed that the drain current mismatch will be different for different gate biases. The experimental results are useful for the circuits operated in the low power devices.
By substituting the gate oxide thickness, flat-band voltage and the doping concentration into Eq. (9), data from twenty ratios of different gate width to length in Fig. 4 have been reproduced over the back-gate forward bias range illustrated. The corresponding extracted variations in process parameters Vfb and γ versus the inverse square root of the device area are plotted in Fig. 6 and Fig. 7. Empirically, we have the formulas which follow
the inverse square root of the device area, in agreement with [2]. where the Leff can be represented by the following formula
Leff =LMK − ΔL2 (11) In the above formula, we suggested that there will be the same LΔ at both ends of source and drain. Here LMK is the mask-level channel length. The value of LΔ will be extracted by the method of the edge direct tunneling and there LΔ will be called [10]. This part had been addressed in Chapter 4.
LTN
Aγ and are the size proportionality constants for
Vfb
A σγ and
Vfb
σ , respectively. The extracted values of Aγ= 0.01551μm and =0.00534μm are shown in Fig. 6 and Fig. 7. Therefore, the combination of (9) and (10) can serve as an analytic design tool for properly calculating the mismatch with back-gate forward bias and device size both as input parameters. With the variation of different sizes, the parameters
Vfb
A
Aγ and will be constants. To put it forward, this assumption can provide us with the characteristics in the circuits with the aim of designing a reasonable circuit with reasonable matching property [11] [12]. According to the results the safe region can be created for design guidelines.
Vfb
A
2.4 Conclusion for Devices Operated in Subthreshold
The on-chip n-type MOSFET circuits having different drawn gate width to length ratios with a large sample number ( 25) have been extensively measured over a small back-gate forward bias range. The MOS transistors with substrate-to-source junction slightly forward biased acts as a high gain gated lateral bipolar transistor in low level injection. Experiment has exhibited that the drain current mismatch occurs in weak inversion, especially for the
≥
small size devices. An analytic mismatch model has been developed and has successfully reproduced the extensively measured data. The extracted variations in the underlying process parameters have been found to follow the inverse square root of the device area. The work of optimizing the trade-off between the match criterion and the device size with back-gate forward bias as design parameter has been demonstrated based on the model.
With the aid of this model, the current mismatch can be expressed as a function of the variations in process parameters, namely the flat-band voltage and body effect coefficient.
The extracted variations are shown to follow the inverse square root of the device area.
Examples have been given to demonstrate that the model is capable of serving as the quantitative design tool for the optimal design between the mismatch criterion and device size with the back-gate forward bias as a parameter.
Chapter 3 Random Threshold Voltage Fluctuation
3.1 Fluctuation Model
As MOSFETs are scaled down, the applied voltage is being steadily lowered to reduce the power consumption and keep the reasonable reliability. Therefore, we pay more attention to the fluctuation of the device characteristics due to the sensitivity of the systems [11]. In this work, we will repeat some work from the Takeuchi’s paper [13] and this method will pave a way for the future work. By the way, we make use of the data created in this work.
Among the sources of the fluctuation, the random placement of impurity atoms is important [14], because it will cause substantial spread in threshold voltage. Of course, this problem cannot be eliminated by simply improving the process technology. And all the effects increase as the devices become smaller.
The vertical electric field in this model is a function of depth x in the channel region.
A charge sheet is added within the channel depletion layer. The voltage drop between the surface and the depletion region is assumed to a constant. Hence, the relationship between threshold voltage and the charge sheet can be shown as a function of depth :
ΔQ Assuming that the impurity number distribution in the charge sheet volume is binomial, the standard deviation of QΔ will be
where the Nsub( ) is doping concentration. The standard deviation of the threshold voltage can be obtained by integrating the contributions of the charge sheets from =0 to =W
x
where Neff is a weighted average of Nsub( ) defined as x
Threshold voltage formula is written as following : th fb s eff dep
The coefficient BVth [9] can be introduced as below
( )
In this thesis, threshold voltage was obtained from gm maximum method and results are shown in Fig. 8-1 and Fig. 8-2. If (σ V )th is caused solely by ideal dopant fluctuation, BVth
should be constant regardless of electrical gate oxide thickness and threshold voltage. In this part, we can gain the result from Fig. 10.
It is well known that standard deviation of Vth commonly satisfies the relationship
( th) Vth
eff
V A
σ = WL (19) Due to the difference in the settings of Tox and Vth, AVth differs substantially. Results of Eq.
(19) are shown in Fig. 9. However, the fluctuation model has offered an effective way to compare and analyze various kinds of transistors produced by different process conditions.
On the other hand, the substrate bias dependence of threshold voltage standard deviation is also properly normalized based on the fluctuation model. In this case, the effects of the back-gate forward bias can be produced according to the fluctuation model and the trend agrees with our data. Fig. 11 shows that the size proportionality constant increases as reversal
bias increases in magnitude. This is well known for variance under change of back-gate bias and we will use this characteristic to complete the following work.
In the above statements, we assume that the threshold voltage fluctuation is based on the impurity in the channel region. In fact, the gate oxide thickness is also a significant factor in this model. In other words, as MOSFETs are scaled down to deep submicrometer feature size the intrinsic spreading in various parameters also plays an important part in the matching performance of supposedly identical transistors. Especially for the N-FETs, there are many possible mechanisms of variations. For example, flat band voltage variation, gate oxide thickness and extra factors will be an uncertainty in the model. However, we pay attention to the difference between Pelgrom’s model [2] and fluctuation model. This is the comparison on the behavior in the threshold voltage with the effect of back-gate bias taken into accout. The results are shown from Fig. 9 and Fig.10.
3.2 Using Extractions of Mismatch Coefficients Aγ and to Derive
fb th
AV AV
It is a different aspect for us to understand the phenomena of the fluctuation of threshold
voltage [15]. We had known that the property of the threshold voltage fluctuation was discussed for many decades, and many people had tried a variety of methods to gain the model in order to obtain reasonable results. The fluctuation model is only an expression to alternationally understand another view for the variation of threshold voltage. Now we have another method to support the extracted values of the Aγ and . We will give attention to the details at the present time.
Vfb
A
First, the formula of threshold voltage can be derived as
Vth =Vfb +φs +γ φs −Vbs (20) In this work, we have extracted the parameter in the subthreshold region and the φs is the
surface potential assumed to be equal to 1.5φf in this situation. A series of subthreshold data in Fig. 4 were transformed via Eq. (9) into the body effect coefficient mismatch σγ and flat-band voltage mismatch
Vfb
σ . Of course, we can observe all the effects for size proportionality constant for threshold voltage under different back-gate biases.
In the previous work, we applied the inverse square root of area law and obtained the proportionality constants Aγ and Therefore, we can make some assumptions according to the results such as to produce a physical model. Using the results of extraction for different parameters can bring interesting insights into observe the mismatch model. We can achieve good reproduction of data on the basis of our model.
V . Afb
Second, we will discuss the random threshold voltage fluctuation as well as the fluctuation mechanisms for the N-MOSFETs. The extractions of the threshold voltage and DIBL in each microscopically different transistors are carried out in the subthreshold at low drain voltages. On the other hand, in order to clarify the phenomena about the relationship between parameters, the results will be compared with the model adopted from the Takeuchi’s paper [5].
According to the work we had done, we can find that threshold voltage is also described by formula (1). Assuming that the correlation coefficient for the flat-band voltage and body effect coefficient is negligibly ignored, strikingly the following physically based relation remains valid:
And we can simplify the above formula according to the proportionality constants ,
Vth
A Aγ and . The proportionality constant can be written as
fb th
2
th fb
AV AV
A2V =V2fbA2V +γ2∗(1.5φf −Vbs)A γ (22)
where the unit of is
Vth
A Viμmand the units of Aγ and are
Vfb
A μm. In this case, the effects of back-gate bias can also be observed. The results are shown in Fig. 12-1. We can find that as the reverse bias increases, the proportionality constant increases simultaneously. This result is reasonable according to formula (22) and we can achieve a new way to predict the influence of the bias.
Vth
A
When we employed almost all our time in research, something may be left behind in a hurry. To insure the reliability of our model, we can try another method to prove the relationship between parameters. As a result, an extraordinary fitting line between the measured and predicted variance is obtained for regions of operation and for a very wide range of transistor sizes, including minimum channel length transistors. In our point of review, this method is a new way to predict the proportionality constant , as shown in Fig. 12-2.
That is, we only need to use a single sample to determine the , although we still need to gain the values of
Vth
A
Vth
A
Aγ and . This is also a trivial process to attain the results. But we have reached that this process is possible with different back-gate biases applied. This is the satisfying result along with assumptions consistent with the previous work.
Vfb
A
3.3 Effect of DIBL on Threshold Voltage
DIBL was defined as the threshold-voltage shift divided by the drain voltage change. In our case, DIBL can be expressed as follows
1 1 0 where the form in our research is simplified to at the condition of drain voltage of 0.01V as usual. In Fig.13-1 and Fig. 13-3 the is extracted under V
work, we employ a maximum trans-conductance method in the linear region to assess quasi-equilibrium threshold voltage as shown in Fig. 8 and the constant subthreshold current
method in the saturation region to extract the DIBL as shown in Fig. 13-1 and Fig. 13-2.
Fig. 14 shows the histogram of the threshold voltage under different drain biases and DIBL.
In the work, we will discuss the matching model for the DIBL and threshold voltage further. Simultaneously, we can write the formula as follows
Vth1(Vds1)=DIBL∗
(
Vds0 −Vds1)
+Vth(vds0) (24) According to Eq. (1), we can derive the mismatch model as follows(25)
where . The results are shown in Fig. 15. We can see that the matching property of threshold voltage can be written as a function of DIBL and threshold voltage. In order to make most use of our data, we had better to retain the accuracy of our model.
Therefore, we can simplify Eq. (25), leading to as below simulate the value of size proportionality constants for the standard deviation of threshold voltage under V
AV
ds=1 V. Indeed, we can observe that the results are expected as inferred from Fig. 16 and Fig. 17.
3.4 Conclusion
In this chapter, we discuss main parameters about threshold voltage and DIBL. We have compared the results between the fluctuation model and the traditional model. It is obvious that the fluctuation model can offer a way to see the changes in under different biases and manufacturing processes. Traditional model is still used to complete our model in the subsequent work. On the other hand, we can consider the effect of DIBL on the threshold
AV
voltage. With channel length scaling down, it is gradually important to discuss short-channel effects such as roll-off of threshold voltage and drain-induced-barrier-lowering. Fig. 13-2 shows that DIBL increases dramatically as the channel length decreases. That is, we may not use the constant current method to determine value of DIBL and Vth1. The results may impose a problem as the gate length scales down to 50nm and beyond. Fig. 13-3 also shows the same obstacle as the channel length decreases. In such a condition, we can not extract the accurate
Vth1. This phenomena is a big challenge needed to overcome.
Chapter 4 Extraction of Series Resistance and Overlap Length
4.1 Constant Mobility Bias Conditions
With the devices scaling down to the deep sub-micrometer region, some phenomenon and factors can’t be neglected for the transport property of semiconductor physics. In this chapter, we will introduce some factors that were neglected in the past and now will be taken into account due to the short channel effect. So we need to extract parameters as source/drain series resistance and the gate-to-source/drain-extension overlap length. This chapter is based on the factors of series resistance and the gate-to-source/drain-extension overlap length.
These two factors really play dominant roles in our model are described below.
First, in order to build a new model, we should extract the value of source-and-drain series resistance. According to the result of the paper [16], a new model of extracting the MOSFET series resistance is cited. This method needs simple dc measurements on a single test device. Experimental demonstration is presented, and on the basis of the MOSFET equivalent circuit, the series resistance leads to excess potential drop, reducing the intrinsic voltage and degrading the drive capacity. As the gate length shrinks, the series resistance becomes a important factor of the total resistance. As the devices scale down, series resistance plays an important role in the circuits.
It is known that the use of previous methods is problematic, and this paper presents a mew method along with experimental demonstration and verification. We know that the relationship exists between the measured channel carrier mobility and the effective silicon vertical electrical field (Eeff) at the SiO2/Si interface [16]. The corresponding Eeff can be expressed as:
eff 1 d 1 i
Si
E Q
ε η
⎛ ⎞
= ⎜ +
⎝ Q ⎠⎟ (27) where εSi is the silicon permittivity, Qd is the depletion charge and Qi is the inversion layer
charge. η is an empirical factor with the values ~2 commonly used for electrons at room temperature. Based on the derivation procedure described elsewhere [17], Eq. (1) can be futher written as:
where Vfb is the flat-bandvoltage and φf is the potential difference between the Fermi level and the intrinsic Fermi level. Both Vfb and φf are essentially unchanged for a single device operated under different biases.
where Vfb is the flat-bandvoltage and φf is the potential difference between the Fermi level and the intrinsic Fermi level. Both Vfb and φf are essentially unchanged for a single device operated under different biases.