Chapter 2 Subthreshold Operation
3.1 Fluctuation Model
3.1 Fluctuation Model
As MOSFETs are scaled down, the applied voltage is being steadily lowered to reduce the power consumption and keep the reasonable reliability. Therefore, we pay more attention to the fluctuation of the device characteristics due to the sensitivity of the systems [11]. In this work, we will repeat some work from the Takeuchi’s paper [13] and this method will pave a way for the future work. By the way, we make use of the data created in this work.
Among the sources of the fluctuation, the random placement of impurity atoms is important [14], because it will cause substantial spread in threshold voltage. Of course, this problem cannot be eliminated by simply improving the process technology. And all the effects increase as the devices become smaller.
The vertical electric field in this model is a function of depth x in the channel region.
A charge sheet is added within the channel depletion layer. The voltage drop between the surface and the depletion region is assumed to a constant. Hence, the relationship between threshold voltage and the charge sheet can be shown as a function of depth :
ΔQ Assuming that the impurity number distribution in the charge sheet volume is binomial, the standard deviation of QΔ will be
where the Nsub( ) is doping concentration. The standard deviation of the threshold voltage can be obtained by integrating the contributions of the charge sheets from =0 to =W
x
where Neff is a weighted average of Nsub( ) defined as x
Threshold voltage formula is written as following : th fb s eff dep
The coefficient BVth [9] can be introduced as below
( )
In this thesis, threshold voltage was obtained from gm maximum method and results are shown in Fig. 8-1 and Fig. 8-2. If (σ V )th is caused solely by ideal dopant fluctuation, BVth
should be constant regardless of electrical gate oxide thickness and threshold voltage. In this part, we can gain the result from Fig. 10.
It is well known that standard deviation of Vth commonly satisfies the relationship
( th) Vth
eff
V A
σ = WL (19) Due to the difference in the settings of Tox and Vth, AVth differs substantially. Results of Eq.
(19) are shown in Fig. 9. However, the fluctuation model has offered an effective way to compare and analyze various kinds of transistors produced by different process conditions.
On the other hand, the substrate bias dependence of threshold voltage standard deviation is also properly normalized based on the fluctuation model. In this case, the effects of the back-gate forward bias can be produced according to the fluctuation model and the trend agrees with our data. Fig. 11 shows that the size proportionality constant increases as reversal
bias increases in magnitude. This is well known for variance under change of back-gate bias and we will use this characteristic to complete the following work.
In the above statements, we assume that the threshold voltage fluctuation is based on the impurity in the channel region. In fact, the gate oxide thickness is also a significant factor in this model. In other words, as MOSFETs are scaled down to deep submicrometer feature size the intrinsic spreading in various parameters also plays an important part in the matching performance of supposedly identical transistors. Especially for the N-FETs, there are many possible mechanisms of variations. For example, flat band voltage variation, gate oxide thickness and extra factors will be an uncertainty in the model. However, we pay attention to the difference between Pelgrom’s model [2] and fluctuation model. This is the comparison on the behavior in the threshold voltage with the effect of back-gate bias taken into accout. The results are shown from Fig. 9 and Fig.10.
3.2 Using Extractions of Mismatch Coefficients Aγ and to Derive
fb th
AV AV
It is a different aspect for us to understand the phenomena of the fluctuation of threshold
voltage [15]. We had known that the property of the threshold voltage fluctuation was discussed for many decades, and many people had tried a variety of methods to gain the model in order to obtain reasonable results. The fluctuation model is only an expression to alternationally understand another view for the variation of threshold voltage. Now we have another method to support the extracted values of the Aγ and . We will give attention to the details at the present time.
Vfb
A
First, the formula of threshold voltage can be derived as
Vth =Vfb +φs +γ φs −Vbs (20) In this work, we have extracted the parameter in the subthreshold region and the φs is the
surface potential assumed to be equal to 1.5φf in this situation. A series of subthreshold data in Fig. 4 were transformed via Eq. (9) into the body effect coefficient mismatch σγ and flat-band voltage mismatch
Vfb
σ . Of course, we can observe all the effects for size proportionality constant for threshold voltage under different back-gate biases.
In the previous work, we applied the inverse square root of area law and obtained the proportionality constants Aγ and Therefore, we can make some assumptions according to the results such as to produce a physical model. Using the results of extraction for different parameters can bring interesting insights into observe the mismatch model. We can achieve good reproduction of data on the basis of our model.
V . Afb
Second, we will discuss the random threshold voltage fluctuation as well as the fluctuation mechanisms for the N-MOSFETs. The extractions of the threshold voltage and DIBL in each microscopically different transistors are carried out in the subthreshold at low drain voltages. On the other hand, in order to clarify the phenomena about the relationship between parameters, the results will be compared with the model adopted from the Takeuchi’s paper [5].
According to the work we had done, we can find that threshold voltage is also described by formula (1). Assuming that the correlation coefficient for the flat-band voltage and body effect coefficient is negligibly ignored, strikingly the following physically based relation remains valid:
And we can simplify the above formula according to the proportionality constants ,
Vth
A Aγ and . The proportionality constant can be written as
fb th
2
th fb
AV AV
A2V =V2fbA2V +γ2∗(1.5φf −Vbs)A γ (22)
where the unit of is
Vth
A Viμmand the units of Aγ and are
Vfb
A μm. In this case, the effects of back-gate bias can also be observed. The results are shown in Fig. 12-1. We can find that as the reverse bias increases, the proportionality constant increases simultaneously. This result is reasonable according to formula (22) and we can achieve a new way to predict the influence of the bias.
Vth
A
When we employed almost all our time in research, something may be left behind in a hurry. To insure the reliability of our model, we can try another method to prove the relationship between parameters. As a result, an extraordinary fitting line between the measured and predicted variance is obtained for regions of operation and for a very wide range of transistor sizes, including minimum channel length transistors. In our point of review, this method is a new way to predict the proportionality constant , as shown in Fig. 12-2.
That is, we only need to use a single sample to determine the , although we still need to gain the values of
Vth
A
Vth
A
Aγ and . This is also a trivial process to attain the results. But we have reached that this process is possible with different back-gate biases applied. This is the satisfying result along with assumptions consistent with the previous work.
Vfb
A
3.3 Effect of DIBL on Threshold Voltage
DIBL was defined as the threshold-voltage shift divided by the drain voltage change. In our case, DIBL can be expressed as follows
1 1 0 where the form in our research is simplified to at the condition of drain voltage of 0.01V as usual. In Fig.13-1 and Fig. 13-3 the is extracted under V
work, we employ a maximum trans-conductance method in the linear region to assess quasi-equilibrium threshold voltage as shown in Fig. 8 and the constant subthreshold current
method in the saturation region to extract the DIBL as shown in Fig. 13-1 and Fig. 13-2.
Fig. 14 shows the histogram of the threshold voltage under different drain biases and DIBL.
In the work, we will discuss the matching model for the DIBL and threshold voltage further. Simultaneously, we can write the formula as follows
Vth1(Vds1)=DIBL∗
(
Vds0 −Vds1)
+Vth(vds0) (24) According to Eq. (1), we can derive the mismatch model as follows(25)
where . The results are shown in Fig. 15. We can see that the matching property of threshold voltage can be written as a function of DIBL and threshold voltage. In order to make most use of our data, we had better to retain the accuracy of our model.
Therefore, we can simplify Eq. (25), leading to as below simulate the value of size proportionality constants for the standard deviation of threshold voltage under V
AV
ds=1 V. Indeed, we can observe that the results are expected as inferred from Fig. 16 and Fig. 17.
3.4 Conclusion
In this chapter, we discuss main parameters about threshold voltage and DIBL. We have compared the results between the fluctuation model and the traditional model. It is obvious that the fluctuation model can offer a way to see the changes in under different biases and manufacturing processes. Traditional model is still used to complete our model in the subsequent work. On the other hand, we can consider the effect of DIBL on the threshold
AV
voltage. With channel length scaling down, it is gradually important to discuss short-channel effects such as roll-off of threshold voltage and drain-induced-barrier-lowering. Fig. 13-2 shows that DIBL increases dramatically as the channel length decreases. That is, we may not use the constant current method to determine value of DIBL and Vth1. The results may impose a problem as the gate length scales down to 50nm and beyond. Fig. 13-3 also shows the same obstacle as the channel length decreases. In such a condition, we can not extract the accurate
Vth1. This phenomena is a big challenge needed to overcome.
Chapter 4 Extraction of Series Resistance and Overlap Length
4.1 Constant Mobility Bias Conditions
With the devices scaling down to the deep sub-micrometer region, some phenomenon and factors can’t be neglected for the transport property of semiconductor physics. In this chapter, we will introduce some factors that were neglected in the past and now will be taken into account due to the short channel effect. So we need to extract parameters as source/drain series resistance and the gate-to-source/drain-extension overlap length. This chapter is based on the factors of series resistance and the gate-to-source/drain-extension overlap length.
These two factors really play dominant roles in our model are described below.
First, in order to build a new model, we should extract the value of source-and-drain series resistance. According to the result of the paper [16], a new model of extracting the MOSFET series resistance is cited. This method needs simple dc measurements on a single test device. Experimental demonstration is presented, and on the basis of the MOSFET equivalent circuit, the series resistance leads to excess potential drop, reducing the intrinsic voltage and degrading the drive capacity. As the gate length shrinks, the series resistance becomes a important factor of the total resistance. As the devices scale down, series resistance plays an important role in the circuits.
It is known that the use of previous methods is problematic, and this paper presents a mew method along with experimental demonstration and verification. We know that the relationship exists between the measured channel carrier mobility and the effective silicon vertical electrical field (Eeff) at the SiO2/Si interface [16]. The corresponding Eeff can be expressed as:
eff 1 d 1 i
Si
E Q
ε η
⎛ ⎞
= ⎜ +
⎝ Q ⎠⎟ (27) where εSi is the silicon permittivity, Qd is the depletion charge and Qi is the inversion layer
charge. η is an empirical factor with the values ~2 commonly used for electrons at room temperature. Based on the derivation procedure described elsewhere [17], Eq. (1) can be futher written as:
where Vfb is the flat-bandvoltage and φf is the potential difference between the Fermi level and the intrinsic Fermi level. Both Vfb and φf are essentially unchanged for a single device operated under different biases.
4.2 Extraction of Source/ Drain Series Resistance
By incorporating the constant mobility criterion into the current equation MOSFETs operated in the linear region, the results under different bias conditions are:
d(Vbs1) OX eff (Vbs1)
(
gs(Vbs1) th(Vbs1) 0.5 ds) (
ds ( bs1))
In this experiment, we assumed that the mobility is essentially the same under back-gate bias and considered mobility is the same under high Eeff condition.
In the above formula, the series resistance can be easily achieved. Fig. 18 shows satisfying results for the series resistance and a constant value about 220(Ω-μm) is determined for our model operated in above threshold region.
4.3 Results and Discussions of Extraction of Source/Drain Series Resistance
In order to obtain constant carrier mobility under different bias conditions, a sufficiently high Vgs is necessary to force the mobility to converge toward the universal curve. Then the extracted Rsd values approach constant and no dependency on the Vbs bias can be observed in the high Vgs region as depicted in Fig. 18.
Although the results of different sizes for extraction in the previous work will vary, we still view the results of the series resistant to be constant. This assumption is reasonable for the following model and the variation of series resistance only plays a minor role in the above threshold region. We can prove this by the results of mismatch model in the above threshold.
4.4 Extraction of Gate-to-Source/Drain-Extension Overlap Length
The edge direct tunneling (EDT) [10] of electron from n+ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs has ultrathin gate oxide thickness. It is found that for thinner oxide thickness, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT), and gate-to-substrate tunneling. As a result, the induced gate and drain leakage and drain leakage is better measured per unit gate width. According to [10], an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.
In this work, we explored a dominant off-state leakage component via edge direct tunneling of electron from n+ polysilicon to underlying n-type drain extension for ultrathin gate oxide thickness. With the effective edge-tunneling area (= ), the EDT I-V model reads
A LTN ×W
IEDT =AQfT =L WQfTN T (32) where is the sheet charge of the accumulation layer; is the electron impact frequency on the n
Q f
+ -poly/SiO2 interface; T is the modified transmission probability considering interface reflection factor. Finally, the extracted gate-to-source/drain overlapLTN is
EDT EDT
TN
J I
= L W (33) In order to gain the value of the the gate-to-source/drain-extension overlap length, we had run a simulator to extract the value of the edge direct tunneling current density. In the pursuit of overlap length, we measured the edge direct tunneling current. Straightforward, the value of gate-to-source/drain-extension overlap length can be obtained. The tunneling path extracted was 6nm [18] ( ) wide from the gate edge as can be corroborated in Fig. 19. This is confirmed from the process simulation.
LTN
4.5 Results
In order to confirm the validity of our model, we will take some parameters into consideration and think whether the results of our experiments are accurate or not. When we consider the effective channel length for the mismatch model, we will view the improved results, indicating a better condition than the past model that directly used the mask-level channel length. We will compare the results with those of other papers [18] to verify that the validity of hypotheses. Although the overlap length will be different for different sizes, we assume that an approximate value for LTN is reasonable.
Chapter 5 Mismatch in above Threshold Region
5.1 Backscattering Theory
In the backscattering theory, we use the wave concept to describe the carrier transport in the channel. As stated in backscattering theory [19]-[20], the nanoscale device performance is limited by the injection velocity and the backscattering coefficients. In this study, if the channel is under low electric field conditions, the width of the kBT layer calculated according to its definition is wide enough to be larger than the channel length L. The backscattering coefficient can be presented from
C( eff) L r low E
L λ
= + (34) where λ is the mean-free-path and L is the channel length. When the channel is under high electric field, <L, the backscattering coefficient can be estimated from
r high EC( eff)
= λ
+ (35) In our model, the channel is assumed to be operated under high electric field. In other words, we will discuss the devices operated in the saturation region. From Fig.20, we can derive the drain current easily and the drain current can be written
Ids =W J[ +(0)−J−(0)]=qW F[ +(1−R)−F−(1−R e) −qV kT/ ] (36) where R is the backscattering coefficient and T(=1-R) is the transmission coefficient. In the saturation region, the value of drain voltage will be higher than thermal voltage. So Eq. (36) can be modified as below
Ids =W J[ +(0)−J−(0)]=qWF+(1−rc) (37)
Combining (37) and (38), we can derive the formula as follows whereυinjare the thermal injection velocity at the top of source-channel junction barrier. In (39), the drain current is related to the backscattering coefficient[21]. In the mismatch model, we also can obtain the formula like Eq. (1) and Eq. (6). The mismatch model in above threshold region will be discussed later and we should characterize some parameters.
5.2 Analysis and Model
Based on backscattering theory, (39) is constructed except low drain voltage. Since the region is operated under high drain voltage. On the other hand, the main region for analog circuits is controlled in the saturation region. These two conditions will confine the region of our research. That is to say there will be some limitations when we extract the data.
In our research, there are several factors used to modify our model such as DIBL and Rsd.
Fig. 21 shows the flowchart for the procedure of extracting rc. Now we propose a new simple statistical model to quantitatively account for the above observed dependencies of the mismatch in the above threshold region on the gate-to-source bias. Eq. (40) the mismatch of the current,
Ids
σ , can be derived as a function of the coefficients of variance of the parameters :
the coefficient of the variance in the threshold voltage,
Vth
σ , the coefficient of the variance in the drain-induced-barrier-lowering σDIBL, and the coefficient of the variance in the channel backscattering coefficient
rc
σ :
( )
In the above formula, we neglect the effect of source-and-drain series resistance. However, we will show the mismatch differences between models withand without Rsd.This new formulation describes the dependence of
Ids
σ with varying gate voltage in the above threshold voltage is very small. Fig. 24 shows that we use the backscattering mismatch model to reproduce the coefficient of the variance of drain current versus gate voltage over 0.4~0.5V at
σ with varying gate voltage in the above threshold voltage is very small. Fig. 24 shows that we use the backscattering mismatch model to reproduce the coefficient of the variance of drain current versus gate voltage over 0.4~0.5V at