Chapter 2 Random Dopant Fluctuation
2.5 Summary
We have provided an assessment of random dopant fluctuations in multi-gate MOSFETs using atomistic simulations. Our full Monte Carlo approach can capture both number and position fluctuations. This is a more efficient and recommended method. Besides, threshold voltage lowering with respect to the continuous simulation is observed in our work. We believe it is due to current percolation in the inhomogeneous potential profile. Furthermore, Source/Drain asymmetry is another characteristic of atomistic simulation especially in lightly doped devices. This has rarely been discussed and may limit the application of switching circuit designs.
In lightly doped devices, position variation is the dominant mechanism and devices with larger AR will lead to less fluctuation due to better electrostatic integrity.
In heavily doped devices, number and position components are comparable and the implementation of full Monte Carlo simulation is required. With higher AR, RDF becomes worse due to smaller channel volume and fewer dopants. Our study indicates that lightly doped FinFET, with its superior electrostatic integrity, is the best candidate for future multi-gate device design under the consideration of random dopant fluctuation.
Fig. 2.1 Poisson distribution of the dopant number inside the active region.
The figure includes 10000 ensembles with 94 mean dopants.
60 70 80 90 100 110 120 130 0
500 1000 1500 2000
O c c u re n c e
Atom number
0 50 100 150 200 250 300 350 400
Fig. 2.2 Top view of 3D random dopant arrangements with 120 dopants inside the region. Closed circles represent dopant atoms. Demonstrated device dimensions are Lg = 100 nm, TSOI = 10nm and Wg = 40nm with doping =
3 10× 18cm-3.
0 50 100 150 200 250 300 350 400 inside the region. Closed circles represent dopant atoms. Demonstrated device dimensions are Lg = 100 nm, TSOI = 10nm and Wg = 40nm with doping = 1 10× 17cm-3.
Fig. 2.4 Perspective view and geometry definitions of the multi-gate MOSFET used in this work.
Aspect Ratio (AR) = H /W fin fin
total fin fin
W ==== 2 H×××× ++++ W
0
10
20 5
15
25
0 5 10 15 0 10 20 30
5 15 25
Channel length [nm]
Fin width [nm]
F in h e ig h t [n m ]
Fig. 2.5 Example of atomistic dopant placement in the channel region of a multi-gate MOSFET with Lg=25nm, Wfin=15nm, Hfin=30nm. Closed circle symbols represent dopant atoms.
Fig. 2.6 Our quasi-uniform meshes used for 3-D RDF device simulations in (a)
(b)
(c) (d) (e)
channel S/D
S/D
channel
channel
channel S/D
S/D S/D
S/D
Dopant number
Poisson distribution
#
dopant number1#
dopant number2#
dopant number3…
Fig. 2.7 Simulation approach for dopant number fluctuation.
Fig. 2.8 Simulation approach for dopant position fluctuation.
Fig. 2.9 Potential distribution at Si/SiO2 interface with discrete dopants inside the channel. Potential distribution is distorted due to discrete dopants and this is the cause of threshold voltage variation.
Table 2.1. Comparison of the atomistic results in this work and in [18]
-0.4 -0.2 0 0.2 0.4 10
-510
-310
-710
-910
-11Gate Voltage [V]
D ra in C u rr e n t [A ]
Wtotal=75nm, Leff=25nm, Vds = 0.05V Triangle : conventional continum doping Line : atomistic doping
Square : atomistic doping (average)
Ioff
Fig. 2.10 Id-Vg curves for conventional simulation (Triangle), 150 atomistic simulations (solid lines) and the average of these atomistic simulations
(square).
Table2.2. Detailed data of Vth shift and Vth variations for devices with Lg = 25 nm and Wtotal = 75nm. Vth lowering is defined as Vth (atomistic) - Vth (continuous).
0
Fig. 2.11 Histogram plots of S/D swapping with 150 microscopically different (a) heavily doped and (b) lightly doped Tri-gate devices. Here forward means before S/D swapping operation and reverse means after S/D
-10 -5 0 5 10 15 20 25 30
Fig. 2.12 Histogram plots of Vth difference between S/D swapping for (a) heavily doped and (b) lightly doped Tri-gate MOSFETs
(b) (a)
Fig. 2.13 The correlation coefficients between the normalized threshold voltages and the dopant number are (a) 0.64 for heavily doped and (b) 0.21 for lightly doped Tri-gate devices.
60 70 80 90 100 110 120
1E17 1E18 1E19
for heavily and lightly doped channels.0.5 1.0 1.5 2.0
Fig. 2.16 The AR dependence of threshold voltage fluctuations for (a) heavily doped and (b) lightly doped devices.
1E16 1E17 1E18 1E19
Fig. 2.17 Doping dependence of threshold voltage variation for 3 AR devices. Threshold voltage variations are determined by the electrostatic integrity and doping concentration.
2.0x1012 4.0x1012 6.0x1012 8.0x1012
Fig. 2.18 Threshold voltage variation as a function of the (a) doping concentration NA b
behind the epi-layer and (b) delta-doping dose Qδ for a set of 50×50nm MOSFET’s with t = 3nm,NA
b = 1×1018 cm-3, NA
e = 1×1015 cm-3, at different epi-layer thickness [28]. Inset plot shows the definition of epi-layer. (c) shows
(a)
(b)
(c)
2x1018 3x1018 4x1018 5x1018 0.00
(a)
(b)
Fig. 2.19 (a) 1D representation of long-range and short-range parts of the dopant number density and (b) 3D perspective view of long-range part number density. Long-range potential does not diverge at the origin.
Chapter 3
Line Edge Roughness and
Equivalent Oxide Thickness Variation
3.1 Line Edge Roughness
3.1.1 Introduction
Due to the resolution limit of lithography, etching process or the grain characteristic of photo resist and poly gate, it’s inevitable to generate line edge roughness (LER) during device processing. This effect was negligible in the past.
However, it is becoming increasingly important for scaled devices. According to the ITRS predictions in 2007 [2], the tolerance of LER for 65nm and 32nm node is 2.6nm (3σ) and 1.3nm, respectively. Unfortunately, the best technology in the world can only provide about 5nm LER in 2003 [10]. LER will soon become comparable to device critical dimension and may worsen device short channel effects. Actually, under the prediction of recent studies [30], LER is expected to become the dominant contributor to device variation for future planar MOSFETs.
In the past, several approaches were adopted to estimate the effects of LER.
For example, P. Oldiges et al. [32] employed simplified 2D slice simulations to capture the behaviors of real ragged 3D devices. C. H. Diaz et al. [33] derived an
the model with experimental data. A. Asenov et al. [10], for the first time, provided a systematic 3D discussion of LER and investigated the relative contribution of RDF and LER to the overall intrinsic parameter fluctuations for planar MOSFETs.
However, a detailed and comprehensive exploration of LER for multi-gate transistors is still needed. Although E. Baravalli et. al. [34] [15] gave a sophisticated simulation on FinFET and concluded that fin- and gate- LER would become significant as compared to RDF below 45-nm gate length geometries, it is still unclear how LER will influence these highly geometry-dependent devices with different AR design or doping concentration. This is one of the main purposes in this work.
In the following sections, we will first introduce the methodology for the LER simulation. For a given gate length and total width, we examine the impacts of simulation parameters on the threshold voltage for heavily and lightly doped devices.
Finally, we provide a comparison of LER with RDF for different doping and device structures.
3.1.2 Methodologies
3.1.2.1 Concept
The causes of LER, such as lithography, etching and diffusion, are similar to low-pass filters during transferring the rough line pattern to devices. Due to the isotropic properties, they could smooth the original rough pattern of photo resist or mask, as revealed from the magnitude of real line edge pattern in frequency domain shown in Fig. 3.1. Based on this characteristic, we can model the behavior of the
magnitude spectrum associated with appropriate phases to reconstruct the LER patterns. This is the concept of Fourier synthesis approach [9-10].
3.1.2.2 Simulation Approach
The most popular model to simulate the magnitude spectrum of LER is the Gaussian and exponential autocorrelation functions with two parameters：
S
G( )k
=π
∆ Λ2e
−(k2Λ2/ 4) (3.1), where ∆ is the rms amplitude of the roughness, and Λ is the correlation length which is a fitting parameter for a particular type of LER. k is the index of discrete sampling points defined as k=i(2 / Ndx)π with dx the spacing of sampling points.
Fig. 3.2 shows a real LER power spectrum compared with the Gaussian and exponential models with the specified values of ∆ and Λ [10]. With appropriate choices of rms amplitude and correlation length combined with randomly selected phases that can make sure each rough line is unique, we can rebuild rough lines as shown in Fig. 3.3. It can be seen that the Gaussian model is smoother than the exponential one due to lack of high frequency component. Besides, unlike planar MOSFETs, multi-gate LER comes from both gate length and fin width dimension deviations. It has been confirmed that σtotal_LER2 =σfin_LER2 +σgate_LER2 [34]. Fig.
As for the determination of model parameters, the value of rms amplitude can be obtained from the ITRS. Unlike rms amplitude, the choice of correlation length should be extracted from the real line edge patterns. P. Oldiges et al. [32] reported that the values of correlation length vary between 10 and 50nm from their measurements.
Based on the SEM analysis, A. Asenov et al. [10] indicated that the values of correlation length are in the range of 20-30nm. Due to lack of the experimental data, we determine the value of correlation length from the literatures mentioned above in the following simulations.
As in chapter 2, we perform Monte Carlo simulation with 150 samples to capture the stochastic behavior regarding LER. Besides, we use the same physical TCAD simulation models and current extraction criterion as in chapter 2. To relieve the simulation burden, we use continuous doping in the following simulations.
3.1.3 Results and Discussions
Before investigating the impacts of model parameters on device characteristics, we first qualitatively evaluate their influences on the LER patterns and try to gain more insights about the model. In Fig. 3.5, we set correlation length to 20nm with various rms amplitude values. It can be seen that increasing rms amplitude gives rise to larger amplitude spectrum. Moreover, from Fig. 3.5 (a) (b), we find the difference in amplitude spectrum is about four times when the rms amplitude becomes two times larger. This can be explained by (3.1). Besides, increasing the rms amplitude would
lead to rougher line as shown in Fig. 3.5 (c). In Fig. 3.6 (a), we vary the correlation length with constant rms amplitude. We can find that the magnitude spectrum with smaller correlation length would spread out to higher frequency region, which results in the rougher LER (more high frequency components) as observed in Fig. 3.6 (b).
Moreover, in Fig. 3.6 (b), we find that increasing correlation length would also lead to worse LER (σLER =1.23, 1.87 nmfor correlation lengths equal to 20 and 50nm).
Fig. 3.7 shows the rms amplitude dependence of σVthfor lightly doped devices with 3 kinds of AR. It can be seen that increasing the rms amplitude, or rougher line edge, may result in severer threshold voltage variation for both gate and fin components. Besides, for devices with AR=0.5 or 1, gate LER is the dominant mechanism due to poor electrostatic integrity. With the increasing of AR, we can find that the influences of gate- and fin- LER become comparable in our FinFET (AR=2) devices. For devices designed with AR=5 as described in [34], fin LER would dominate the overall LER variation. In Fig. 3.8, we design the total width of FinFET (AR=2) devices to three times of Lg at different technology nodes and compare the importance of gate and fin LER. It can be seen that the fin LER is the main contributor to device LER variations because of the significant shrinkage of fin width at smaller devices. From above discussions, we conclude that gate and fin LER will become dominant for devices with critical dimension in channel length and fin width, respectively.
In Fig. 3.9, we investigate the impacts of correlation length on device variation.
Similar to the results in Fig. 3.7, increasing correlation length leads to higher Vth
fluctuation. In addition, we find that Vth fluctuations would saturate as correlation
variations induced by the fin LER will saturate as correlation lengths reach the gate length, 25nm, and gate LER shows different saturation levels because of the different fin widths for three various AR devices. This property is also observed in planar transistors [10]. To explain the phenomenon, we demonstrate three LER patterns associated with different correlation lengths as shown in Fig. 3.10. If we assume that the device critical dimension is equal to 50nm, and assign the corresponding LER pattern for each device as shown in the figure, it can be seen that as the correlation length decreases, the discrepancy of LER pattern for each device increases. This explains the initial increase for small correlation lengths. When the correlation length approaches the device critical dimension, there is less LER pattern dispersion and therefore the Vth variation saturates.
For heavily doped transistors, all of above characteristics are similar to lightly doped ones. In Fig. 3.11, we compare total LER (σfin_LER2 +σgate_LER2 ) for devices with different doping concentration and AR. It can be seen that heavily doped devices show better immunity to LER because of the superior gate control especially for the devices with small AR. Moreover, increasing doping concentration can significantly suppress LER at the price of worse RDF as mentioned in chapter 2. Fig. 3.12 illustrates the comparison of RDF and LER. It can be seen that RDF dominates in heavily doped devices. For lightly doped devices, LER is the most important contributor to device variations. Under the consideration of RDF and LER, lightly doped FinFET (AR=2) has better immunity to device intrinsic parameter fluctuations.
So far, we have discussed several properties of LER and its influences on multi-gate devices. We tackle the problem with individual assessment of RDF and
LER, that is, we assume that they are independent events. Actually, this is confirmed in planar MOSFETs [10]. However, there are several studies against this argument. It is believed that there exist coupling between RDF and LER. S. Xiong et. al. [35]
performed process simulation and found LER enhanced lateral diffusion. M. Hane et.
al. [36] considered both RDF and LER simultaneously and confirmed the existence of
coupling. To assess this problem, we make a simple examination of dopant number in the channel with different degree of LER. The determination of dopant number is similar to the full Monte Carlo simulation in section 2.2.2. Fig. 3.13 show the dopant number histogram plots with no LER, LER with rms amplitude=1.5nm and 2.5nm, respectively. It can be seen that different rough patterns have the same average but different spreading in dopant number. Rougher line edge pattern seems to be more diverse. This is because worse LER causes larger discrepancy in the channel volume which is closely related to the total dopant number. In other words, we may observe the coupling between RDF and LER in aspect of dopant number. We will further investigate the coupling between RDF and LER in the future.
3.2 Equivalent Oxide Thickness Variation
3.2.1 Introduction
To sustain gate control, reducing equivalent oxide thickness (EOT) is an effective way in scaled MOSFETs. When gate oxide is scaled to several atom layers, not only random dopant fluctuation and line edge roughness, surface roughness at the SiO2/Si and SiO2/gate interfaces will lead to significant local oxide thickness variation
and become another source of device variation. A. Asenov et. al. [11] implied that for conventional MOSFETs with dimensions below 30nm, threshold voltage fluctuations induced by oxide thickness variation are comparable to random dopant fluctuation.
Later on, A. T. Putra et. al. [37] performed 3D simulations on atomic oxide roughness and local gate depletion and then concluded that oxide thickness variation is not the main origin of Vth variation in FDSOI MOSFETs.
Under the concern of gate leakage, using higher dielectric constant (high-k) materials in placement of conventional SiO2 insulator provides us an alternative for device design [2]. Due to higher dielectric constant, we can retain the same gate coupling with thicker physical thickness and less local oxide thickness variation.
However, the introduction of high-k gate stack may also bring several technological issues [38]. Some of these effects will introduce intrinsic parameter fluctuations such as the non-uniformity of dielectric constant over the gate stack [39].
In the following section, we will introduce our methodology in the investigation of the impacts of oxide thickness variation and high-k non-uniformity on multi-gate transistors. Finally, we will compare this mechanism with RDF and LER.
3.2.2 Methodologies
Oxide Thickness Variation (OTV)
OTV is simulated with the Fourier synthesis approach as described in LER section except for the modification of 1D line pattern to 2D roughness interface
matrix [11]. The Gaussian function is applied to model the magnitude spectrum of rough surface and combined with randomly selected phases to reconstruct the rough interface. To simulate the atomic level imperfections, we assign the rms amplitude to 0.3nm, which is close to the magnitude of atom layers. As for the determination of correlation length, S. M. Goodnick et. al. [9] reported that the value of correlation length is between 1-3 nm from their TEM measurements. At the same time, the values of correlation length are also extracted from the AFM measurements and reported to range from 10 to 30 nm [11]. Due to the discrepancy in correlation length, we will investigate the impacts of correlation length on device variability.
After constructing the interface, digitalizing the original analog interface is essential to reduce the simulation burden. In [19], C. Riddet et. al. digitalize the rough surface to two 0.15 nm steps above and below the position of original smooth surface.
To avoid the unwanted distortions, we provide higher resolution with more steps. Fig.
3.14 is the rough interface generated by the Fourier synthesis and the step approximation. It can be seen that the step-approximated surface pattern is very similar to the original one. Fig. 3.15 is the demonstration of OTV for multi-gate MOSFET from TCAD device simulation.
Dielectric Constant Fluctuation (DCF)
So far, device variation induced by the high-k material is less studied. A. R.
Brown et al. [40] first proposed a novel method to assess this problem. In the following section, we will study the impacts of high-k variation on lightly doped multi-gate transistors with identical simulation approach as described in [40].
To capture the spatial variation of dielectric constant, we construct a 2D rough interface pattern as in OTV. Then we specify an extra parameter,α , which is chosen to be a fraction of rms amplitude. This parameter determines the gate stack to SiO2
(k=3.9) while −α <H x( )<α and HfO2 (k=25) while |H x( ) |≥α. Fig. 3.16 illustrates the 1D representation in determining non-uniform high-k pattern. In Fig. 3.17, we compare the original TEM image of HfSiO film with the dielectric pattern produced by this method. With appropriate parameters, we may duplicate the real pattern fairly well. Fig. 3.18 shows several dielectric patterns with different parameters. It can be seen that the correlation length alters the scale of dielectric pattern. Besides, α decides the portion of SiO2 material in high-k gate stack. Decreasing the value ofα will reduce the portion of SiO2, that is, less DCF.
3.2.3 Results and Discussions
Fig. 3.19 shows the impacts of channel doping, AR and correlation length on OTV. From a simple long channel Vth model：
ε
∝ B
th ox ox
V t Q
(3.3)It can be seen that the threshold voltage dispersion induced by OTV is related to the bulk charge term, QB. It means that devices with higher channel doping and larger channel volume have poorer immunity to OTV as shown in the figure.
Therefore, we can observe significant degradation of Vth variation in heavily doped
transistors as correlation length changes from 10nm to 15nm. Fig. 3.20 gives another support of this argument by changing the channel doping concentration.
Fig. 3.21 is the potential profile of a planar MOSFET showing the influence of DCF. The distortions in surface potential due to the spatial variation in the gate stack pattern can be seen. Different gate stack patterns lead to different potential distortions, as a consequence of Vth variation. In Fig. 3.22, we find the same AR and correlation length dependence of Vth variation as in OTV. Devices with larger channel volume (smaller AR) and correlation length show higher sensitivity to DCF. Besides, due to higher pattern discrepancy, the degradation in Vth variation at largerαcan also be seen in the figure.
Fig. 3.23 summaries several fluctuation sources discussed above, RDF, LER and EOT variation. It can be seen that EOT variation is less important as compared to RDF and LER in lightly doped devices and becomes comparable to LER in heavily doped case. Except for the increment of overall fluctuation, RDF and LER are still the main variations in heavily and lightly doped devices, respectively.
Fig. 3.23 summaries several fluctuation sources discussed above, RDF, LER and EOT variation. It can be seen that EOT variation is less important as compared to RDF and LER in lightly doped devices and becomes comparable to LER in heavily doped case. Except for the increment of overall fluctuation, RDF and LER are still the main variations in heavily and lightly doped devices, respectively.