Chapter 3 Line Edge Roughness and Equivalent Oxide Thickness
3.2 Equivalent Oxide Thickness Variation
3.2.1 Introduction
To sustain gate control, reducing equivalent oxide thickness (EOT) is an effective way in scaled MOSFETs. When gate oxide is scaled to several atom layers, not only random dopant fluctuation and line edge roughness, surface roughness at the SiO2/Si and SiO2/gate interfaces will lead to significant local oxide thickness variation
and become another source of device variation. A. Asenov et. al. [11] implied that for conventional MOSFETs with dimensions below 30nm, threshold voltage fluctuations induced by oxide thickness variation are comparable to random dopant fluctuation.
Later on, A. T. Putra et. al. [37] performed 3D simulations on atomic oxide roughness and local gate depletion and then concluded that oxide thickness variation is not the main origin of Vth variation in FDSOI MOSFETs.
Under the concern of gate leakage, using higher dielectric constant (high-k) materials in placement of conventional SiO2 insulator provides us an alternative for device design [2]. Due to higher dielectric constant, we can retain the same gate coupling with thicker physical thickness and less local oxide thickness variation.
However, the introduction of high-k gate stack may also bring several technological issues [38]. Some of these effects will introduce intrinsic parameter fluctuations such as the non-uniformity of dielectric constant over the gate stack [39].
In the following section, we will introduce our methodology in the investigation of the impacts of oxide thickness variation and high-k non-uniformity on multi-gate transistors. Finally, we will compare this mechanism with RDF and LER.
3.2.2 Methodologies
Oxide Thickness Variation (OTV)
OTV is simulated with the Fourier synthesis approach as described in LER section except for the modification of 1D line pattern to 2D roughness interface
matrix [11]. The Gaussian function is applied to model the magnitude spectrum of rough surface and combined with randomly selected phases to reconstruct the rough interface. To simulate the atomic level imperfections, we assign the rms amplitude to 0.3nm, which is close to the magnitude of atom layers. As for the determination of correlation length, S. M. Goodnick et. al. [9] reported that the value of correlation length is between 1-3 nm from their TEM measurements. At the same time, the values of correlation length are also extracted from the AFM measurements and reported to range from 10 to 30 nm [11]. Due to the discrepancy in correlation length, we will investigate the impacts of correlation length on device variability.
After constructing the interface, digitalizing the original analog interface is essential to reduce the simulation burden. In [19], C. Riddet et. al. digitalize the rough surface to two 0.15 nm steps above and below the position of original smooth surface.
To avoid the unwanted distortions, we provide higher resolution with more steps. Fig.
3.14 is the rough interface generated by the Fourier synthesis and the step approximation. It can be seen that the step-approximated surface pattern is very similar to the original one. Fig. 3.15 is the demonstration of OTV for multi-gate MOSFET from TCAD device simulation.
Dielectric Constant Fluctuation (DCF)
So far, device variation induced by the high-k material is less studied. A. R.
Brown et al. [40] first proposed a novel method to assess this problem. In the following section, we will study the impacts of high-k variation on lightly doped multi-gate transistors with identical simulation approach as described in [40].
To capture the spatial variation of dielectric constant, we construct a 2D rough interface pattern as in OTV. Then we specify an extra parameter,α , which is chosen to be a fraction of rms amplitude. This parameter determines the gate stack to SiO2
(k=3.9) while −α <H x( )<α and HfO2 (k=25) while |H x( ) |≥α. Fig. 3.16 illustrates the 1D representation in determining non-uniform high-k pattern. In Fig. 3.17, we compare the original TEM image of HfSiO film with the dielectric pattern produced by this method. With appropriate parameters, we may duplicate the real pattern fairly well. Fig. 3.18 shows several dielectric patterns with different parameters. It can be seen that the correlation length alters the scale of dielectric pattern. Besides, α decides the portion of SiO2 material in high-k gate stack. Decreasing the value ofα will reduce the portion of SiO2, that is, less DCF.
3.2.3 Results and Discussions
Fig. 3.19 shows the impacts of channel doping, AR and correlation length on OTV. From a simple long channel Vth model：
ε
∝ B
th ox ox
V t Q
(3.3)It can be seen that the threshold voltage dispersion induced by OTV is related to the bulk charge term, QB. It means that devices with higher channel doping and larger channel volume have poorer immunity to OTV as shown in the figure.
Therefore, we can observe significant degradation of Vth variation in heavily doped
transistors as correlation length changes from 10nm to 15nm. Fig. 3.20 gives another support of this argument by changing the channel doping concentration.
Fig. 3.21 is the potential profile of a planar MOSFET showing the influence of DCF. The distortions in surface potential due to the spatial variation in the gate stack pattern can be seen. Different gate stack patterns lead to different potential distortions, as a consequence of Vth variation. In Fig. 3.22, we find the same AR and correlation length dependence of Vth variation as in OTV. Devices with larger channel volume (smaller AR) and correlation length show higher sensitivity to DCF. Besides, due to higher pattern discrepancy, the degradation in Vth variation at largerαcan also be seen in the figure.
Fig. 3.23 summaries several fluctuation sources discussed above, RDF, LER and EOT variation. It can be seen that EOT variation is less important as compared to RDF and LER in lightly doped devices and becomes comparable to LER in heavily doped case. Except for the increment of overall fluctuation, RDF and LER are still the main variations in heavily and lightly doped devices, respectively.
3.3 Summary
In this chapter, we use Fourier synthesis with Gaussian model to investigate the impacts of LER and EOT variation on device variability. This approach is highly dependent on choice of the model parameters, rms amplitude and correlation length.
Because of this, reasonable specification of model parameter is essential to reflect the actual conditions. In this work, we reference the required parameters from the
literatures to make our work more practical.
In our simulations, we find that gate and fin LER will become dominant for devices with critical dimension in channel length and fin width, respectively. To obtain the comparable gate and fin LER variations, appropriate design of device AR may be an efficient approach and helpful in reducing the impact of LER. Besides, due to the improved gate control, heavily doped devices will suffer less LER variation at the price of worse RDF.
In the second part, we investigate the impact of EOT variation and find that EOT variation is closely related to the device bulk charge. For devices with higher channel doping or larger channel volume, EOT variation will become important.
Besides, it can be seen that EOT variation is negligible in lightly doped devices but comparable to LER in heavily doped case. Except for the increment of overall fluctuation, RDF and LER are still the main variations in heavily and lightly doped devices, respectively.
Fig. 3.1 Magnitude spectrum of a real LER pattern. It resembles low-pass filter. The figure is revised from [9].
2 2
2 ( / 4)
2
2 2
( ) ( ) 2
1
π − Λ
= ∆ Λ
= ∆ Λ + Λ
k G
E
S k e
S k
k
Fig. 3.2 Magnitude spectrum of LER from real line pattern accompanied with the Gaussian and exponential models [10].
Wave number
Fig 3.3 Example of randomly generated LER using 1D Fourier synthesis with rms amplitude = 2nm and correlation length = 12nm.
Fig. 3.4 Simulation flow to generate the fin- and gate- LER.
0 absolute magnitude and (b) normalized magnitude and (c)
(a)
(c) (b)
0
Fig 3.6. Correlation length dependence of the Gaussian model in (a) absolute magnitude and (b) LER pattern.
(a)
(b)
1.0 1.5 2.0
Wtotal = 75nm, Lgate = 25nm
|Vds| = 0.05V
Wtotal = 75nm, Lgate = 25nm
|Vds| = 0.05V
Fig 3.7. Rms amplitude dependence of threshold voltage variation for the (a) fin LER and (b) gate LER.
Fig 3.8. Comparison of gate and fin LER of FinFET (AR=2) devices (b)
10 20 30
Wtotal = 75nm, Lgate = 25nm
|Vds| = 0.05V
Wtotal = 75nm, Lgate = 25nm
|Vds| = 0.05V
Fig 3.9. Correlation length dependence of threshold voltage variation for the (a) fin LER and (b) gate LER. Fin widths are 37.5nm, 25nm and 15nm for AR=0.5, 1, 2 devices, respectively.
(a)
(b)
0 50 100 150 200 250
Fig 3.10. Explanation of Vth fluctuation saturation.
1E 1 7 1E 1 8 1E 1 9 channel doping. Heavily doped devices show better immunity to LER.
0.5 1.0 1.5 2.0
50 60 70 80 90 100 110 120 130
Fig 3.13. Dopant number inside the channel with (a) no LER (b) LER with rms=1.5nm and (c) LER with rms=2.5nm.
(a)
(b)
(c)
(a)
(b)
Fig. 3.14 Oxide thickness variation generated by the Fourier synthesis for (a) original rough surface and (b) the digitized surface.
Fig. 3.15 Demonstration of OTV for multi-gate MOSFETs.
k1 k1 α
αα α αα αα
k1 k2 k1 k2 k1 k2 k1 k2 k1
x H(x)
Fig. 3.16 1D representation of determining high-k non-uniformity with two extreme dielectric constant values.
0 5 10 15 20 25 30 0
5 10 15 20 25 30
(a)
(b)
Fig. 3.17 Demonstration of (a) the TEM image of HfOSi film [40] and (b) the simulated pattern. Black colored is SiO2 and white ones are HfO2.
5 10 15 20 25
Fig. 3.18 Dielectric patterns produced with different parameters: (a) Λ=2.5nm, α=0.25 (b) Λ=2.5nm, α=0.75 (c) Λ=10nm, α=0.25 (d) Λ=10nm, α=0.75. Black colored is SiO2 and white ones are HfO2.
0.5 1.0 1.5 2.0
Fig. 3.19 The impacts of channel doping, AR and correlation length on OTV.
Fig. 3.20 Vth variation induced by OTV at different channel doping.
Fig. 3.21 Potential distribution of a planar MOSFET. Surface potential is distorted by the DCF.
0.25 0.50 0.75
0 2 4 6 8
AR=2 AR=1
Sigma Vth [mV]
α
AR=0.5 solid: corre. length=10nm
dash:corre. length=15nm doping=1E17cm-3, thigh-k =2nm Lgate=25nm.Wtoal=75nm
|Vds|=0.05V
Fig. 3.22 The AR and correlation length dependence of DCF.
0.5 1.0 1.5 2.0
Fig. 3.23 Comparison of RDF, LER and EOT at (a) 6E18 cm-3 and (b) 1E17 cm-3 channel doping. LER and EOT are with correlation length=10nm.
Chapter 4
Variability in Multi-Gate MOSFETs
4.1 Introduction
So far, we have investigated individual variation in multi-gate transistors. Will the variability of the multi-gate device better than the bulk MOSFET？ Systematic assessments of individual source of intrinsic parameter fluctuation for conventional bulk MOSFETs and UTB SOI transistors have been described in [30] and [41], respectively. For multi-gate variability, F.-L. Yang et. al. [14] provided a comparison of planar MOSFET and omega FinFET in RDF, and LER variation and found superior device fluctuation immunity in multi-gate devices. In this chapter, we will investigate the impact of intrinsic parameter fluctuations introduced by RDF, LER and EOT variation in multi-gate MOSFETs. In addition, we will quantify the dominate variation source for multi-gate transistors at different technology nodes.
4.2 Intrinsic Parameter Fluctuations in Multi-Gate MOSFETs
Due to the predominant variability immunity of lightly doped FinFET (AR=2) shown in previous chapters, we use FinFET as a representative of multi-gate devices.
Three of the most important fluctuation sources, RDF, LER and EOT variation, are considered in 25-, 18-, 13-, and 9-nm channel-length devices. To capture the overall
effect of RDF, we perform atomistic simulations for both channel and Source/Drain regions. Besides, the diffusion of donor dopants from Source/Drain into channel region under the constraint of ITRS extension junction lateral abruptness requirements is also included in this part. In the LER simulations, two scenarios have been adopted：pessimistic and optimistic predictions of rms amplitude. In the pessimistic one, the specifications of simulation model parameters are based on the worst case prediction, that is, LER does not scale with each node ahead. In the optimistic scenario, LER follows the ideal prescriptions of the ITRS. Shown in table 4.1 are the corresponding model parameters. Density gradient approximation is included in the following simulations.
Fig. 4.1 shows the comparison of individual fluctuation source of FinFET at different technology nodes. When the rms amplitude of LER is fixed for each node, it can be seen that the LER prevails RDF and EOT variation or more accurately, fin LER is the most important mechanism over the whole range. The degradation of fin LER becomes pronounced at 13-nm channel length and reaches about 80 mV at 9 nm due to the deteriorated electrostatic integrity. Fig. 4.2 is the corresponding Id-Vg characteristics of 150 9-nm FinFETs with fin LER. It can be seen that large portion of devices are nearly punch-through with Vth smaller than zero. To relieve the device variation induced by the fin LER, appropriate device design is needed. In Fig. 4.3, we investigate the impact of AR on LER for 9-nm FinFET and observe the opposite trends in gate and fin LER. We find that the devices with AR=1.5 have comparable gate and fin LER and show better immunity to the overall LER. It seems that designing the devices with comparable gate and fin LER is beneficial in the suppression of the pessimistic LER fluctuations.
In the optimistic scenario, the values of rms amplitude follow the ITRS predictions which are specified to 1.2, 1.0, 0.75 and 0.5 nm for 25-, 18-, 13- and 9-nm channel length devices, respectively. As shown in Fig. 4.4, the device variation of LER is well-controlled, reaching about 15 mV for Vth variation at the 9-nm channel length. Because of the variation in local effective channel length induced by the Source/Drain RDF, it is observed that the influence of RDF starts to dominate LER when the channel length equals to 9 nm. This implies that even for lightly doped multi-gate MOSFETs, the implementation of atomistic simulation which considers Source/Drain and channel RDF is needed to investigate the actual device variability at this regime.
4.3 Comparison of Planar and Multi-Gate MOSFETs
In this comparison, our planar MOSFETs follow the ITRS roadmap for 25-, 18-, 13-, 9-nm channel length transistors. To make a fair comparison, we design planar and multi-gate MOSFETs with the same total width and Ioff by adjusting the corresponding gate work functions. Table 4.2 summarizes the device parameters of planar and multi-gate MOSFETs.
Fig. 4.5 is the comparison of planar MOSFETs and FinFETs with corresponding variation sources as LER is under the pessimistic condition. The difference between planar and FinFET devices is small for 25-nm channel length
device, and FinFET starts to prevail planar counterpart as scaled below 18nm. The degradation of variability with decreasing channel length results from the LER for both planar and FinFET transistors. Quantitatively, FinFET is four times better than planar devices for the 13- and 9-nm channel lengths. Without the improvements in LER, threshold voltage dispersion would reach 280 and 80 mV for planar and FinFET devices, respectively. We may assume each source of intrinsic fluctuation is statistically independent and calculate the overall Vth dispersion by [30]：
2 2 2
σ
V
th=
σV
RDF+
σV
LER+
σV
EOT (4.1)Fig. 4.6 shows the overall threshold voltage variation for planar and FinFET transistors. It can be seen that the difference between planar and FinFET devices becomes pronounced with the scaling of channel length.
4.4 Summary
We have investigated the impacts of RDF, LER and EOT variation on FinFET transistors at different technology nodes. Two scenarios of LER are included. In the pessimistic LER scenario, LER will become the dominant fluctuation source due to the deteriorated electrostatic integrity. Designing the devices with comparable gate and fin LER components by varying AR is beneficial to reduce the overall threshold voltage fluctuation. When we follow the optimistic predictions of LER in ITRS, we find that the threshold voltage variation induced by LER is well-controlled. In this scenario, the Source/Drain RDF starts to prevail LER as channel length is below 10 nm. Our results indicate that the difference between planar and FinFET devices the
overall threshold voltage variation becomes pronounced with the scaling of channel lengths.
Table 4.1 Specifications of model parameters used in the work.
Fig. 4.1 Threshold voltage variation for 25-, 18-, 13- and 9-nm channel length MOSFETs due to RDF, LER and EOT variation. LER is kept at rms=1.5nm and correlation length=30nm.
rms amplitude
correlation length = 30nm
Fig. 4.2 Id-Vg characteristic of 150 9-nm FinFETs due to fin LER.
Fig. 4.3 AR dependence of gate and fin LER fluctuations for 9-nm FinFETs.
1.0 1.5 2.0
20 30 40 50 60 70 80 90 100
S ig m a V th [ m V ]
Aspect Ratio
Total LER fin LER gate LER
MuG with Lgate=9nm Wtotal=27nm,|Vds|=0.05V
10 15 20 25 0
5 10 15 20 25 30
S ig m a V th [ m V ]
Channel length [nm]
RDF(channel+S/D) LER
EOT
Wtotal=3×Lgate
|Vds|=0.05V
Fig. 4.4 Threshold voltage variation for 25-, 18-, 13- and 9-nm channel length MOSFETs due to RDF, LER and EOT.
LER follows the ITRS roadmap with correlation length = 30 nm.
Table 4.2 Design parameters of planar and multi-gate MOSFETs.
0
Fig. 4.5 Comparison of individual variation source for planar and FinFET devices. LER is kept at rms=1.5nm and correlation length=30nm.
Fig. 4.6 Comparison of overall Vth fluctuation for planar and FinFET transistors. LER is kept at rms=1.5nm and correlation length=30nm.
Chapter 5 Conclusions
In this thesis, we have provided a systematic investigation of three important intrinsic parameter fluctuations, namely RDF, LER and EOT variation, with sophisticated simulation approaches for multi-gate MOSFETs.
For the RDF part, we have performed atomistic simulation to capture the impact of each dopant inside the channel. Our full Monte Carlo approach can capture both number and position components. In addition, the threshold voltage lowering of atomistic simulation with respect to continuous simulation has been observed in this work. In lightly doped devices, our study indicates that the position component dominates. In heavily doped devices, the number and position fluctuations are comparable and the implementation of full Monte Carlo simulation is required. Under the consideration of RDF, lightly doped FinFET (AR=2) is the recommended device design.
LER can be classified into fin- and gate-LER for multi-gate devices. In our simulations, we find that the gate and fin LER will become dominant for devices with critical dimension in channel length and fin width, respectively. An appropriate device design with comparable gate and fin LER variations may be helpful in reducing the overall LER. Because of the improved electrostatic integrity, multi-gate device with heavily doped channel has better immunity to LER at the price of worse RDF.
Comparing both the RDF and LER effects, we find that lightly doped FinFET is still
the best choice.
EOT variation can be grouped into oxide thickness variation (OTV) and dielectric constant fluctuation (DCF). We find that EOT variation is closely related to the bulk charge in channel region and this fluctuation source is small compared to RDF and LER.
In the pessimistic LER scenario, LER will become the dominant fluctuation due to the deteriorated electrostatic integrity. In the optimistic scenario, we find that the threshold voltage variation induced by the LER is under control even at 9-nm channel length devices. However, for multi-gate devices with well-controlled LER and sub-10nm channel length, the RDF from the Source/Drain encroachment will become increasingly important.
Under the same total width and Ioff, we have compared the variability of planar and multi-gate MOSFETs. Without effective improvement of LER, fin LER would become the dominant variation source for both planar and multi-gate transistors. If we assume each variation is independent and compare the overall fluctuations, we find that FinFET is better than planar MOSFETs and the difference between planar and FinFET devices increases with the scaling of channel length.
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