Chapter 4 Variability in Multi-Gate MOSFETs
4.3 Comparison of Planar and Multi-Gate MOSFETs
In this comparison, our planar MOSFETs follow the ITRS roadmap for 25-, 18-, 13-, 9-nm channel length transistors. To make a fair comparison, we design planar and multi-gate MOSFETs with the same total width and Ioff by adjusting the corresponding gate work functions. Table 4.2 summarizes the device parameters of planar and multi-gate MOSFETs.
Fig. 4.5 is the comparison of planar MOSFETs and FinFETs with corresponding variation sources as LER is under the pessimistic condition. The difference between planar and FinFET devices is small for 25-nm channel length
device, and FinFET starts to prevail planar counterpart as scaled below 18nm. The degradation of variability with decreasing channel length results from the LER for both planar and FinFET transistors. Quantitatively, FinFET is four times better than planar devices for the 13- and 9-nm channel lengths. Without the improvements in LER, threshold voltage dispersion would reach 280 and 80 mV for planar and FinFET devices, respectively. We may assume each source of intrinsic fluctuation is statistically independent and calculate the overall Vth dispersion by [30]：
2 2 2
σ
V
th=
σV
RDF+
σV
LER+
σV
EOT (4.1)Fig. 4.6 shows the overall threshold voltage variation for planar and FinFET transistors. It can be seen that the difference between planar and FinFET devices becomes pronounced with the scaling of channel length.
4.4 Summary
We have investigated the impacts of RDF, LER and EOT variation on FinFET transistors at different technology nodes. Two scenarios of LER are included. In the pessimistic LER scenario, LER will become the dominant fluctuation source due to the deteriorated electrostatic integrity. Designing the devices with comparable gate and fin LER components by varying AR is beneficial to reduce the overall threshold voltage fluctuation. When we follow the optimistic predictions of LER in ITRS, we find that the threshold voltage variation induced by LER is well-controlled. In this scenario, the Source/Drain RDF starts to prevail LER as channel length is below 10 nm. Our results indicate that the difference between planar and FinFET devices the
overall threshold voltage variation becomes pronounced with the scaling of channel lengths.
Table 4.1 Specifications of model parameters used in the work.
Fig. 4.1 Threshold voltage variation for 25-, 18-, 13- and 9-nm channel length MOSFETs due to RDF, LER and EOT variation. LER is kept at rms=1.5nm and correlation length=30nm.
rms amplitude
correlation length = 30nm
Fig. 4.2 Id-Vg characteristic of 150 9-nm FinFETs due to fin LER.
Fig. 4.3 AR dependence of gate and fin LER fluctuations for 9-nm FinFETs.
1.0 1.5 2.0
20 30 40 50 60 70 80 90 100
S ig m a V th [ m V ]
Aspect Ratio
Total LER fin LER gate LER
MuG with Lgate=9nm Wtotal=27nm,|Vds|=0.05V
10 15 20 25 0
5 10 15 20 25 30
S ig m a V th [ m V ]
Channel length [nm]
RDF(channel+S/D) LER
EOT
Wtotal=3×Lgate
|Vds|=0.05V
Fig. 4.4 Threshold voltage variation for 25-, 18-, 13- and 9-nm channel length MOSFETs due to RDF, LER and EOT.
LER follows the ITRS roadmap with correlation length = 30 nm.
Table 4.2 Design parameters of planar and multi-gate MOSFETs.
0
Fig. 4.5 Comparison of individual variation source for planar and FinFET devices. LER is kept at rms=1.5nm and correlation length=30nm.
Fig. 4.6 Comparison of overall Vth fluctuation for planar and FinFET transistors. LER is kept at rms=1.5nm and correlation length=30nm.
Chapter 5 Conclusions
In this thesis, we have provided a systematic investigation of three important intrinsic parameter fluctuations, namely RDF, LER and EOT variation, with sophisticated simulation approaches for multi-gate MOSFETs.
For the RDF part, we have performed atomistic simulation to capture the impact of each dopant inside the channel. Our full Monte Carlo approach can capture both number and position components. In addition, the threshold voltage lowering of atomistic simulation with respect to continuous simulation has been observed in this work. In lightly doped devices, our study indicates that the position component dominates. In heavily doped devices, the number and position fluctuations are comparable and the implementation of full Monte Carlo simulation is required. Under the consideration of RDF, lightly doped FinFET (AR=2) is the recommended device design.
LER can be classified into fin- and gate-LER for multi-gate devices. In our simulations, we find that the gate and fin LER will become dominant for devices with critical dimension in channel length and fin width, respectively. An appropriate device design with comparable gate and fin LER variations may be helpful in reducing the overall LER. Because of the improved electrostatic integrity, multi-gate device with heavily doped channel has better immunity to LER at the price of worse RDF.
Comparing both the RDF and LER effects, we find that lightly doped FinFET is still
the best choice.
EOT variation can be grouped into oxide thickness variation (OTV) and dielectric constant fluctuation (DCF). We find that EOT variation is closely related to the bulk charge in channel region and this fluctuation source is small compared to RDF and LER.
In the pessimistic LER scenario, LER will become the dominant fluctuation due to the deteriorated electrostatic integrity. In the optimistic scenario, we find that the threshold voltage variation induced by the LER is under control even at 9-nm channel length devices. However, for multi-gate devices with well-controlled LER and sub-10nm channel length, the RDF from the Source/Drain encroachment will become increasingly important.
Under the same total width and Ioff, we have compared the variability of planar and multi-gate MOSFETs. Without effective improvement of LER, fin LER would become the dominant variation source for both planar and multi-gate transistors. If we assume each variation is independent and compare the overall fluctuations, we find that FinFET is better than planar MOSFETs and the difference between planar and FinFET devices increases with the scaling of channel length.
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簡歷 簡歷 簡歷 簡歷
姓名：范銘隆
生日：72 年 11 月 19 日 籍貫：台灣省台中市
地址：台中市向上路一段 245 巷一弄 19 號 學歷：
國立台中第一高級中學畢業 (88 年 9 月~91 年 6 月) 國立交通大學電機與控制工程學系畢業 (91 年 9 月~95 年 6 月) 國立交通大學電子工程研究所碩士班畢業 (95 年 9 月~97 年 9 月)
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