This dissertation concentrates on the studies of the novel low-temperature technologies applied on Pt/PSrT/Pt (MFM) and Pt/PSrT/Si (MFS) capacitors, used as advanced NVRAM devices. Several post-annealing techniques have been conducted to enhance material and electrical performance. The process parameters and consequent film properties are thoroughly studied to acquire the optimal conditions. Superior crystallinity and excellent electrical characteristics can be obtained, and the corresponding relationships for the materials to the electrical characteristics and concerning mechanisms are also explored in this dissertation.
Several conclusions are summarized as follows.
The surface morphologies, crystallinity, microstructure and electrical characteristics of PSrT films are noticeably dependent on the annealing conditions.
Films post-ELA show a denser and rougher surface morphology, larger value of O/(Pb+Sr) and the enhanced crystallinity of the upper region of films, resulting in the slight increase of dielectric constant and leakage current. As the annealing temperature increases, films indicate a surface image of distinctive grain clusters with pin holes, clear diffraction peaks of provskite structure, distinct C-E hysteresis loops and large dielectric constant, suggesting that the ferroelectricity is evidently improved by post-RTA. However, the leakage current is seriously increased due to the defects and interfacial diffusion induced by post-RTA.
Furthermore, films post-ELA and subsequent RTA at 600 oC exhibit the dense surface, specific two regions of microstructure, the largest dielectric constant of 492, and the inhibited leakage current density biased at +100-150 kV/cm. Concisely, the
superior crystallinity, improved ferroelectricity, longer lifetime and higher breakdown field of PSrT films can be achieved by the annealing technique of laser-assisted two-step process.
Low-temperature PLD PSrT films, deposited from 300 to 450 oC (Ts), have been demonstrated with dense and crack-free surface morphologies, evident crystallinity, and excellent ferroelectric properties. Among the Pt/PSrT/Pt capacitors, the 350
oC-deposited one exhibits strong (100) preferred orientation, maximum dielectric constant and good ferroelectricity. The dependence of dielectric constant on Ts is consistent with the ferroelectricity properties and preferred orientation. The leakage mechanism of Pt/PSrT/Pt capacitors reveals Schottky emission/Poole-Frenkel emission (SE/PFE) at lower/higher applied field. The high substrate temperature (Ts
≥ 350 oC) yields fewer interface states and better interfacial properties, and also shows fewer trapping states inside PSrT films, revealing that increasing Ts decreases the leakage current.
Moreover, the 400 oC-deposited PSrT films reveal minimal leakage current density biased at +170 kV/cm, nearly fatigued-free J-E characteristics after 1010 switching cycles, the highest breakdown field, and the best TDDB behavior, which are well explained by the defect chemistry. But the excessively high Ts (450 oC) may produce serious volatilization of Pb-O compounds, resulting in more vacancies and defects in the films, which may be the cause of degradation in crystallinity, high-field leakage currents and reliability properties.
The current density increases with temperature (Tm) and biased fields.
Low-temperature PLD PSrT films exhibit high stability of leakage current and film resistance below 150 oC, which is important and well for memory application. The NTCR behavior is observed in the temperature range of 100 – 390 oC. Furthermore, PSrT films exhibit strong NTCR behavior with a larger resistance range (log
(Rmax/Rmin) values than the PSrT ceramics do. The larger resistance range of the PLD PSrT films infers a potential application of thermistor sensor.
The preferred orientation, microstructure, and electrical characteristics of PSrT films could be apparently affected by ambient oxygen pressures (PO2 ) during
low-temperature PLD. The smoother surface morphology, the higher oxygen composition, and the stronger intensity of (110) orientation could be evidently influenced by increasing PO2 during PLD. The paraelectricity/ferroelectricity transition and dielectric constant are associated with the preferred orientation, tetragonality (c/a) and oxygen concentration. Films deposited at higher PO2 also
exhibit longer lifetime and higher breakdown field due to their smaller leakage current density. The leakage current analysis of Pt/PSrT/Pt capacitors reveal SE/PFE at low/high applied field, except the PSrT films deposited at PO2 = 200
mTorr only indicate SE behavior at the applied field range. PSrT films deposited at lower PO2 have porous surface and more oxygen vacancies (OVs) than those
deposited at higher PO2, yielding more interfacial states and more trapping states inside films and the fatigue properties are dominated by the interfacial states.
Consequently, PSrT films deposited at higher PO2 show improved interfaces and
fewer OVs, yielding fewer interfacial states and fewer deep trapping states inside films and the fatigue properties are dominated by deep trapping states.
PLD PSrT films, deposited on p-type Si wafers at low Ts from 300 to 450 oC, exhibit the perovskite phases without significant inter-diffusion at PSrT/Si interface.
The Ts strongly enhances the film crystallinity and affects electrical properties of Pt/PSrT/Si capacitors. As Ts increases, films have smaller leakage current and fewer
interfacial trap states at both electrode interfaces due to fewer structural defects correlated with enhanced crystallinity. It also reveals the higher ferroelectric gate capacitance, the larger width of
ε
r-E hysteresis loops, and larger memory windows (Vm) as Ts increases. In contract, films deposited at lower Ts (300 oC) exhibit the small and counterclockwise loop with the positive voltage shift, which is ascribed to the more negative charges in the trap states. However, films deposited at high Ts (450 oC) may produce serious volatilization of Pb-O compounds, incurring more chemical defects and the leakage degradation.Besides, the fixed charge density (Nfc) shows the minimum value of ~ 1012
2.85 × cm-2 for the films deposited at 400 oC. The trend of Nfc is consistent with the flatband voltage shift and the leakage current density is dominated by space charge limited conduction (SCLC). Furthermore, 450 oC-deposited films disclose excellent fatigue endurance before/after 1010 switching cycles with less than 11%
variation of Vm. As a consequence, the high-quality MFS structure without buffer layer between the PSrT films and the Si substrate could be realized by the low-temperature PLD.