Chapter 1 Introduction
B. Electrical Characteristics of Ferroelectric Capacitor
Leakage current and power consumption are the critical concerns of the electrical properties applied on the memory capacitor. The conduction mechanisms of high dielectric constant or ferroelectric materials are complicated, which may be associated with dielectric itself, grain boundaries, interfacial layers, electrodes, etc.
Besides, many high dielectric constant or ferroelectric materials are found to polarize in a manner that displays substantial time dependence. In addition to an essentially instantaneous or very high-frequency polarization, polarization charging current flow into such materials with a power-law time dependence of approximately t-n, where n ≤ 1 usually, as shown in Fig. 1-9 [15]. The charging current is the sum of the polarizing current, which dominates at short times because of its t-n behavior, and the true leakage current is referred to the current flow from electrons or holes, which dominates at long time. Therefore it should be very careful to identify the real and steady leakage current from the polarizing current with including a proper delay time during the I-V measurements. The leakage behaviors of the ferroelectric material can be expressed by several conductive models due to many complicated mechanisms coexisted. Usually the Ohmic contact is not easily formed between the high dielectric constant or ferroelectric materials and electrodes, unless the carrier concentration of dielectrics is high enough in the interface and results in tunneling effect. Besides, the ultra-thin dielectric insulator (i.e. thinner than 30 nm) behaves tunneling current. Because there is strong temperature dependence of leakage current in the dielectrics, both Schottky emission (SE) (or thermionic emission) and Poole-Frenkel (PFE) transport are the possible conduction mechanisms [16-18]. The equations of these two conduction mechanisms are shown as the following
[ ]
[ ] {
q (qE/ ) /kT}
Eexp B J :
E PF
= − ϕ
t− πε
dε
0 1/2PF , (1-6)
where A* is the effective Richardson’s constant, φB is the potential barrier height in the interface, B is a constant, φt is the trapped energy level, εd is the dynamic dielectric constant of the ferroelectric material in the infrared region, q is the unit charge, k is Boltzmann’s constant, J is current density, T is absolute temperature, correspondingly .In addition, many researches reported lots of other theories about the leakage current, such as space charge limited current (SCLC) [19-20] and the effect of grain boundaries [21]. Consequently, the conduction mechanisms should be determined by the practical conditions, which is associated with the form of energy band diagram constructed from dielectrics, electrodes, grain boundaries, etc. [21-24].
The tangent loss is due to the leakage current through the loss by a parallel resistance shown in Fig. 1-10 [7]. It is defined as the ratio of the leakage current through the resistance (IR) to the leakage current through the ideal dielectric (IC).
Therefore the value of tangent loss can be extracted from the following equations:
Figure 1-9 Short-time charging and discharging current in Pt/(Ba,Sr)TiO3/Pt, exhibiting power-law behavior for the relaxation current. [15]
,
where C is the capacitance, C0 is the geometric capacitance in free space, Z is impedance, ε’ and ε” are the relative real and imaginary dielectric constants, R and X are series relative real and imaginary impedance (resistance). Usually the tangent loss comes from two mechanisms: resistive loss and relaxation loss. In the resistive loss mechanism, the energy is consumed by mobile charges in the film. In the case of
Figure 1-10 The circuit model of tangent loss due to the leakage current through the loss by a parallel resistance. [7]
,
the relaxation loss mechanism, it is the relaxation of the dipole that expends the energy. Both two mechanisms of tangent loss are associated with the leakage current in the ferroelectric films, also investigated in this dissertation.
For the paraelectric or ferroelectric dielectrics, there are many electrical properties that will change with time, including the dielectric constant, remnant and saturation polarization, coercive field, tangent loss, leakage current, breakdown field, etc. Three time-dependent mechanisms will affect these electrical properties, which are aging, fatigue and resistive degradation.
Aging is generally defined as a spontaneous change in electrical properties with time, either under electrical stress or not. Fatigue is related to the ability decrease to switch the memory cell into the opposite state, after being kept programmed in one state for long periods of time. This effect is related to the polarization decrease in the hysteresis loop and it is proportional with the increasing number of switching cycles.
Both mechanisms are found in ferroelectric states and believed due to the pinning of domain walls from charge trapping, oxygen vacancies and associated defect dipoles [2, 25-27].
Figure 1-11 Scheme of different current regimes in metal-insulator-metal systems containing ferroelectric films. [28]
The third mechanism is time-dependent dielectric breakdown (TDDB), which is also referred as resistance degradation, for both paraelectric and ferroelectric dielectrics. It is defined as an increase of the leakage current under a constant applied electric field after prolonged times, also shown in Fig. 1-11 [28]. In this dissertation, the mechanisms of leakage, fatigue and TDDB for (Pb,Sr)TiO3 (PSrT) films were methodically addressed.
1-1-3 Fabrication Methods of Ferroelectric Thin Films
Experientially, fabrication methods of perovskite thin films can be categorized into three types, such as chemical solution deposition (CSD), chemical vapor deposition (CVD) and physical vapor deposition (PVD).
1. Chemical solution deposition (CSD)
The dielectric and ferroelectric films can be deposited by spin coating in CSD technique such as sol-gel [3, 22-24] and metal-organic deposition (MOD) [3].
Easy process, low cost, high throughput and simple facility requirement are the advantages of CSD technique. Although there are many advantages for CSD technologies, numerous problems still exist in this technology, such as the contamination control in the solvent and the porosity after baking. Besides, poor control of the perovskite phase stoichiometry can stem from varieties of the chemical source conditions. Poor step coverage and film crack after annealing are another problems.
2. Chemical vapor deposition (CVD)
The CVD technology, such as metal-organic chemical vapor deposition (MOCVD) [29, 30], liquid source misted chemical vapor deposition (LSMCVD) [3, 4], etc., can fabricate ferroelectric film for high-density devices due to excellent step coverage and uniformity. However, more complicated
mechanisms of CVD process results in difficult process control, and the high temperature post-treatments are needed for removing the carbon species from precursor. Besides, the process temperature of CVD is still very high for CMOS technology because of the chemical reaction requirement. Also utilizing metal-organic precursors, with which the technique is so called MOCVD, reduces the process temperature. However, more complicated mechanisms of the process are resulted and the remove of carbon species from precursors is needed with post-treatments (curing and annealing). Besides, LSMCD is one of CVD methods to deposit dielectrics. Only single precursor is misted by atomizer, carried to a chamber by Ar carrier gas and deposited on a substrate.
The drying (baking and curing) and high-temperature crystallization (annealing) processes are also needed. However, the uniformity for run to run is not stable.
3. Physical vapor deposition (PVD)
The PVD technique includes sputtering [3, 6-8], pulsed-laser deposition (PLD) [3, 31] … etc. Sputtering is a term used to describe the technology in which atoms are removed from the target surface by collision with high energy particles. Sputtering can afford to perform a uniform thickness using large area target. Besides, sputtering is a low cost, mature and easy-controlled technique.
However, poor step coverage and different sputtering yield for different elements are disadvantages of sputtering. PLD can easily achieve a wide variety of stoichiometry of ferroelectric film, which is simple, versatile, and capable of epitaxy growth and excellent crystallinity without subsequent high-temperature annealing. In this dissertation, the excmier pulsed-laser deposition technique was applied on the fabrication of PSrT film.
Mostly, ferroelectric thin films require low-temperature processes for IC and MEMS applications to prevent the formerly-fabricated structure from thermal damage. The high-temperature process will result in the volatilization of Pb-O in lead-titanate-based films, the loss of Bi content in bismuth-tatanate-based films, the diffusion of constituent elements and/or the chemical reactions between ferroelectric film and underlying layer, which in turn affects the film composition and degrades the electric properties of ferroelectric device [3, 4, 8]. Thus, a low-thermal budget process, a relatively low-temperature process with short thermal-duration, is certainly required for the preparation of PSrT thin films.
1-2 Challenges of Advanced (Pb,Sr)TiO3 (PSrT) Capacitors
1-2-1 Basic Properties and Literatures of PSrT Materials
PbTiO3 (PTO) film has been considered for applications in nonvolatile random access memory (NVRAM), but many drawbacks of this film must be improved, such as high coercive field, high crystallization temperature, and poor microstructure.
Normura and Sawada investigated polycrystalline samples of (Pb,Sr)TiO3 (PSrT) ceramic system and established a complete series of solid solution from PbTiO3 (PTO) to SrTiO3 (STO) since 1955 [41, 42]. STO films have a cubic structure at room temperature and characterized by lower crystallization temperature and lower dielectric constant than those of PTO films [43, 44]. PTO and STO films, at room temperature, behave a tetragonal structure (ferroelectric phase) and a cubic structure (paraelectric phase), respectively, because PTO has the Curie temperature (Tc) at 490
oC and STO has the Tc at -220 oC. The Tc can be linearly adjusted from -220 oC to 490
oC by varying the lead (Pb) content in the PSrT ceramics as indicated in Fig. 1-12 [42].
It is reported that PTO forms continuous range of solid solution with STO, the lattice
volume and the tetragonality (c/a, the ratio of c-axis/a-axis lattice constant) of PTO decrease with the increment of Sr/Pb composition ratio [44-47], presented in Fig.
1-13. The effects of lead substituted by strontium (Sr) in the PTO film decrease the crystallization temperature and offer a good control of the dielectric properties at room temperature [47, 48].
Moreover, PSrT have aroused considerable interest in the composite effect of negative and positive TCR (NTCR and PTCR), firstly found in 1988 [49]. In the past studies [50-55], PSrT ceramics are found to exhibit a NTCR behavior below Tc and the PTCR effect above Tc. Figure 1-14 indicates that the resistivity-temperature
Figure 1-12 Phase diagram of PbTiO3–SrTiO3
system. [42]
Figure 1-13 Lattice parameters at room temperature as a function of Sr/Pb composition. [45]
properties of PSrT ceramics are functions of the composition Sr/Pb ratio and also affected by the fabrication process, such as the different sintering techniques.
Therefore, PSrT is suitable for memory, sensor, frequency tuning devices and microwave applications due to its large electric-field-dependent dielectric constant and composition-dependent Curie temperature [42-60].
1-2-2 Challenges of PSrT Capacitors Integrated with CMOS IC Process
PSrT is the superior candidate material of future NVRAM, but there are still some challenges for the integrations of CMOS process.
1. CMOS devices deformed by high temperature process
In general, high deposition temperature (> 550 oC) of PSrT films is frequently Figure 1-14 Resistivity-temperature proprieties of PSrT ceramics affected by
(a) the composition Sr/Pb ratio [51] and (b) the sintering
techniques, such as microwave sintering (ms) and conventional furnace sintering (cs) [50].
(a)
(b)
applied to obtain good crystallinity of a perovskite structure [42, 47, 56-60], but the high temperature process may deform the junction profile and alter the gate length of the metal-oxide-semiconductor (MOS) FET, especially on the deep submicron scale. In stacked-capacitor structure, the dopant of MOS-FET is always implemented prior to the capacitor fabricated, which needs to be fabricated at low temperature to avoid the damage of the MOS-FET.
2. Suitable bottom electrode formation of PSrT capacitor
Usually, there is serious reaction or inter-diffusion between ferroelectric and bottom electrode during the deposition processing at high temperature. A thermally and electrically stable bottom electrode is indeed required for ferroelectric capacitor prepared at relatively low-temperature. Here, Table 1-1 lists down the most significant requirements of bottom electrode for stacked PSrT capacitor.
3. Dramatic variations of the electrical properties for the device operating in various temperatures
As mentioned, PSrT exhibits strong TCR properties, especially when temperature approaches Tc. It means that the electrical properties of PSrT, i.e.
leakage current, can dramatically change with temperature. Thus, the Tc of PSrT is necessary to be much higher than the temperature of memory operation.
In general, the operation junction-temperatures for consumer IC applications and is designed lower than 125 oC and qualification spec ranges from –0 oC to +120 oC (ambient temperature ranging of –40 – +120 oC). In this dissertation, the TCR properties of PSrT are performed to sure if the normal device operation can be obtained at ≥ 120 oC.
4. Unwilling interface properties between PSrT and silicon due to high temperature process
The high-temperature process will cause the diffusion of constituent elements and/or the chemical reactions between ferroelectric film and underlying silicon, which produce undesirably high density of interfacial trap states. Thus, a leaky interface and high leakage current will appear and destroy device characteristics of MFS-FET. A low-temperature technique is the key for the using of PSrT in 1T FeRAM.
Therefore, the thin film technologies of the PSrT capacitors must overcome the above tough blockade, or it should be impossible to achieve the practical NVRAM applications.
1-3 Method of Attack
It is clear that the low-temperature preparing techniques are necessary for PSrT films applied on memory. Furthermore, the noble metal platinum (Pt), with low resistivity, is considered as the electrode material because of its low power consumption and RC delay, and good stability to lead-based perovskite materials [4, 57]. In dissertation, we perform two approaches for this goal expressed as following
Table 1-1Summarized requirements of bottom electrode for stacked PSrT capacitor.
No.
1 2 3 4 5 6
List of the bottom electrode requirements Must remain conductive after PSrT deposition
Must be etchable down to deep submicron features Must not react with PSrT
Must maintain low contact resistance to underlying plug Must adhere to silicon, silicon dioxide & plug material Must be depositable using production tools
1. PSrT films post-treated by novel laser-assisted annealing
A low-thermal budget treatment, laser-assisted annealing, is proposed to improve the poor crystallinity of PSrT films deposited at extremely low temperature. The multi-layer structure of Pt/PSrT/Pt/Ti/SiO2/p-type Si was used in this work. The specific parameters of PSrT film preparation and post-annealings were carefully controlled. The thinner (~ 120 nm) PSrT film was adapted due to the limited depth of laser absorption in ferroelectrics. The novel laser-assisted two-step process, the combination of initial crystal seed induced by ELA and the grain growth carried out by subsequent RTA, which may be a potential technique to improve the crystallinity and electrical properties of PSrT films and systematically investigated in this dissertation.
2. PSrT films prepared by pulsed-laser deposition
A relatively low-temperature (≤ 450 oC) pulsed-laser deposition is conducted to prepare PSrT film for two architectures, MFM and MFS, which are used to simulate the devices of COB and MFS-FET, accordingly. The process parameters were seriously controlled, and the material characterizations and electrical properties were scientifically conducted to obtain the optimal process conditions. The corresponding mechanisms were also thoroughly studied in this dissertation.
1-4 Motivation
This dissertation dedicated in obtaining excellent characteristics of PSrT capacitor fabricated by novel low-temperature technologies. The motivation and the major concepts of this study are listed below.
1. Enhancing the crystallinity of PSrT films using the novel technique of laser-assisted annealing
Low temperature prepared PSrT films usually exhibit poor crystallinity, so the films have to be post treated by the annealing process to enhance the crystallinity and ferroelectricities. A novel low-temperature technique, using excimer laser annealing (ELA) and subsequent rapid thermal annealing (RTA), was introduced in this work due to its very low thermal budget and high crystallization efficiency. ELA is an extremely powerful technology to achieve a successful integration process of IC at low temperature due to the shallow depth of energy absorption without the damage of under layer devices.
Although ELA technology is widely used for preparing poly-Si thin film in thin film transistor (TFT) industry, but up to now, very few investigations report the ELA influence for ferroelectric films. Even though the process temperatures are high, the using of RTA process has been proposed for reducing the total thermal budget for depositing ferroelectric films. Thus, the novel laser-assisted two-step process, the combination of initial crystal seed induced by ELA and the grain growth carried out by subsequent RTA, which may be a potential technique to improve the crystallinity and electrical properties of PSrT films and systematically investigated in this dissertation.
2. Optimizing the process controls for PLD PSrT thin film fabricated at relatively low temperature
In general, the technique of the pulsed-laser deposition (PLD) is simple, versatile, and capable for growing a wide variety of stoichiometric oxide films without subsequent high-temperature annealing. Although a low-temperature technique is required for the deposition of PSrT in the semiconductor process,
controlling the crystallinity and ferroelectricities is normally more difficult with a low-temperature technique than with a high-temperature technique. The structural and the electrical characteristics of PLD ferroelectric films are strongly affected by the process parameters, such as substrate temperature and oxygen ambience. These process parameters and the electrical mechanisms were systematically studied to obtain the optimal process conditions.
3. Investigating the temperature dependent properties of PSrT film
PSrT have aroused considerable interest in the composite effect of negative and positive temperature coefficient of resistance (NTCR and PTCR). The TCR effect of PSrT bulk prepared by conventional ceramic solid state sintering processes has been reported. However, the TCR properties of PSrT thin films lack for systematically studies, which can be used as thermistor sensor embedded into micro-electro-mechanical systems (MEMS). Besides, the stable ferroelectricity of PSrT films is indeed necessary for memory application during the operation temperature of IC. PSrT films exhibit high stability of leakage current and film resistance below 150 oC, which is important and suitable for memory application. The strong negative temperature coefficient of resistance (NTCR) behavior at the ranging of 100 – 390 oC can be also obtained in film-type PSrT.
4. Investigating the feasibility of Low-temperature pulse-laser-deposited PSrT films applied in metal/ferroelectric/silicon (MFS) gate structure of 1T-FeRAM
PLD PSrT films can demonstrate well crystallinity and good ferroelectricities at low temperatures, which is a superior candidate for the MFS-FET devices. To date, much less is known about the properties of PLD PSrT films deposited on Si substrate. In our dissertation, the low-temperature PLD PSrT films can show
the enhanced crystallinity, few interfacial trap states and excellent fatigue endurance. Thus, a high-quality MFS structure without the buffer layer between PSrT films and Si substrate has been developed.
1-5 Thesis Organization
This dissertation reports how the novel low temperature techniques applied on the fabrication of PSrT capacitor. The multilayer structure of Pt/PSrT/Pt and the configuration of Pt/PSrT/Si were proposed to simulate the practical capacitor over a bit-line (COB) and metal/ferroelectric/semiconductor (MFS) configuration of 1T FeRAM, respectively. Material characterizations and electrical measurements are scientifically conducted in this dissertation.
Chapter 2 presents the details of the experimental concepts and the equipments of this dissertation. The experimental procedures, PSrT thin film fabrication processes, the treatments of post-annealings, and the techniques of material characterization and electrical measurement will be introduced in this chapter.
Chapter 3 reports the effects of various post-annealing techniques applied on the PSrT films. The detail analyses of physical properties and electrical characteristics are methodically discussed for PSrT films treated by RTA, ELA, and the novel laser-assisted two-step process.
Chapter 4 reveals the characteristics of the low-temperature PLD PSrT films. The well crystallinity and excellent ferroelectricities of PSrT can be achieved at low-temperatures by PLD technique. The corresponding analysis of the material, electrical properties and mechanisms are systematically performed in this chapter.
Chapter 5 investigated the influences of ambient oxygen pressure on the
low-temperature PLD PSrT films. Process parameters were carefully controlled and
low-temperature PLD PSrT films. Process parameters were carefully controlled and