Pulse-Laser-Deposited (Pb,Sr)TiO
3Films in Metal/Ferroelectric/Silicon Structure
7-1 Brief Concept of Metal/Ferroelectric/Silicon (MFS) Structure
Ferroelectric based gate insulator field-effect transistors (FETs) have been investigated as future nondestructive read-out (NDRO) nonvolatile memory devices [19, 20, 95-100]. Among several kinds of ferroelectric gate FET structures, a metal/ferroelectric/semiconductor (MFS) configuration is particularly promising due to the advantages of simple fabrication processes, low power consumption (without the voltage drop across the buffer insulator) and small memory cell size compared to its alternatives. MFS-FET exploits the ferroelectric field effect, which is the modulation of conductivity by the electrostatic charges induced by ferroelectric polarization, and thus requires the direct deposition of ferroelectric thin films on silicon (Si) wafer. Thin films of various ferroelectric materials, such as Pb(Zr,Ti)O3
(PZT), YMnO3 (YMO), SrBi2Ta2O9 (SBT), Bi4Ti3O12 (BIT), and CaBi2Nb2O9 (CBN) have been investigated for MFS-FET devices [19, 20, 96-100]. These materials are usually processed at high-temperatures (> 600 oC) to obtain the good crystallinity of a perovskite structure [19, 20, 96-99]. However, the high-temperature process will cause the diffusion of constituent elements and/or the chemical reactions between ferroelectric film and underlying silicon [4, 101, 102], which produce undesirably high density of interfacial trap states [19, 20, 97-100]. In addition, the volatilization of Pb-O in lead-titanate-based films and the loss of Bi content in bismuth-tatanate-based films, processing at high temperatures, always degrade the microstructure and
reliability of ferroelectric devices [4, 62, 103]. Hence, a relatively low-temperature process is indeed required for the deposition of ferroelectric thin films for MFS-FET applications.
(Pb,Sr)TiO3 (PSrT) is feasible for memory applications due to its large electric-field-dependent dielectric constant and composition-dependent Curie temperature [47, 48, 84]. The (Pb,Sr)TiO3 (PSrT) solid-solution film is constituted by PbTiO3 and SrTiO3. The effect of lead (Pb) substituted by strontium (Sr) in the PbTiO3
film will decrease the crystallization temperature and offers a good control of dielectric properties at room temperature [47, 84]. To deposit PSrT films, a pulsed-laser deposition (PLD) technique is applied, which is feasible for fabricating films with complex compounds and capable of growing a wide variety of stoichiometric oxide films without subsequent high-temperature annealing. Hence, PLD is a potential technique, which could be integrated into low-temperature semiconductor processing. To date, much less is known about the properties of PLD PSrT films deposited on Si substrate. In this chapter, the low-temperature PLD process can avoid these problems as stated and make several improvements of film properties. Thus, a high-quality MFS structure without the buffer layer between PSrT films and Si substrate has been developed.
7-2 Experiments
Si (100) has the lowest surface state density, which is superior to Si (110) and Si (111). In order to reduce the effect of surface states, (100) orientation p-type Si wafers were employed as the substrates in this study. After initial RCA cleaning process, thin PSrT films (200 nm thick) were then deposited on p-type Si substrates by a PLD system (LPX 210i, Lambda Physik) utilizing KrF excimer laser (λ=248 nm) radiation.
A set of optical lens was used to focus the laser beam over the (Pb0.6Sr0.4)TiO3 target in vacuum. The vacuum chamber was pumped down to a base pressure of 0.1 mTorr and then refilled O2 as reactive gas. The vaporized species of the target were transferred and deposited on the substrate heated by a thermal heater. The deposition temperature (substrate temperature, Ts) was used as a variable from 300
oC to 450 oC, calibrated at the wafer upper surface. The target to substrate distance was 4 cm. During the PLD process, the oxygen ambient pressure was 80 mTorr. The laser pulsed rate and the average energy fluence were 5 Hz and 1.55 J/cm2 per pulse, respectively.
An Auger electron spectroscope (AES) (Auger 670 PHI Xi, Physical Electronics) was used to analyze the element depth profile of PSrT films. The crystallinity of films was analyzed by X-ray diffractometer (D5000, Siemens). The optical properties of refraction index (n) and extinction coefficient (κ) were investigated by an n&κ analyzer (1280, n&κ Technology). The n and κ are influenced by the electronic structure and/or crystallinity of the film. After the physical examination, patterned platinum (Pt) top electrodes, with a thickness of 100 nm and a diameter of 75 μm, were deposited by sputtering process to form a Pt/PSrT/Si (MFS) capacitor structure.
The thickness of PSrT films was controlled as ~ 200 nm to deduct the influence of film thickness on electrical properties. The noble metal platinum, with low resistivity, is considered as the electrode of Pt/PSrT/Si capacitor because of its small leakage current, low power consumption, small RC delay, and good thermal stability to lead-based perovskite materials [4]. Then, the native oxide on the backside of Si wafer was removed by HF etching. An aluminum (Al) film (500 nm thick) was sequentially deposited on wafer backside to form Si/Al bottom electrode. The combination of a semiconductor parameter analyzer (4156C, Agilent Technologies) and a probe station was used to measure the leakage current (I-V characteristics). A
capacitance-voltage (C-V) analyzer (Package 82 system C-V 590, Keithley) was also used to measure C-V curves at 100 kHz. A pulse generator (8110A, Hewlett Packard) and a pulse/function generator (8116A, Hewlett Packard) were connected together with low noise BNC cables to generate +3 V/-3 V bipolar wave pulsed at 1 MHz, confirmed by an oscilloscope (54645A, Hewlett Packard), as an input signal for the measurement of polarization switching degradation (fatigue).
7-3 Physical Analysis
Figure 7-1 reveals AES depth profiles of PLD PSrT films deposited on Si (100).
Without standard samples to calibrate the sensitivity factor, the count intensity of elements presented here can only be semi-quantitative, but not absolute. No evident difference is observed between the depth profiles of films deposited at 300 oC and 450
oC. As can be seen from the abrupt interface profile, no significant inter-diffusion of oxygen, titanium, and silicon between PSrT films and Si substrate occurs at such low temperatures.
Figure 7-2(a) presents the X-ray diffraction pattern of PSrT films deposited at various Ts. All the diffraction peaks of these data are indexed as (100), (110), (111), (200), (210) and (211) planes of (Pb1-xSrx)TiO3 perovskite phases [47, 48, 56, 84]. The crystalline PSrT films appear at such low temperatures because (i) the addition of strontium makes the crystallization temperature of PSrT lower than that of PZT [47], and (ii) the PLD technique could preserve the crystalline phases and stoichiometric composition of the target material at low Ts [31, 84]. Moreover, the intensities of the (100), (111), (200), (210) and (211) orientations increase significantly with the increasing Ts. Figure 7-2(b) quantizes the XRD spectral analysis using Eq. (4-1). X100, the relative proportion of the (100) orientation, increases as Ts increases and shows
the maximum at Ts = 450 oC, indicative of strong (100) preferred orientation. It infers that the intensity of (100)-oriented peak of PSrT films is strongly enhanced by the using of Si (100) substrate as opposed to that on Pt/SiO2/Si (Fig. 4-4).
Figure 7-1 AES depth profiles of PLD PSrT films deposited on Si (100) wafers at (a) 300 oC and (b) 450 oC.
Figure 7-2 (a) X-ray diffraction pattern and (b) texture characteristics of PLD PSrT films deposited on Si at various substrate temperatures.
20 30 40 50 60
Substrate Temperature (
oC)
I100
I110
X
100R e lative Pr oport ion ( % )
(a)(b)
7-4 Electrical Analysis
The Pt/PSrT/Si capacitor with aluminum backside electrode is used as MFS configuration for electrical measurements. These MFS devices require the ferroelectric film to be deposited on silicon surface directly, and utilize their remnant polarization to control the surface potential of silicon. Thus the interfacial states and the leakage current are very important for normal FET operations. Figure 7-3 displays the curves of current density versus electric field (J-E) and an extraction of slope, α, in different regions of log (J)-log (E) plots, which gives an idea of the conduction process involved under the influence of varying electrical fields. Initially, the leakage current shows an ohmic behavior at low fields (α ≤ 1). At slightly higher electrical fields (α ~ 6 - 8.8), it shows an onset of the linear region, attributed to the space charge limited conduction (SCLC) mechanism [19, 20]. The inhibited leakage current observed in PSrT films deposited at 300 - 400 oC is correlated with the fewer structural defects because of the enhanced crystallinity as shown in Fig. 7-2.
Comparing the data at Ts = 400 oC and Ts = 450 oC, the increasing current density may correspond to the more chemical defects due to the more serious volatilization of Pb-O of PSrT films at higher temperature (≥ 450 oC) [4, 62].
Figure 7-3 Current density versus electric field (log (J)-log (E)) curves of Pt/PSrT/Si capacitors prepared at various substrate temperatures.
The corresponding slopes in different regions are denoted as α.
0.9 1.2 1.5 1.8 2.1 2.4
Figures 7-4 reveal the experimental and fitted log (J/T2) versus E1/2 (Schottky emission) plots of Pt/PSrT/Si capacitors applied at positive/negative bias. If the leakage current follows Schottky emission behavior, a log (J/T2) against E1/2 plot should be linear and the dashed lines work as the fitted results. It is noted that Figs.
7-4(a) and 7-4(b) reveal a similar tendency. The decreasing values of log (J/T2) against E1/2 present the inhibited interfacial trap states as Ts increases from 300 to 400
oC. As Ts increases to 450 oC, however, the increasing values of log (J/T2) against E1/2 indicate more trap states at both electrode interfaces. A strong polarity dependence of the leakage current is noted due to the different materials used for the top (Pt) and bottom (Si) electrodes as shown in Figs. 7-4(a) and 7-4(b) [100]. The polarity dependence is connected with the different Schottky barrier height (
ϕ
b1andϕ
b2) at the Pt/PSrT and PSrT/Si interfaces, expressed as the following relations [77, 104]f m 1
b
ϕ
qχ
ϕ = -
, (7-1) Figure 7-4 Experimental and fitted log (J/T2) versus E1/2 (Schottky emission) plotsof Pt/PSrT/Si capacitors at (a) positive bias and (b) negative bias.
4 5 6 7 8 9
f
1.12 eV), k is the Boltzmann’s constant, T is the absolute temperature, ni is the intrinsic carrier concentration of Si, and the doping concentration (Na) is about
2 × 10
15 cm-3, according to the p-type Si resistivity of 5-10 Ωcm [77, 104, 105].The values of the electron affinity of PZT, BST, and SrTiO3 are reported as
χ
PZT = 3.5 eV, χBST= 4.0 eV, and χSTO= 4.1 eV, accordingly [105, 106]. Thus, the electron affinity of PSrT,χ
f , may be roughly assumed as 3.8 eV. Hence, the Schottky barrierheights could be calculated as
ϕ
b1= 1.3 eV andϕ
b2= 0.8 eV. In addition, the more interfacial trap states result in more charge accumulation and a severe image-force effect at the edge of electrodes, leading to the decrease of Schottky barrier height. The image-force lowering (Δφ) can be expressed as [2, 76]2 dielectric constant of the ferroelectric material. Figure 7-5 illustrates the schematic drawing of the electron energy band for Pt/PSrT/Si. In general, the electron energy band at the interfaces of electrodes reveal that PSrT films act as n-type semiconductors due to the generation of oxygen vacancies in ABO3 perovskites [2, 18, 76]. The band gap of PSrT films, Efg, is measured as 3.52 ~ 3.66 eV by optical
investigation of refraction index (n) and extinction coefficient (κ). The values of Efg are approximately close to the reported value of 3.6 eV for PbTiO3 [21].
Figure 7-6 displays the hysteresis loops of dielectric constant versus electric field (
ε
r-E) for the Pt/PSrT/Si capacitors deposited at various Ts, sweeping at 0.05 V/100 ms from a negative bias to a positive bias and reversing it again. The dielectric constant of hysteresis loops presents the series properties of the capacitor of the Si depletion region and the capacitor of ferroelectric films (CPSrT). The CPSrT can be calculated from maximum dielectric constant ofε
r-E hysteresis loops, expressed as:d A ε ε
CPSrT
=
r,max×
0×
, (7-4)where A is the capacitor area (Pt electrode area), d is the thickness of ferroelectric film, Figure 7-5 Schematic drawing of the electron energy band for the Pt/PSrT/Si
structure.
△φ
qχi~ 0.95 eV
Ev
Interfacial states
Ec Ef
Pt PSrT SiOx p-type Si
Efg ~ 3.6 eV
Eg = 1.12 eV
Eig = 9 eV
qφm~ 5.3 eV qχf~ 3.8 eV qχSi~ 4.05 eV Ev
max
ε
r, is the maximum dielectric constant. It is seen that the CPSrT and the width of hysteresis loops increase as Ts increases, which could be ascribed to the enhanced crystallinity of the film (Fig. 7-2) m. In addition, films deposited at higher Ts (≥ 350 oC) show the clockwise hysteresis loops, whereas those deposited at 300 oC reveal the counterclockwise loop. The clockwise hysteresis means that ferroelectric dipole switching governs the surface potential of p-type Si, which is the desired switching mode for the operation in MFS-FET devices [19, 100, 107]. In contrast, the counterclockwise loop could be attributed to the numerous border trap states induced by the poor-quality interfacial native oxide (SiOx) between ferroelectric film and Si, since SiOx can be found anywhere in the MFS capacitors [19, 97, 98, 107].Moreover, 300 oC-deposited films indicates a positive voltage shift of C-E loops compared to those deposited at higher Ts (≥ 350 oC). The negative charge causes the shift toward positive voltage and dominates the electrical properties of the PSrT/Si interface.
Figure 7-6 Hysteresis loops of dielectric constant-electric field (
ε
r-E) for the Pt/PSrT/Si capacitors prepared at various substrate temperatures.Furthermore, the fixed charge density (Nfc) could be estimated from the C-E loops by the following formula [19, 20]:
)/(qA)
-(V C
Nfc
=
PSrT fbϕ
ms , (7-5)where Vfb is the flatband voltage, φms is the effect function remainder between metal (Pt) electrode and semiconductor (Si) substrate, and A is the Pt electrode area. Figure 7-7(a) points out the minimum Nfc of ~
2.85× 10
12 cm-2 for films deposited at 400 oC.It is found that the trend of Nfc is consistent with that of the leakage current density biased at +150 kV/cm (evaluated from Fig. 7-3), where the conduction is dominated by the SCLC mechanism. Figure 7-7(b) presents the memory windows (Vm), extracted from Fig. 7-6, of Pt/PSrT/Si capacitors prepared at various Ts. The value of Vm
increases as Ts increases and shows the maximum of 1.785 V for 450 oC-deposited films, which is associated with the larger CPSrT and the enhanced crystallinity. The Vm
can be linked to twice the coercive voltage (2Vc) and severely narrows down by the charge injection into the border traps of SiOx located at the PSrT/Si interface, which can be described as [97, 98]
ci c
m 2V V
V
= +
, (7-6)where Vci is the flatband voltage shift due to charge injection. Here, the values of 2Vc
are 2.06 V, 1.7 V, 1.8 V, and 2.4 V (Fig. 4-8), respectively, which could be referred to the polarization versus electric field (P-E) curves of Pt/PSrT/Pt capacitors prepared at Ts = 300 - 450 oC. From Eq. (7-6), the Vci shows the minimum value of ~ -1.57 V for films deposited at 300 oC and the maximum value of ~ -0.3 V for films deposited at 350 - 400 oC. In addition, the Vci slightly changes to -0.61 V as Ts increases from 400 oC to 450 oC. Consequently, the evolution of Vci agrees well with the Nfc, the shift of C-E
loop, and leakage currents as mentioned above.
300 350 400 450
0.0 0.5 1.0 1.5 2.0 2.5
Memory Window (V)
Substrate temperature(oC)
300 350 400 450
2x1012 4x1012 6x1012 8x1012
10-10 10-8 10-6 10-4
Fixed Charge Density (cm-2 )
Substrate temperature(oC)
C u rr ent De ns ity (A /c m
2)
(b) (a)
Figure 7-7 (a) Fixed charge density (Nfc) and leakage current density (at +150 kV/cm) as a function of substrate temperatures for Pt/PSrT/Si structures. (b) Memory window (Vm) of Pt/PSrT/Si capacitors prepared at various Ts.
7-5 Fatigue Properties
Figure 7-8 demonstrates the fatigue properties of
ε
r-E hysteresis loops for Pt/PSrT/Si capacitors prepared at 450 oC before/after (fresh/fatigued) 1010 switching cycles. The variation of memory windows is less than 11% before/after the fatigued switching cycles. In summary, it suggests that PLD PSrT films deposited at suitable substrate temperatures could be promising for MFS-FET devices.0 500 1000 1500 2000
Fresh Fatigued
Dielectric Constant
Electric Field (kV/cm)
150 100
50 0
-50 -150 -100
Figure 7-8
ε
r-E hysteresis loops of Pt/PSrT/Si capacitors prepared at 450 oC before/after (fresh/fatigued) 1010 fatigued switching cycles.7-6 Summary
PLD PSrT films, deposited on p-type Si wafers at low substrate temperatures (Ts) from 300 to 450 oC, exhibit the perovskite phases without significant inter-diffusion at PSrT/Si interface. The Ts strongly enhances the film crystallinity and affects electrical properties of Pt/PSrT/Si capacitors. As Ts increases, films have smaller leakage current and fewer interfacial trap states at both electrode interfaces due to the fewer structural defects correlated with enhanced crystallinity. It also reveals the higher ferroelectric gate capacitance, the larger width of
ε
r-E hysteresis loops, and larger memory windows (Vm) as Ts increases. In contract, films deposited at lower Ts(300 oC) exhibit the small and counterclockwise loop with the positive voltage shift, which is ascribed to the more negative charges in the trap states. However, films deposited at high Ts (450 oC) may produce serious volatilization of Pb-O compounds, incurring more chemical defects and the leakage degradation. Besides, the fixed charge density (Nfc) shows the minimum value of ~ 2.85 ×1012 cm-2 for the films deposited at 400 oC. The trend of Nfc is consistent with the flatband voltage shift (Vci) and the leakage current density is dominated by space charge limited conduction (SCLC). Furthermore, 450 oC-deposited films disclose excellent fatigue endurance before/after 1010 switching cycles with less than 11% variation of Vm. As a consequence, the high-quality MFS structure without buffer layer between the PSrT films and the Si substrate could be realized by the low-temperature PLD.