Chapter 1 Introduction
1.2 T HESIS O RGANIZATION
In chapter 2, the basic concepts of performance metrics used to characterize ADCs is introduced. Then, the architectures of ADC are reviewed. We also summarized the characteristic of those ADCs at last. In chapter 3, the pipeline architecture is briefly introduced. Furthermore, the error sources of each stage of pipelined ADC are discussed. In chapter 4, the design and analysis of the building block will be presented. In chapter 5, we made conclusions for our design, and the future work is given.
Chapter 2
Fundamentals of Pipelined Analog-to-Digital Converter
2.1 OVERVIEW
The analog-to-digital converters are widely used in many applications. A high-speed ADC is usually applied to video system, and multi-media system, etc.
Digital processing, storage, and transmission of video information require an ADC can be operated with a sample rate, range from 20MHz to 100MHz, and a resolution range from 8-bit to 12-bit.The summary of ADC in systems are shown in Table 2.1 [1].
For instance, the conventional NTSC TV system requires 8-bit resolution and a 20MHz sampling. However, recently proposed high definition television (HDTV) digital VTR in Japan requires 10-bit resolution and 75 MHz sampling for 1125 scanning lines, a 60Hz field rate with 30 MHz bandwidth luminance signal, and two 15MHz bandwidth color-difference signals [2].
Architectures for realizing ADC can be roughly divided into three categories—low-to-medium speed, medium speed, and high speed as shown in Table 2.2 [3]. Each of them is the different trade-off between resolution, speed, area and power. In this chapter, we first discuss performance specifications to characterize ADCs, and then describe the design details for these different Architectures. In the end of this chapter, we summarized and chose the suitable architecture to meet our target specification.
Table2.1 Summary of ADC in systems
Applications Requirements
NTSC/PAL Decoder 8Bits, 14-17MHz
HDTV 8-10Bits, 50-75MHz
CATV Channel Modems 8-12Bits, 50-75MHz
ADSL/HDSL Transceivers 12-16Bits,3MHz
CDDI Transceivers, VG 8-10Bits, 30-60MHz Mag Storage Read Channel 6-8Bits, 75-150MHz
High Performance Imager 12Bits, 75MHz
Scanner 10-16Bits, 6-40MHz
LCD Monitor 8Bits, 150MHz
APS CMOS Sensor 8-12Bits, 20MHz
Table2.2 Different A/D converter architectures Low-to-Medium
Integrating Successive approximation Flash
Oversampling Algorithmic Two-step
Interpolating
Folding
Pipelined
Time-interleaved
2.2 ADCPERFORMANCE SPECIFICATIONS
ADCs are characterized in a number of different ways to indicate the performance capability, cost, and ease of use. Some of the most important characteristics of ADCs are introduced below.
2.2.1 Resolution and LSB
Resolution describes the fineness of the quantization performed by the ADC.
Sometimes it is called as effective number of bits (ENOB). A high resolution ADC divides the input range into a large number of sub-ranges than a low resolution converter. Resolution is usually defined as the base 2 logarithm of the number of sub-ranges which the ADC inputs range is divided into. This quantity is referred to the number of bits resolved by the ADC. Thus, for a fixed full scale input range, the high resolution ADC can resolve smaller signals than a low resolution ADC.
Resolution is usually degraded by noise or nonlinearity. Therefore, most techniques for characterizing the true resolution of an ADC are to measure either noise, nonlinearity, or both [4].
LSB means least significant bit size, can be expressed by Equation (2.1).
max 2N
LSB=V (2.1)
Where Vmax is the full-scale voltage, N is the ADC’s resolution. It is useful to define LSB to be the voltage change when one LSB changes, particularly in measure errors.
2.2.2 Nonlinearity
Most ADCs are intended to have a transfer characteristic approximating a straight line. As the resolution increases, the input-output characteristic of the ADC is
more close to a straight line. The transfer characteristic for ideal ADCs progresses from low to high in a series of uniform steps. Therefore, nonlinearity is present even in an ideal ADC. The transfer characteristic of a practical ADC contains steps which are not perfectly uniform, and this deviation generally contributes to further non-idealities. Such non-idealities can be expressed in several ways as shown in Figure 2.1. An error which causes all thresholds to shift from their ideal positions by an equal amount is called an offset error. Non-ideality which results in an erroneous quantizer step size is called gain error or scale factor error. Linearity error refers to the deviation of the actual threshold levels from their ideal values after offset and gain errors have been removed. Excessive linearity error results in missing codes.
Figure 2.1 Quantization transfer functions including error sources (a) Offset error, (b) Gain error, (c) Linearity error, (d) Missing code.
Two types of nonlinearity are used to characterize this deviation. Differential nonlinearity (DNL) measures how far each of step sizes deviates from nominal value of the step size. Integral nonlinearity (INL) is the difference between the actual transfer characteristic and the straight line characteristic the ADC is intend to approximate. DNL and INL are both plotted as a function of code. DNL and INL are generally expressed in term of LSB of the converter input. Figure 2.2 shows INL and DNL, which can be expressed as Equation (2.2) and Equation (2.3).
( 1) ( ) ( ) UB i UN i 1 DNL i
LSB
= + − − (2.2)
( 1) ( )
( ) UB i UN i ideal 1
INL i
LSB
= + − − (2.3)
where UB(i) is transition level of i-th code [4] [5] [6] [7].
Figure 2.2 Transfer characteristic of ADC showing INL and DNL.
2.2.3 Signal to Noise Ratio
The signal to noise ratio (SNR) is the ratio of signal power to noise power in the output of ADC. One common way to measure SNR is plot the spectrum of the output of the ADC. The SNR is calculated by measuring the difference between signal peak and noise floor and including a factor to adjust for the number of samples used to generate the spectrum as shown below.
( ) _ ( ) _ ( ) 10 log
SNR db =signal peak db −noise floor db − N (2.4)
The last term in the Equation (2.4) can be understood as follows. To generate an N point Faster Fourier Transform (FFT) of a signal, N samples of the signal are taken.
Sampling the signal N times increase signal power by a factor of and the noise power by a factor of N. Thus the SNR is increased by a factor of N and the SNR of the FFT is higher than SNR in one sample of the signal. The SNR improvement in db is 10logN, and the noise floor in the FFT becomes lower relative to the signal as more samples are taken. Figure 2.3 illustrated this idea [8].
N2
Figure 2.3 Procedure for computing SNR from an N point FFT
The use of quantization introduces an error, q(n), defined as the difference between input signal x(n) and the output y(n). The error is called quantization noise.
We can build a model to calculate as shown in Figure 2.4
(a) (b)
Figure 2.4 (a) The difference between input signal x(n) and the output y(n).
(b) Quantization error of an ADC.
It is assumed that the quantization error Q is a uniformly distributed random variable, and the interfering effect of the quantization noise on the quantizer input is similar to that of thermal noise. The probability density function for such an error signal will be a constant value, as shown in Figure 2.5.
Figure 2.5 The probability density function of the quantization error.
The equation of the quantization error Q is expressed as Equation (2.5).
Therefore, the R.M.S value of the quantization error is
2 2 2 2
In general, when the quantization noise is uniformly distributed over the interval , the R.M.S quantization noise voltage equals
LSB/ 2
±V VLSB/ 12 and is independent
of the sampling frequency, fs, and input signal.
The SNR formula is to assume that is a sinusoidal waveform between and . Thus, the AC R.M.S value of sinusoidal wave is
Note that Equation (2.9) gives the best possible SNR for an N-bit ADC. However, the idealize SNR decreases from this best possible value for reduced input signal levels [4]
[5].
2.2.4 Signal to Noise + Distortion Ratio
The signal to noise plus distortion ratio (SNDR) is also often used to measure the performance of an ADC. It measure degradation due to the combined effect of noise, quantization errors, and harmonic distortion. The SNDR of a system is usually measured for a sinusoidal input and is a function of the frequency and amplitude of the input signal. When a sinusoidal signal of a single frequency is applied to a system, the output of the system generally contains a signal component at input frequency.
Due to distortion, the output also contains signal components at harmonics of the input frequency. An ADC usually samples an input signal at finite rate. As the result, some of the harmonic distortion products are aliased down to lower frequencies.
Furthermore, the ADC adds noise to the output, and this noise is generally present to some degree at all frequencies. The SNDR of the ADC is defined as the ratio of the signal power in the fundamental to the sum of the power in all of the harmonics, all of the aliased harmonics, and all of the noises [8]. It can be expressed by Equation (2.10).
Dynamic range is another useful performance benchmark. Dynamic range is a measure of the range of input signal amplitudes for which useful output can be obtained from a system. Dynamic range can be defined in a number of different ways.
One way to define dynamic range for a system is as follows. Apply a sinusoidal input of a single frequency to the system and vary the amplitude. Measure the maximum power obtainable from the system at the input frequency. The dynamic range could be
defined as the ratio of the maximum power at the fundamental frequency to the output power for a minimum detectable input signal. The minimum detectable input signal power is the value of the signal power when the signal to noise ratio is 0dB. If the noise power is independent of the size of the signal, the dynamic range is equal to the SNR at full scale. However, in some cases the noise power increases as the signal level increases. In these cases, the maximum SNR is less than the dynamic range [4]
[5].
2.2.6 Spurious Free Dynamic Range
The spurious free dynamic range (SFDR) is the ratio of the largest spurious frequency and the fundamental frequency. This is the difference between the R.M.S input signal and highest frequency spur at the output of the ADC as showing in Figure 2.6.
Figure 2.6 An example of how SFDR is measured in a FFT test.
2.2.7 Sampling Rate, Conversion Time and Latency
The sampling rate indicates the number times the input signal is sampled per second. Conversion time means converter data time from sample to data out, and latency is the clock cycle from sample edge to data out edge. Figure 2.7 shows examples above.
Figure 2.7 Definitions of sampling time, conversion time and latency
2.2.8 Input Bandwidth
ADC’s resolution is a function of the frequency of the input signal. At high input frequencies, the SNDR of the ADC output can be reduced by a number of effects. The input bandwidth of the ADC is the input frequency at which the SNDR is 3dB below the maximum value.
2.2.9 Input Capacitance
Input capacitance is the capacitive load presented by the ADC to the circuit driving it. The input capacitance of an ADC is an important parameter because the input capacitance can load the circuit driving the ADC and degrade its performance.
2.2.10 Input Signal Swing
The input signal swing indicates the maximum and minimum values that the input signal may have without driving the ADC out of range or resulting in an unacceptable level of distortion.
2.2.11 Power Dissipation
Power dissipation is becoming an important ADC specification because many ADCs are being implemented in portable systems powered by a battery with limited energy. Reducing power dissipation can reduce system weight or improve battery life.
Reducing power dissipation can also make it easier to keep the temperature of the ADC at a reasonable level.
2.3 ARCHITECTURES OF ADC
2.3.1 Flash ADC Flash ADCs, also known as parallel ADCs, are the standard approach for
realizing very-high-speed converters. Figure 2.8 shows a block diagram of an N-bit flash ADC. It consists of 2n-1 comparators, are used to directly measure an analog signal to a resolution of n bits. The flash architecture has the advantage of being very fast, because the conversion occurs in a single ADC cycle. The disadvantage of this approach is that it requires a large number of comparators that are carefully matched and properly biased to ensure that the results are linear. Since the number of comparators needed for an N-bit resolution ADC is equal to 2n-1, limits of physical integration and input loading keep the maximum resolution fairly low. For example, a 4-bit ADC requires 15 comparators, an 8-bit ADC requires 255 comparators, and a 10-bit ADC would require 1023 comparators.
The flash ADCs are suitable for applications requiring very large bandwidths.
However, flash converters consume a lot of power, have relatively low resolution, and can be quite expensive. This limits them to high frequency applications that typically cannot be addressed any other way. Examples include data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives [3] [9] [10].
Figure 2.8 Block diagram of an N-bit flash ADC.
2.3.2 Sub-ranging ADC
In the field of high speed ADCs, the flash ADCs remain dominant due to their one-clock-cycle conversion; however, they suffer from large power consumption and area usage due to their 2N comparators. For applications such as imaging, video and digital communication, where high resolution is required, the sub-ranging structures, first introduced by Dingwall and Zazzu [11], have gradually begun to replace the flash
ADC. Sub-ranging ADC uses fewer comparators than parallel flash ADCs. Instead of using one comparator per LSB like a flash converter does, a sub-ranging ADC uses fewer comparators, draws less power, has lower input capacitance, and can attain higher resolutions. Although not as fast as a parallel ADC, sub-ranging ADCs can digitize at speeds greater than 100 Ms/s at 8-bit resolution [12]. They can resolve signals to 16 bits at slower speeds. Figure 2.9 shows a block diagram of a 10-bit sub-ranging ADC that uses two 5-bit stages to digitize the analog input signal. The first ADC converts the upper 5 bits while the second stage converts the lower 5 bits.
This design uses 62 comparators (31 for each ADC) rather than the 1023 comparators required by a 10-bit flash converter. Sub-ranging ADCs often find use in RF test equipment, lower-speed digitizing oscilloscopes, and high-end PC plug-in digitizer cards and PC-external data-acquisition systems.
Figure 2.9 Conventional block diagram of a 10-bit sub-ranging ADC.
2.3.3 Successive Approximation ADC
The successive-approximation architecture can be thought of as the other end of the spectrum from the flash architecture. While a flash converter uses many comparators to converter in a single cycle; a successive-approximation-register (SAR) converter conceptually uses a single comparator to converter in many cycles. To understand the basic operation of SAR ADC, knowledge of the search algorithm referred to as a “binary search” is helpful [3]. Figure 2.10 shows block diagram of a SAR ADC. To implement the binary search algorithm, the N-bit register is first set to midscale (that is, 100... .00, where the MSB is set to '1'). This forces the DAC output (Vdac) to be Vref/2, where Vref is the reference voltage provided to the ADC. A comparison is then performed to determine if Vin is less than or greater than Vdac. If Vin is greater than Vdac, the comparator output is logic high or '1' and the MSB of the N-bit register remains at '1'. Conversely, if Vin is less than Vdac, the comparator output is logic low and the MSB of the register is cleared to logic '0'. The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison. The sequence continues all the way down to the LSB. Once this is done, the conversion is complete, and the N-bit digital word is available in the register.
Figure 2.10 Block diagram of successive approximation architecture.
Figure 2.11 shows an example of a 4-bit conversion. The y-axis (and the bold line in the figure) represents the DAC output voltage. In the example, the first comparison shows that Vin < Vdac. Thus, bit 3 is set to '0'. The DAC is then set to 01002 and the second comparison is performed. As Vin > Vdac, bit 2 remains at '1'.
The DAC is then set to 01102, and the third comparison is performed. Bit 1 is set to '0', and the DAC is then set to 01012 for the final comparison. Finally, bit 0 remains at '1' because Vin > Vdac.
Figure 2.11 SAR operation (4 bits example).
SAR architectures are chosen frequently for medium-to-high-resolution applications, typically with sample rates fewer than 5 Ms/s. SAR ADCs most commonly range in resolution from 8 to 16 bits and provide low power consumption as well as a small form factor. This combination makes them ideal for a wide variety of applications, such as portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition.
2.3.4 Algorithmic (Cyclic) ADC
An algorithmic converter operates in much the same way as a SAR ADC.
However, whereas a SAR ADC halves the reference voltage in each cycle, a cyclic ADC doubles the error voltage while leaving the reference voltage unchanged.
Figure 2.12 shows the block diagram for an algorithmic converter [3]. This converter requires a small mount of analog circuitry because it repeatedly uses the same circuitry to perform its conversion cyclically in time. This architecture has difficulties in building an accurate multiply-by-two gain amplifier. Besides, if we use the switch-capacitance circuits, the capacitor ratio mismatch and clock feed-through must be carefully considered also. For the audio applications, it could reach low-power and low-voltage operation.
Figure 2.12 Block diagram of algorithmic converter.
2.3.5 Integrating (Dual Slope) ADC
The integrating converter architecture combines high resolution and excellent noise rejection, making it ideal for converting low-bandwidth analog signals [13].
Figure 2.13 shows the block diagram of an integrating ADC. It integrates the input
signal over a period of time so that fluctuations resulting from random noise contained in the signal are averaged together and thus largely eliminated. In its most basic form, the integrating ADC has two operational phases as shown in Figure 2.14.
During the integration phase, the signal is converted to a stored charge on a capacitor.
Once the integration period is completed, the reference phase begins. In this phase the capacitor is switched from the input signal to a fixed reference voltage which is opposite in sign to the input signal. The capacitor is discharged, and the time necessary to discharge the capacitor is measured. This time is directly related to the charge on the capacitor and is used to determine the binary output of the ADC.
The major disadvantage of integrating ADCs is that they are slow. Typical conversion rates are in the 1 to 10 samples per second range. For this reason integrating ADCs are typically used only in instruments where the signal level is expected to change rather slowly. This type of converters often include built-in drivers for LCD or LED displays and are found in many portable instrument applications, including digital panel meters and digital multi-meters.
Figure 2.13 Block diagram of an integrating ADC.
Figure 2.14 The operation of the integrating ADC.
2.3.6 Sigma-Delta (over-sampling) ADC
Sigma-delta converters, also called over-sampling converters, the basic concepts
Sigma-delta converters, also called over-sampling converters, the basic concepts