Simulation Results of Whole Chip

4.7.6 Simulation Results of Clock Generator

The clock generator creates two non-overlap clocks to perform the pipelined architecture. Figure 4.35 shows the two non-overlap clock clk1 and clk2, and clk1p has earlier falling edge of clk1 can reduce some error as described before.

Figure 4.35 Simulation results of the clock generator.

4.7.7 Simulation Results of Whole Chip

Figure 4.36-4.43 show the 1024-point FFT analysis of the pipelined ADC with different frequency of input signal, and the performance is listed on the figure. Figure 4.44 shows the SNDR versus frequency of input signal. Figure 4.45 shows ramp response of the pipelined ADC is used to calculate the DNL and INL. Figure 4.46 and Figure 4.47 show the linearity of the pipelined ADC. In order to minimize the simulation time, each codes of ADC is sampled 3 times to make sure both DNL and INL are under ¹

2LSB.

Figure 4.36 The output waveform of the pipelined ADC with an input frequency of 19.84375MHz.

Figure 4.37 The FFT analysis of the pipelined ADC with an input frequency of 19.84375MHz.

Figure 4.38 The output waveform of the pipelined ADC with an input frequency of 2.0703125MHz.

Figure 4.39 The FFT analysis of the pipelined ADC with an input frequency of 2.0703125MHz.

Figure 4.40 The output waveform of the pipelined ADC with an input frequency of 273.4375KHz.

Figure 4.41 The FFT analysis of the pipelined ADC with an input frequency of 273.4375KHz.

Figure 4.42 The output waveform of the pipelined ADC with an input frequency of 39.0625KHz.

Figure 4.43 The FFT analysis of the pipelined ADC with an input frequency of 39.0625Hz.

Figure 4.44 SNDR versus Input frequency.

Figure 4.45 Ramp response of the pipelined ADC.

Figure 4.46 DNL of the pipelined ADC.

Figure 4.47 INL of the pipelined ADC

Table 4.3 Summary of the pipelined ADC

Parameter Value

Power supply 3.3V

Architecture Pipelined ADC

Resolution 10-bit

Operation frequency 40MHz

Input swing (differential) ±1V

SNDR @ Nyquist-rate 61.1dB

Power dissipation ≈100mW

Technology TSMC 0.35-um 2P4M CMOS

process

Chapter 5 Conclusions

5.1 CONCLUSIONS

The operational amplifier is a very important part in the pipelined ADC, and limits the performance of ADC. Under the consideration of accuracy and speed, the new operational amplifier with positive feedback is proposed. With the simulation of the HSPICE, the new amplifier performs high gain and high speed, and is suitable for low power applications. The problems of stability are critical, when designing the positive feedback circuits. In our design, we minimize the positive feedback quantity to make sure the stability. The other parts of the pipelined ADC are carefully designed.

It reduces the power, area and reference voltage, and increases the speed and accuracy by using some techniques or idea. .

5.2 FUTURE WORK

In this research, there still exist many issues which limit performance of pipelined ADC. First, a better clock arrangement can reduce the area and power.

Second, the dynamic comparator should design careful, because it will induce the kick-back noise, although we reduce this affection by arranging clock and changing the output latch of comparator. However, this issue will be more critical in higher speed and resolution applications. Third, we should learn more about the proposed amplifier to achieve higher performance and reduce the non-ideal factor.

REFERENCES

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簡歷

VITA

姓 名：黃傑忠

學 歷：

新竹省立高級中學 (84 年 9 月~87 年 6 月)

國立中央大學電機工程學系 (87 年 9 月~91 年 6 月)

國立交通大學電子研究所碩士班 (92 年 9 月~94 年 6 月)

研究所修習課程：

類比積體電路I 吳介琮教授

類比積體電路II 吳重雨教授

數位積體電路 柯明道教授

積體電路設計實驗I 李鎮宜教授

積體電路設計實驗II 李鎮宜教授

積體電路之靜電放電防護設計特論 柯明道教授

低功率與高速積體電路設計 周世傑教授

計算機結構 黃俊達教授

永久地址：苗栗縣頭份鎮東庄里六鄰民族路380 號

Email： joeey.ee92g@nctu.edu.tw u3470618@cc.ncu.edu.tw m9211667@alab.ee.nctu.edu.tw