Chapter 2 Fundamentals of Pipelined Analog-to-Digital
2.4 S UMMARY
All advantages and disadvantages of ADC introduced above are summarized in Table 2.3. The target specification of 10-bit 40MSPS ADC is required. The high speed group includes flash, interpolating, folding and pipelined techniques are capable to reach the specification. However, the flash and interpolating architectures cost large percentage of passive components, so we don’t adopt them. Therefore, the Folding and pipelined are the most suitable architectures. From the view point of disadvantages, the pipelined architecture has large latency. In many applications, the large latency is not an issue. However, the large capacitance of the folding ADC may increase the loading of the front-end circuit, especially when time interleave technique is adopted. On the other hand, from the view point of advantages, error correction of the pipelined ADC is useful because the process variations may degrade the performance and it can correct the related errors. As discusses above, the pipelined
architecture is adopted.
Table 2.3 The comparisons of ADC architectures [16].
Architectures Advantages Disadvantages
SAR Medium resolution
Easy to implement S/H and DAC required Integrating
High input capacitance Large comparator
High input capacitance
Pipelined
Very high speed
Error corrections possible Low input capacitance
Large latency
Algorithmic
Error correction possible Low input capacitance Small area and power
Chapter 3
Architecture of Pipelined Analog-to-Digital Converter
3.1 OVERVIEW
In the previous chapter, several high speed architectures are introduced. We adopted pipelined architecture to realize a 10-bit 40MSPS ADC with many considerations. In this chapter, the focus will be the system structure and the operations of the pipelined architecture. The error sources of a switched capacitor (SC) pipeline stage and their effect on the ADC performance are compiled and the design constraints of the pipeline ADC presented
3.2 BASIC PIPELINED ARCHITECTURE
The block diagram of the pipelined ADC is introduced in section 2.3.8. The front-end sample-and-hold (S/H) block takes samples of its analog input signal and holds these samples in a memory element. The key feature of this circuit, when used as the front-end of an ADC, is that it relaxes the timing requirements of the latter.
This means that the precision and speed of the converter will be limited to a certain degree by the S/H circuit.
The operation of an S/H circuit is divided into two modes, sample and hold.
Usually this is done at uniform time intervals, set by a periodic clock that divides circuit operation into two phases. During the sample-mode the output of the circuit can either track the input or reset to some fixed value. In the hold-mode, the output of
the S/H circuit is equal to the input value obtained (sampled) at the end of the sample mode. Figures 3.1 (a) and (b) illustrate example waveforms for an S/H circuit and a T/H (track-and-hold) circuit. Although here a distinction was made between sampling and tracking, the majority of the circuits are referred to as S/H circuits even though they behave as T/H circuits.
Figure 3.1 (a) S/H circuit and (b) T/H circuit output waveforms.
The most basic form of an S/H circuit combines a switch and a capacitor, as shown in Figure 3.2. The operation of the circuit proceeds as follows. In sampling mode the switch is “on”, creating a signal path that allows the capacitor to track the input voltage. When the switch is “off” an open circuit is created that isolates the capacitor from the input, hence changing the circuit from sampling mode into holding mode.
Figure 3.2 Simple sample-and-hold circuit.
Figure 3.3 shows one stage of the pipelined architecture. Each stage comprises a low-resolution sub-analog-to-digital converter (sub-ADC) and an arithmetic unit called the multiplying digital-to-analog converter (MDAC) that performs a sample-and-hold (S/H) operation, coarse D/A conversion, subtraction, and amplification. In operation, each stage performs an A/D conversion of Bi effective bits with r-bit redundancy, converts the digital output back to analog and subtracts it from the sampled and held analog input. This residue is amplified with a gain of
2B i 1 r
G i = + − (3.1)
and fed to the next stage. The stages operate concurrently; that is, at any time, the first stage operates on the most recent sample while all other stages operate on residues from previous samples. Serial stages operate in opposite clock phases. The digital outputs of the stages 1B +r B.... k+ are delayed so that their values correspond to rk the same input sample.
Figure 3.3 Block diagram of one pipeline stage
The analog transfer function of a Bi+r-bit pipeline stage follows the equation
Vout,i = GiVin,i+DiVref (3.2)
where Di is an integer, the value of which is dependent on the output of the sub-ADC and with a step of 2 when r = 0 and 1 otherwise. The other terms Gi and Vin,i and the addition in Equation 3.2 are provided by the MDAC [17].
(
2 1 , (2)
1)Di∈ −⎡⎣ Bi− + Bi− ⎤⎦
3.2.1 Per-Stage Resolution
The pipelined ADC architecture allows a designer flexibility in the choice of sub-ADC resolution for each stage. As such, the most common implementation of the pipelined ADC is a 1.5 bits-per-stage structure. The reduction in stage resolution allows for very fast conversion times and small power consumptions. This is due to the relaxed requirement of the sub-ADC, and is most effective in designs for low-to-medium resolution.
The most other pipelined ADCs fall into a class of pipelines known as multi-bit pipeline ADCs. These are pipelines with greater than 1.5 bits-per-stage sub-ADC resolution, and are most useful in design situations requiring large overall ADC resolutions. The advantage of a multi-bit pipeline is the large gain at output of the first MDAC – noise power contributions of all following stages are reduced by the squared MDAC gain. High-resolution designs place stringent requirements on the ADC noise and the size and power consumption of the back-end stages can be decreased effectively with the large gain from a multi-bit stage. The aggressive scaling leaves more budgeted power and area available for the critical initial stages of the pipeline.
Therefore, the resolution of 1.5-bits-per-stage is adopted mainly for the following reasons [3] [17] [18] [19]:
1. The bandwidth of the SC circuit stage which limits the overall conversion rate can be maximized.
2. Because the code 11 is never occurred, the number of the required levels in the DAC is reduced by one. It makes sub-DAC faster and less sensitive to capacitor ratio error than conventional counterpart.
3. The design of error correction circuits and control logic is simpler, and the number of comparators in sub-ADC is minimized.
4. The smaller inter-stage gain, which equal to 2, makes faster settling, so the bandwidth can be maximized for high-speed operation.
5. The power consumption can be reduced for high speed operation.
3.2.2 Digital Error Correction
In order to illustrate the algorithm behind digital correction, a 2-bit pipeline stage is presented here as an example. Figure 3.4 shows the ideal transfer function of 2-bit pipeline stage whose block diagram is shown on the left. When the input crosses one of the sub-ADC decision levels, the digital output for the stage is increased by one bit, whereas the stage output decreases by 2 Vref’s. With the inter-stage gain of 4, the signal presented to the next stage is the full scale and does not allow any tolerance for errors in sub-ADC and sub-DAC.
Figure 3.4 Ideal transfer function of a 2-bit pipelined stage.
When an offset occurs in the sub-ADC or sub-DAC, the output of the first stage will exceed the range bounded by ±Vref as shown in Figure 3.5. This will saturate the second stage and cause missing information. To eliminate this problem, one can increase the range of the second stage sub-ADC or equivalently reduce the inter-stage gain of the first stage to tolerate sub-ADC error.
When the inter-stage gain is reduced to 2, the transfer function becomes Figure 3.6. This allows the sub-ADC error to be as large as 1
4Vref and the output is still in the input range of the following stage. However, when a sub-ADC error is present without digital correction, the error will appear in the final digital output.
In another words, if digital correction is not used, the first stage sub-ADC must still be as linear as the entire converter. Whereas the later stages, because of inter-stage gain, the requirements can be relaxed. Now, assume the first stage is ideal, with a full scale input to the first stage, the output is only between
1 2Vref
− and 1
2Vref , leaving an extra bit on top and bottom of the per-stage resolution. Digital correction simply utilizes the extra bit to correct the overranging section from the previous stage.
Figure 3.5 Transfer function with sub-ADC error (a) and sub-DAC error (b).
Figure 3.6 Transfer function of inter-stage gain of 2 and sub-ADC error.
For example, when one of the sub-ADC thresholds has an offset, the output of the first stage will exceeds 1
2Vref . The second stage, sensing the overranging, will increase the output by one LSB. This bit will cause the first stage output to increase by one LSB during the digital correction cycle. In the same way, when the output of the first stage drops below 1
2Vref
− , the second stage will sense the overranging and subtract one LSB during digital correction cycle. With this method, the sub-ADC error, as large as 1
4Vref , in the stage can be corrected by the following stage with digital correction.
With the above digital correction algorithm, both addition and subtraction need to be present in the digital correction circuit which complicates the code assignment for the pipeline stage. Subtraction can be eliminated by intentionally adding an
1 4Vref
− offset to the sub-ADC and the output of sub-DAC. A conceptual block diagram and transfer function is shown in Figure 3.7. With this configuration, the sub-ADC error, up to 1
4Vref , can be tolerated and digital correction circuit is modified to contain adders only.
Figure 3.7 Conceptual Block Diagram of Modified Pipeline Stage and Coding.
Since overranging in the transfer function can be detected by the next stage, one can simplify the design even more by eliminating a comparator at 3
4Vref . The final block diagram and transfer function is shown in Figure 3.8. The comparator thresholds (sub-ADC) are at 1
4Vref
− and 1
4Vref ; the sub-DAC levels are at 1
2Vref
− , 0 and 1
2Vref . The codes are shown on top of the transfer function and the overranging part on the transfer function will be digitally corrected by the next stage except the last stage of the pipeline. The 1.5-bit ADC and DAC here represent the effective bits per stage after digital correction [20] [21].
Figure 3.8 Conceptual Block Diagram of Modified Pipeline Stage and Coding.
3.3 ERROR SOURCE OF PIPELINED STAGE
Pipeline Analog-to-Digital data converters have many potential error sources – many of them are the same error sources found in other ADCs. There is, however, a fundamental difference in how the error sources appear in the final converted signal for pipelined ADCs. The segmented nature of the Pipeline ADC is very helpful in addressing power and speed concerns, but complicates understanding and reduction of error propagation from stage to stage. Simple errors in Pipeline ADCs produce non-linearities that are difficult to correct. Much effort has therefore been spent on understanding these errors [3] [17] [22] [23] and finding means of reducing them [24]
[25] [26].
3.3.1 Offset Error
Offset errors are simple additive errors that can be modeled as an error constant summed with the signal. Offset error in ADC can be compensated by the digital error correction generally. This is not only for pipelined ADCs but also the other architectures of ADC. Offsets that occurs mid-pipeline can create significant non-linearities; this necessitates special design techniques and careful design to reduce the amount of signal offset present in the pipeline. Common offset sources in pipelined ADCs are charge injection, comparator offsets, operational amplifier offset.
z Charge Injection
Charge injection is a general term for when circuit components that add inadvertent charge. The most common source of charge injection in switched-capacitor circuits is “orphaned” charge originating from the inversion layer when a MOSFET switch is turned off. Charge injection offset can be mitigated with careful design. There are also several “tricks” often used to reduce this offset
including early-clocking, dummy switches, and complimentary switches [3].
z Comparator Offset
The main error source of the sub-quantization in a pipeline stage is the offset voltage of the comparators. An offset voltage shifts the decision level of the comparator introducing a quantization error to the Bi+r-bit output the stage. The effect of the threshold level shifting on the transfer function of a 1.5-bit stage is present in Figure 3.9, where the non-zero comparator offset voltage are assumed to be the only non-idealities present.
Figure 3.9 Effect of the comparator offset on the transfer function of a 1.5-bit stage.
The comparator offset voltage is originated from several reasons. The main component is inherited from the device mismatch, the combined effect of which can be reduced into the comparator input. Deviation in the reference voltage levels
can be also included in the input referred offset voltage. If no redundancy is exploited, the error in the output voltage of each stage must be less then half of the LSB referred to the resolution of the remaining back-end pipelined ADC. The maximal error allowed in the output of the mth stage is given by
Vref +
1
where is the full scale output voltage. Referred to the stage input, the maximal allowed comparator input referred offset is given by
FS 2
When the digital error correction with one-bit redundancy is employed, the comparator offset requirement is described in section 3.2.2, the value of which is much larger than Equation 3.3 and furthermore, independent of the order of the stage.
z Operational Amplifier Offset
The operational amplifier offset voltage introduces a constant error of Vos, which is directly translated to an equal, constant shift of the output voltage Vout as depicted for a negative offset of a 1.5-bit stage in Figure 3.10. The shift can cause the stage output to overflow and saturate the remaining pipeline stages. The effect of this offset voltage can be minimized by using well known circuit techniques like auto-zeroing, i.e. connecting the amplifier in unity gain feedback during the sample phase, or measuring and compensating the offset analogically or digitally.
Figure 3.10 Effect of the amplifier offset on the transfer function of a 1.5-bit stage.
3.3.2 Gain Error
Gain error is a multiplicative error that acts on the input signal. It can be modeled as a gain stage where a gain of one is the optimal gain value. Like offset error, gain error on the system level is a fairly simple error to correct. Also, just like offset error within pipelined stages, gain errors can create difficult-to-remove non-linear errors.
The most common gain error sources are finite operational amplifier gain error and feedback capacitor to MDAC capacitor mismatch.
z Operational Amplifier Gain Error
The errors result from the finite operational amplifier open loop DC-gain error , which is given in this case by
A0 A0 =gm ro⋅ , and from the parasitic input
capacitance , which changes the feedback factor. Figure 3.11 shows the structure of the MDAC. For the general unit capacitor MDAC of Figure 3.11, omitting all non-linearities other than the finite open loop DC-gain , it can be written on the charge preservation in the sample and hold mode
Cp
where the is a constant multiplier equal to -1, 0 or +1 depending on the output of the sub-ADC, the parameter
The effect of the amplifier parasitic input capacitance on the feedback factor is also manifested in Equation 3.7. By comparing Equation 3.6 to the ideal transfer function
f s s
it can be observed that the error introduced by the amplifier finite open loop DC-gain is given the last term in Equation 3.6, for which, when
0
thus, the amplifier finite DC-gain decrease the gain and steps at the comparator thresholds in the transfer function by an error term ε of
0
1 ε = A f
⋅ (3.10)
The effect of the resulting signal-dependent gain error introduced to the transfer function of a 1.5-bit stage is depicted exaggeratedly by the solid line in Figure 3.12.
Figure 3.11 The structure of the MDAC
Figure 3.12 Effect of the finite amplifier DC-gain on the transfer function of a 1.5-bit stage.
z MDAC Capacitor Mismatch
In switched capacitor MDACs, mismatch of the sampling C and feedback s Cf capacitors is the major error source. Each of the capacitor can be modeled to consist of an ideal part C and s Cf plus a mismatch +Cs and +Cf , respectively, corresponding to the Figure 3.13.
Figure 3.13 The structure of the MDAC with the capacitor mismatch.
Including the capacitor mismatch in the transfer function of a switched capacitor MDAC in Equation 3.8, results in
( )
The multiplier of the input Vin represents a gain error, while the multiplier of the second term introduces an error in the height of the voltage steps at the comparator threshold levels. For the unit capacitor MDAC, by exploiting the property
, Equation 3.11 can be written as
where for the unit capacitor mismatch α holds 1
The effect of the capacitor mismatch on the stage transfer function is depicted in Figure 3.14. For a 1.5-bit stage, it is noticed that when Vin = ±Vref, there are no errors result. The gain error and the deviation of the voltage steps at the comparator threshold levels are clearly visible from the figure.
Figure 3.14 Effect of the capacitor mismatch on the transfer function of a 1.5-bit stage.
z Other Gain Error
The other gain error source not usually a concern for pipelined ADCs is reference mismatch from stage and stage. Generally the voltage is a very-low impedance signal that is sent to each stage of the pipeline. The reference mismatch is almost negligible.
3.3.3 Slew Rate and Gain Bandwidth Error
A more severe dynamic error in the stage transfer function is caused by the incomplete settling of the operational amplifier output. This error is introduced by the finite slew rate (SR) and gain bandwidth of the operational amplifier. At the beginning of the hold mode, the operational amplifier enters slewing, providing its maximal output current Imax, after which it settles exponentially towards the ideal stage output voltage, the settling now being limited by the amplifier transconductance gm and the effective load capacitance in this mode CL H, . For the slew rate limited part of the settling, it is a good practice to reserve one third of the total settling time of T=2, where T is the sample clock period, relating to the sample frequency by fs 1
=T . The load capacitance, which has to be charged or discharged during the settling, depends on the capacitor charging in the previous sample phase. In the worst case, the total load capacitance during the slewing is CL total, +Cf , resulting
max
where CL total, + Cf is the total load capacitance including the parasitic capacitance at the amplifier output . The stage output voltage is linearly dependent on the slew
where CL total, + Cf is the total load capacitance including the parasitic capacitance at the amplifier output . The stage output voltage is linearly dependent on the slew