Chapter 3 Architecture of Pipelined Analog-to-Digital
3.3 E RROR S OURCE OF P IPELINED S TAGE
3.3.6 Sampling Clock Jitter
Especially in high-resolution pipeline A/D converters, the total kT/C-noise contribution of all the MDACs of a pipeline ADC determine the minimum size of the capacitors and full-scale voltage which does not degrade the SNR below the quantization noise level..
The noise of the operational amplifiers of the SC MDACs must also be taken into account in the design. The thermal noise of an amplifier is dependent on the circuit topology and can be considered separately superimposed on the kT/C-noise.
3.3.6 Sampling Clock Jitter
The most critical clocking signal in the S/H is the sampling clock, the falling edge of which determines the sampling moment. Random variations of the falling
edge, referred as clock jitter or aperture uncertainty σa, are unavoidable. Because of its random nature, the sampling clock jitter does not introduce any fixed pattern tones in the output spectrum but degrades the signal-to-noise ratio.
Figure 3.16 shows the example of the aperture uncertainty error. The effect of the aperture uncertainty comes about because an ADC does not sample the input at precisely equal time-intervals 1
Ts
= fs. The sampling process is random-like and can be characterized by a mean and standard deviation with regard to the location in time of when sampling occurs. The mean is the average position of the sampling instant and the standard deviation is defined as the rms aperture jitter σa. The worst-case voltage error due to the aperture jitter corresponds to sampling a sinusoidal waveform with the Nyquist-rate frequency, which is fs/ 2, i.e. a full-scale signal
( )
( ) sin 2
2 VFS
v t = π⋅ ⋅ fs t (3.23)
The maximum error will occur when attempting to sample the signal v(t) at its zero-crossing, where its derivative gives the maximum slope of the signal
(0)
FS
dv fs V
dt = ⋅ ⋅π (3.24)
The maximum rms voltage error is given by the product of Equation 3.24 and the aperture uncertainty.
rms FS a
v = ⋅ ⋅π fs V ⋅σ (3.25)
which corresponds to an output noise power of
2 2 2 2
which adds to the quantization noise and degrades the SNR.
Figure 3.16 Example of the aperture uncertainty error.
In the back-end pipeline stages, which have an almost constant exponentially settling output of the previous stage as their input, the sampling clock jitter is of much less importance than in the first stage. The time varying output of a pipeline stage is given by Equations 3.16-3.19, the derivative of which is given by
,
Rms voltage error at the sampling moment of stage i, which is at the end of the hold phase of stage i-1, i.e. 1
The corresponding noise power being
,
The noise contribution of Equation 3.29 is usually much below that of Equation 3.26.
Chapter 4
Circuits Design
4.1 OVERVIEW
The Analog-to-Digital converter designed here is a 10-bit 40MS/s pipelined ADC. The entire analog and digital circuits are designed for 3.3V power supply. The full scale input voltage is from -1V to 1V. And all analog circuits are fully differential;
include the switches, sample-and-hold, operational amplifier, MDAC, flash type quantizer, and comparators. The digital circuits contain the clock generator, digital error correction. In this chapter, all the circuits will be discussed in detail.
4.2 INPUT STAGE SAMPLE-AND-HOLD
The conversion process of a pipelined ADC begins at the S/H circuit. Figure 4.1 shows the unity-gain S/H circuit used for this work. The analog signal is applied to the terminals Vin+ and Vin- and the held output is taken at the terminals Vout+ and Vout- . The signal ground COM is the common-mode voltage of the output differential signal. Because the architecture of the operational amplifier is a telescopic amplifier, which has a lower input DC level, the node COMI is for input common-mode voltage. It is different from the output common-mode voltage COM Although the charge stored in the capacitor from different path are not the sane quantity, the input and output voltage signals are not affected apparent.
Figure 4.1 The sample-and-hold (S/H) circuit
There are four related clock phase in sample-and-hold as shown in Figure 4.2.
The clk1, clk1p are used during the sample phase and clk2 are used during the hold phase. The clk1 and clk2 are non-overlap phases to prevent the charge loss on the path when both the clk1 and clk2 are closed. The clk1p has the same rising edge to the clk1 phase, but earlier falling edge takes the advantage of reducing the charge injection from the sampling switch. There is a switch connects Vout+ and Vout- during the sampling phase, and then the output node of the operational amplifier can keep the voltage at output common-mode and prevent saturation. That reduces the settling time when a non-saturated voltage needs to go back to the target voltage at hold phase [16].
Figure 4.2 Timing diagram of the Sample-and-hold
4.2.1 Capacitors
The size of capacitors played an important role in design of the pipelined ADC.
However, because of the architecture of S/H which we adopted, the major problem of capacitor mismatch is removed. The operational amplifier in Figure 4.1, can be simplified as an infinite input impedance and the output has finite gain gm ro⋅ . The operational amplifier’s input differential pair is usually large sized to reach higher gm. Hence the parasitic capacitance Cp, from the node to ground, is too large to be ignored. A larger sampling capacitor Cs can get small time constant because it is the feedback factor. If the size too small, the clock feed-through and charge-sharing effect will be worse. In this design, the Cs which used for the S/H is 2pF.
4.2.2 Switches
The sample-and-hold circuit which operates in the sample mode is shown in Figure 4.3. The Ron is independent of the input voltage Vin if we choose the bootstrap switches. It enhances the SNR and the linearity of the pipelined ADC. The voltage in the input of the operational amplifier almost does not change when the switches S1 turns on. So using the NMOS transistor only will be suitable [27].
Figure 4.3 Sample-and-hold in sample mode
Figure 4.4 shows the circuit detail of the bootstrap block. It operates on a signal phase clock φ that turn the switch M10 on and off. During the off phase φ is low, device M6 and M9 discharge the gate of M10 to ground. At the same time, Vdd is applied across capacitor C3 by M3 and M11. This capacitor will act as the battery across the gate and source during the on phase. M7 and M8 isolate the switch from C3 while it is charging. When φ goes high, M5 pulls down the gate of M7, allowing charge from the battery capacitor C3 to flow onto the gate G. This turns on both M8 and M10. M8 enables the gate G to track the input voltage S shifted by Vdd. Keeping the gate-source voltage constant regardless of the input signal. For example, if source S is at Vdd, the gate G is 2Vdd, however Vgs=Vdd. Because the body (nwell) of M7 is tied to its source, the latch-up is suppressed.
M1, M2, C1, and C2 from a clock multiplier that enables M3 to unidirectional charge C3 during the offset phase. This entire circuit was carefully designed such that no device experiences a relative terminal voltage greater than Vdd. This circuit is similar to a low distortion sampling switch which provides a constant Vgs across the switching device.
Figure 4.4 Bootstrapped switch circuit
Design guideline: C3 must be sufficiently large to supply charge to the gate of the switching device in addition to all parasitic capacitance in the charging path.
Otherwise, charge-sharing will significantly reduced the boosted voltage according to the equation as follows:
where is the total parasitic capacitance connected to the top plate of while it is across the main switching device M10. Figure 4.5 shows the conceptual output waveform of the bootstrap circuit [19].
Cp C3
Figure 4.5 Conceptual output waveform of the bootstrap circuit.
4.3 MULTIPLYING DAC
Figure 4.6 shows the differential schematic diagram of the MDAC. The differential held analog input is applied to terminals Vin+ and Vin-, and the held output is taken at terminal Vout+ and Vout-. The MDAC operation and timing are almost the same as S/H. The control switches which are connected with the bottom
plates of Cs+ and Cs-, are used to control the transferred quantity as the function of a subtractor. The control signals a, b and c depending on the state of digital output of the sub-DAC.
Figure 4.6 Schematic diagram of fully differential MDAC.
4.3.1 Capacitor
Unlike the S/H, the capacitor mismatch of MDAC is very critical. With the discussion in the section 3.3.2 and section 4.2.1, we can determine the minimum capacitors in the design of MDAC. The 1pF capacitor is adopted for this MDAC to meet our specification of 10-bit 40MS/s ADC.
4.3.2 Switches
As the mentioned in the section 4.2.2, the voltage in the input of the operational amplifier in sample phase and the voltage in the bottom plates of Cs+ and Cs- are almost not changed when these switches turns on. So using the NMOS or PMOS transistor only will be suitable.
The other switches are the complementary switches to enhance the linearity of MDAC. Figure 4.7 (a) shows the complementary switch in our design, and Figure 4.7
(b) shows the model of the switch.
Figure 4.7 (a) The complementary switch, (b) simplify model of switch.
We can observe that the current flowing through the MOS transistors depends on the input voltage level of Vin. In the case of the NMOS, if the turn on voltage of the gate is Vdd and the source-drain voltage is much smaller than , then the transistor must operates in triode region and the flowing current is
Vdd V− th
Then, the turn-on resistance of NMOS is given by
( )
Then the total on-resistance is
( )
, , ,
1
on total on NMOS on PMOS
n ox DD THN n ox p ox in p ox THP enhances the SNR and the linearity of the pipelined ADC. Because the mobility
, MDAC with all the switches which are adopted.
Figure 4.8 A fully differential MDAC with adopted switches
4.4 OPERATIONAL AMPLIFIER
4.4.1 Gain Requirement
The DC open-loop gain of the operational amplifier limits the ADC’s resolution.
Figure 4.9 shows the operation of the S/H circuit in both sample phase and hold phase.
It acts like the MDAC as shown in Figure 4.10 which is discussed in section 3.3.2.
Then we have constitutes the input of following 9 stages. The maximum tolerable DNL is 0.5LSB at
10 bit level for the following 9 stages, the
9
The operational amplifier gain requirement for the MDAC is discussed in section
3.3.2. The error is
and the Vout constitutes the input of following 8 stages, the
8 open-loop gain for the first stage of MDAC is 61.03 dB
Figure 4.9 Operation of the S/H circuit in (a) sample phase and (b) hold phase.
Figure 4.10 Operation of the MDAC circuit in (a) sample phase and (b) hold phase.
4.4.2 Bandwidth Requirement
The successive pipeline stages operate in opposite clock phases, which gives a settling time of a half of the clock cycle (T/2). The settling time is determined first by the slew-rate (SR) and finally by the gain bandwidth (GBW) of the amplifier, as indicated in Figure 4.11.
Figure 4.11 Settling of the stage output
The half cycle of the sampling time for 40MHz is 12.5ns. However, the rising time (Tr), falling time (Tf) and non-overlap time must be taken into consideration.
And the half cycle (T/2) is approximately 11ns. Briefly we can assume the time ratio of two parts to be about 1:2. That would be 3ns:8ns in our timing arrangement.
During the SR limited transient response period, the critical case will be full range swing in 3ns. We can calculate the requirement of SR as
0.5
167 / 3
SR V V us
= ns ≈ (4.9)
The most commonly used operational amplifier can be modeled with a single-pole small-signal model of Figure 4.12.
Figure 4.12 Small-signal model of MDAC in the hold phase.
The gain bandwidth frequency of the operational amplifier is related to the transconductance gm by equation
2
L total,gain bandwidth gm
π C
= ⋅
(4.10)where the total load capacitance CL total, =CL+Cout includes the parasitic output capacitance Cout. Using the symbol of Figure 4.15, the transfer function is
the corner frequency is given by 3
The error ετ caused by the incomplete exponential settling during the time of gain bandwidth limited phase ( ), is given by Tb
In order to fulfill the resolution requirement, the settling error must be less than 0.5LSB, this case reduced to the input of the stage i, which results in a condition
1 2Ni
ετ < (4.14)
where Ni is the resolution of the remaining back-end pipeline including the ith stage.
For S/H the Ni is 10, and for the first MDAC stage the Ni is 9. By combining Equation 4.13 and Equation 4.14, and solving the amplifier transconductance gm
yields
On the other hand, the transconductance is related to the width W, length L, and drain current I of the transistor by D
m 2 ox W
g C D
μ⋅ ⋅ L ⋅I (4.16)
=
where μ is the mobility and the gate oxide capacitance. By substituting Equation 4.15 into Equation 4.16, a condition for the minimum drain current of one transistor of the amplifier input differential pair
Cox
Using Equation 4.10, this can be expressed in terms of the minimal gain bandwidth
Table 4.1 shows the gain and bandwidth requirement of operational amplifier in S/H and the first MDAC stage for the design of 10-bit 40MS/s pipelined ADC. It is assumed that CL total, 3pF, Cs =Cf = Cp (in S/H, C is zero ) and s Tb = s8n .
Table 4.1 The requirements of operational amplifier in S/H and MDAC
Parameter S/H MDAC of the first stage
DC open-loop gain 61.79dB 61.03dB
Unity gain bandwidth 193MHz 359MHz
Slew-rate 167V/us 167V/us
4.4.3 Telescopic Operational Amplifier
The simplest approach for a high-gain operational amplifier is the one-stage telescopic amplifier of Figure 4.13. All transistors in Figure 4.13 are biased in saturation region, PMOS transistors M5, M6, M7, M8 can be considered as current source, NMOS transistors M3, M4 are connected as common-gate form, NMOS transistors M1, M2 are the differential input of the operational amplifier, and M9 is the tail current source. The transistors from Mb1 to Mb16 are the bias circuits of this operational amplifier.
Typically, when using fully-differential operational amplifier in a feedback application, the applied feedback determined the differential signal voltage, but does not affect the common-mode voltages. It is necessary to add additional circuitry to determine the output common-mode voltage and to control it to be equal to some specified voltage. This circuitry, referred to as the common-mode feedback (CMFB) circuitry, is often the most difficult part of the operational amplifier design.
Figure 4.13 Telescopic operational amplifier with bias circuits.
Figure 4.14 Continuous-time CMFB of the telescopic operational amplifier.
Figure 4.14 shows the CMFB in our design. Since the two pairs have the same differential voltages being applied, the current in Mc1 will be equal to the current in Mc3, while the current in Mc2 will be equal to the current in Mc4. As long as the voltage Vo+ is equal to the negative value of Vo-, the current through diode-connected Mc5 will not change even when large differential signal voltages are present. When common-mode voltage of the output is changes (assume a positive common-mode voltage is present), will cause the current in both Mc2 and Mc3 to increase, which causes the current in diode-connected Mc5 to increase, which in turn causes its voltage to increase. This voltage is the bias voltage that sets the current levels in the n-channel current sources at the output of the operational amplifier [3].
The telescopic architecture was chosen rather than folded-cascode architecture, the major reason is the consideration of bandwidth. The biggest disadvantage of this architecture is its low maximum differential output swing. If we want to get higher swing, the DC open-loop gain will be decreased. There are many techniques to solve this problem, and gain-boosting technique is a good choice. However, for fully differential applications, the CMFB are required. Gain-boosting architecture needs one or two additional amplifiers to enhance its gain and output resistance, each of them need CMFB also. If the switch-capacitor CMFB is adopt, the die size will increase and the performance of the circuit will be limited.
Here, we proposed a new technique to enhance the gain of the telescopic architecture as shown in Figure 4.15. The transistors from Mp1 to Mp7 perform the positive feedback operation. In order to guarantee the stability of the operational amplifier, the size of positive feedback circuits is ten times smaller than the original telescopic operational amplifier, and the positive feedback quantity can not be too large.
Although the increase of gm is not obviously, because of the low positive feedback,
the M5, M6, M7, M8 still perform a negative output resistance. Therefore, the gain is enhanced. The operational amplifier we proposed has many advantages. At first, the DC open-loop gain is boosted without using many transistors like gain-booting architecture. Second, the output Vol+ and Vol- are the voltage level shift of Vo+ and Vo- can be used to the CMFB, it will decrease the output capacitance. Finally, the operational amplifier works when the lower Vdd is applied, without sacrificing the output swing and the speed.
Figure 4.15 Telescopic operational amplifier with the positive feedback circuits.
4.5 COMPARATOR
Figure 4.16 shows the circuit topology of a dynamic latch comparator. A latch with resistive comparing circuits in series with its NMOS is used to give low power during the regeneration mode. However, there is no PMOS precharging circuit and an NMOS pass transistor M12 for output charge sharing is used to equalize the two output voltages to approximately Vdd/2 during the reset mode. This is possible because the latch is totally disconnected from both Vdd and ground by M1, M10 and M11 when clk1p is high and clk1pb is low. Therefore a significant half power reduction, as compared to the precharging approach, is achieved. Note also that at the start of the regeneration mode (comparing mode), the latch is already active since both outputs are at Vdd/2. Hence the comparing speed tends to be fast. However, the comparing speed depends additionally on the different magnitude of the inputs and the amplifying loop gain within the latch. Hence the speed can be increased by enlarging the widths of M2-M5.
The comparator offset comes from the input transistor mismatch, M6-M9 as shown in Equation 4.19, of threshold voltage. In this equation the subscript A, B relate with M6-M7 and M8-M9 pairs respectively. However, the offset error may be increased from Equation 4.19 by unequal loading at its output nodes. Furthermore, the output should not drive a static gate directly since its level during the reset interval is neither high nor low.
Thus, an output latch circuit should be used to buffer with the load and convert into static outputs. When clk2 is low and clk2b is high. Ma2, Ma3, Ma6 and Ma7 are off to disable the effect of output of the dynamic comparator. Vout+ and Vout- are
Vt
+
therefore latched at their previous states. When clk2 is low and clk2b is high. Ma2, Ma3, Ma6 and Ma7 are on to enable transferring the comparator outputs to the output latch. The clk2 and clk1p is the same as the timing of S/H and MDAC. The size of
therefore latched at their previous states. When clk2 is low and clk2b is high. Ma2, Ma3, Ma6 and Ma7 are on to enable transferring the comparator outputs to the output latch. The clk2 and clk1p is the same as the timing of S/H and MDAC. The size of