Input Capacitance

Input capacitance is the capacitive load presented by the ADC to the circuit driving it. The input capacitance of an ADC is an important parameter because the input capacitance can load the circuit driving the ADC and degrade its performance.

2.2.10 Input Signal Swing

The input signal swing indicates the maximum and minimum values that the input signal may have without driving the ADC out of range or resulting in an unacceptable level of distortion.

2.2.11 Power Dissipation

Power dissipation is becoming an important ADC specification because many ADCs are being implemented in portable systems powered by a battery with limited energy. Reducing power dissipation can reduce system weight or improve battery life.

Reducing power dissipation can also make it easier to keep the temperature of the ADC at a reasonable level.

2.3 ARCHITECTURES OF ADC

2.3.1 Flash ADC Flash ADCs, also known as parallel ADCs, are the standard approach for

realizing very-high-speed converters. Figure 2.8 shows a block diagram of an N-bit flash ADC. It consists of 2ⁿ-1 comparators, are used to directly measure an analog signal to a resolution of n bits. The flash architecture has the advantage of being very fast, because the conversion occurs in a single ADC cycle. The disadvantage of this approach is that it requires a large number of comparators that are carefully matched and properly biased to ensure that the results are linear. Since the number of comparators needed for an N-bit resolution ADC is equal to 2ⁿ-1, limits of physical integration and input loading keep the maximum resolution fairly low. For example, a 4-bit ADC requires 15 comparators, an 8-bit ADC requires 255 comparators, and a 10-bit ADC would require 1023 comparators.

The flash ADCs are suitable for applications requiring very large bandwidths.

However, flash converters consume a lot of power, have relatively low resolution, and can be quite expensive. This limits them to high frequency applications that typically cannot be addressed any other way. Examples include data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives [3] [9] [10].

Figure 2.8 Block diagram of an N-bit flash ADC.

2.3.2 Sub-ranging ADC

In the field of high speed ADCs, the flash ADCs remain dominant due to their one-clock-cycle conversion; however, they suffer from large power consumption and area usage due to their 2^N comparators. For applications such as imaging, video and digital communication, where high resolution is required, the sub-ranging structures, first introduced by Dingwall and Zazzu [11], have gradually begun to replace the flash

ADC. Sub-ranging ADC uses fewer comparators than parallel flash ADCs. Instead of using one comparator per LSB like a flash converter does, a sub-ranging ADC uses fewer comparators, draws less power, has lower input capacitance, and can attain higher resolutions. Although not as fast as a parallel ADC, sub-ranging ADCs can digitize at speeds greater than 100 Ms/s at 8-bit resolution [12]. They can resolve signals to 16 bits at slower speeds. Figure 2.9 shows a block diagram of a 10-bit sub-ranging ADC that uses two 5-bit stages to digitize the analog input signal. The first ADC converts the upper 5 bits while the second stage converts the lower 5 bits.

This design uses 62 comparators (31 for each ADC) rather than the 1023 comparators required by a 10-bit flash converter. Sub-ranging ADCs often find use in RF test equipment, lower-speed digitizing oscilloscopes, and high-end PC plug-in digitizer cards and PC-external data-acquisition systems.

Figure 2.9 Conventional block diagram of a 10-bit sub-ranging ADC.

2.3.3 Successive Approximation ADC

The successive-approximation architecture can be thought of as the other end of the spectrum from the flash architecture. While a flash converter uses many comparators to converter in a single cycle; a successive-approximation-register (SAR) converter conceptually uses a single comparator to converter in many cycles. To understand the basic operation of SAR ADC, knowledge of the search algorithm referred to as a “binary search” is helpful [3]. Figure 2.10 shows block diagram of a SAR ADC. To implement the binary search algorithm, the N-bit register is first set to midscale (that is, 100... .00, where the MSB is set to '1'). This forces the DAC output (Vdac) to be Vref/2, where Vref is the reference voltage provided to the ADC. A comparison is then performed to determine if Vin is less than or greater than Vdac. If Vin is greater than Vdac, the comparator output is logic high or '1' and the MSB of the N-bit register remains at '1'. Conversely, if Vin is less than Vdac, the comparator output is logic low and the MSB of the register is cleared to logic '0'. The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison. The sequence continues all the way down to the LSB. Once this is done, the conversion is complete, and the N-bit digital word is available in the register.

Figure 2.10 Block diagram of successive approximation architecture.

Figure 2.11 shows an example of a 4-bit conversion. The y-axis (and the bold line in the figure) represents the DAC output voltage. In the example, the first comparison shows that Vin < Vdac. Thus, bit 3 is set to '0'. The DAC is then set to 01002 and the second comparison is performed. As Vin > Vdac, bit 2 remains at '1'.

The DAC is then set to 01102, and the third comparison is performed. Bit 1 is set to '0', and the DAC is then set to 01012 for the final comparison. Finally, bit 0 remains at '1' because Vin > Vdac.

Figure 2.11 SAR operation (4 bits example).

SAR architectures are chosen frequently for medium-to-high-resolution applications, typically with sample rates fewer than 5 Ms/s. SAR ADCs most commonly range in resolution from 8 to 16 bits and provide low power consumption as well as a small form factor. This combination makes them ideal for a wide variety of applications, such as portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition.

2.3.4 Algorithmic (Cyclic) ADC

An algorithmic converter operates in much the same way as a SAR ADC.

However, whereas a SAR ADC halves the reference voltage in each cycle, a cyclic ADC doubles the error voltage while leaving the reference voltage unchanged.

Figure 2.12 shows the block diagram for an algorithmic converter [3]. This converter requires a small mount of analog circuitry because it repeatedly uses the same circuitry to perform its conversion cyclically in time. This architecture has difficulties in building an accurate multiply-by-two gain amplifier. Besides, if we use the switch-capacitance circuits, the capacitor ratio mismatch and clock feed-through must be carefully considered also. For the audio applications, it could reach low-power and low-voltage operation.

Figure 2.12 Block diagram of algorithmic converter.

2.3.5 Integrating (Dual Slope) ADC

The integrating converter architecture combines high resolution and excellent noise rejection, making it ideal for converting low-bandwidth analog signals [13].

Figure 2.13 shows the block diagram of an integrating ADC. It integrates the input

signal over a period of time so that fluctuations resulting from random noise contained in the signal are averaged together and thus largely eliminated. In its most basic form, the integrating ADC has two operational phases as shown in Figure 2.14.

During the integration phase, the signal is converted to a stored charge on a capacitor.

Once the integration period is completed, the reference phase begins. In this phase the capacitor is switched from the input signal to a fixed reference voltage which is opposite in sign to the input signal. The capacitor is discharged, and the time necessary to discharge the capacitor is measured. This time is directly related to the charge on the capacitor and is used to determine the binary output of the ADC.

The major disadvantage of integrating ADCs is that they are slow. Typical conversion rates are in the 1 to 10 samples per second range. For this reason integrating ADCs are typically used only in instruments where the signal level is expected to change rather slowly. This type of converters often include built-in drivers for LCD or LED displays and are found in many portable instrument applications, including digital panel meters and digital multi-meters.

Figure 2.13 Block diagram of an integrating ADC.

Figure 2.14 The operation of the integrating ADC.

2.3.6 Sigma-Delta (over-sampling) ADC

Sigma-delta converters, also called over-sampling converters, the basic concepts behind the sigma-delta ADC architecture originated at Bell Labs in the 1950s—in work done on experimental digital transmission systems utilizing delta modulation and differential PCM. By the end of the 1960s, the sigma-delta architecture was well understood. However, because digital filters (then a rarity) were an integral part of the architecture, practical IC implementations did not appear until the late 1980s, when signal processing in digital CMOS became widely available [14].

Figure 2.15 shows the sigma-delta ADC consists of 2 major blocks: modulator and digital filter. The modulator, whose architecture is similar to that of a dual-slope ADC, includes an integrator and a comparator with a feedback loop that contains a 1-bit DAC. The modulator oversamples the input signal, transforming it to a serial bit stream with a frequency well above the required sampling rate. The output filter then converts the bit stream to a sequence of parallel digital words at the sampling rate.

Sigma-delta ADCs are used predominately in lower speed applications requiring a trade off of speed for resolution by over sampling, followed by filtering to reduce noise. 24-bit sigma-delta ADCs common used in Audio designs, instrumentation and

Sonar. Bandwidths are typically less than 1MHz with a range of 12 to 18 true bits.

Figure 2.15 Block diagram of first-order sigma-delta ADC.

2.3.7 Folding and Interpolating ADC

Since the flash ADC uses many comparators costs a lot of power and area. It makes flash ADC not adequate for high resolution applications. In order to reduce the large number of comparators, the difference between analog input and each reference voltage can be quantized at the output of each comparator. This is possible because of the finite gain and nonzero linear input range of comparators in front of latches.

Figure 2.16 shows example of a 4-bit interpolating ADC.

Figure 2.16 Example of a 4-bit interpolating ADC.

The number of input amplifier can be reduced by using the interpolating architecture. However, the number of latch comparators remains at for an N-bit converter. This large number of the latch comparators can be reduced by using folding architectures.

2^N

The folding architecture is similar in operation to a sub-ranging converter in that a group of LSBs are found separately from a group of MSBs. Whereas the sub-ranging converter requires an accurate DAC, a folding converter determines the LSB set more directly through the use of analog preprocessing while the MSB set is determined at the same time. Figure 2.17 shows example of a 4-bit interpolating ADC.

Figure 2.17 Example of a 4-bit folding ADC.

While the folding approach reduces the number of latch comparators, a large input capacitance similar to that for a flash converter is also present with the folding circuit shown. To reduce this large input capacitance, folding converters also make use of an interpolating architecture as shown in figure 2.18 [3].

Figure 2.18 Example of a 4-bit folding ADC with an interpolating architecture.

2.3.8 Pipelined ADC

The pipeline ADC is the extension of the two-step structure. The conversion is divided into several stages with each stage generating a certain number of digital bits.

The general block diagram is shown in Figure 2.19. There are M stages and the ith stage generates Ni digits. If no redundancy is used, the sum of Ni equals to m, the resolution of ADC. All stages operate concurrently. When a stage works on the current sample, the next stage processes the previous one. The nature of concurrence makes the throughput of the converter independent of its resolution, and the same as for a flash ADC. The hardware increases linearly with the increase of resolution, compared to the flash structure. The disadvantage of this structure is the large latency time between valid digital output and the analog input signal. In some applications, such as data recovery in the Local Area Network (LAN) and disk drive read/write channels, the ADC is inside a feedback loop. Excessive latency will make the loop unstable. For most video applications, latency is not an issue [3] [15].

Figure 2.19 Block diagram of an m-bit pipelined ADC

The pipelined ADC has become the most popular ADC architecture for sampling rates from a few megasamples per second (MS/s) up to 100MS/s+, with resolutions from 8 to 16 bits. They offer the resolution and sampling rate to cover a wide range of applications, including CCD imaging, ultrasonic medical imaging, digital receiver, base station, digital video (for example, HDTV), xDSL, cable modem, and fast Ethernet.

2.3.9 Time-interleaved ADC

Very-high-speed ADC conversions can be realized by operating many ADC in parallel. The system architecture for a four-channel ADC is shown in Figure 2.20.

Here, φ₀ is a clock at four times the rate of φ₁ to φ₄. Additionally, φ₁ to φ₄ are delayed with respect to each other by the period of φ₀, such that each converter will get successive samples of the input signal, Vin, sampled at the rate of φ₀. In this way, the four ADC operate at one-quarter the rate of the input sampling frequency [3].

Figure 2.20 A four-channel time-interleaved ADC

2.4 SUMMARY

All advantages and disadvantages of ADC introduced above are summarized in Table 2.3. The target specification of 10-bit 40MSPS ADC is required. The high speed group includes flash, interpolating, folding and pipelined techniques are capable to reach the specification. However, the flash and interpolating architectures cost large percentage of passive components, so we don’t adopt them. Therefore, the Folding and pipelined are the most suitable architectures. From the view point of disadvantages, the pipelined architecture has large latency. In many applications, the large latency is not an issue. However, the large capacitance of the folding ADC may increase the loading of the front-end circuit, especially when time interleave technique is adopted. On the other hand, from the view point of advantages, error correction of the pipelined ADC is useful because the process variations may degrade the performance and it can correct the related errors. As discusses above, the pipelined

architecture is adopted.

Table 2.3 The comparisons of ADC architectures [16].

Architectures Advantages Disadvantages

SAR Medium resolution

Easy to implement S/H and DAC required Integrating

High input capacitance Large comparator

High input capacitance

Pipelined

Very high speed

Error corrections possible Low input capacitance

Large latency

Algorithmic

Error correction possible Low input capacitance Small area and power

Chapter 3

Architecture of Pipelined Analog-to-Digital Converter

3.1 OVERVIEW

In the previous chapter, several high speed architectures are introduced. We adopted pipelined architecture to realize a 10-bit 40MSPS ADC with many considerations. In this chapter, the focus will be the system structure and the operations of the pipelined architecture. The error sources of a switched capacitor (SC) pipeline stage and their effect on the ADC performance are compiled and the design constraints of the pipeline ADC presented

3.2 BASIC PIPELINED ARCHITECTURE

The block diagram of the pipelined ADC is introduced in section 2.3.8. The front-end sample-and-hold (S/H) block takes samples of its analog input signal and holds these samples in a memory element. The key feature of this circuit, when used as the front-end of an ADC, is that it relaxes the timing requirements of the latter.

This means that the precision and speed of the converter will be limited to a certain degree by the S/H circuit.

The operation of an S/H circuit is divided into two modes, sample and hold.

Usually this is done at uniform time intervals, set by a periodic clock that divides circuit operation into two phases. During the sample-mode the output of the circuit can either track the input or reset to some fixed value. In the hold-mode, the output of

the S/H circuit is equal to the input value obtained (sampled) at the end of the sample mode. Figures 3.1 (a) and (b) illustrate example waveforms for an S/H circuit and a T/H (track-and-hold) circuit. Although here a distinction was made between sampling and tracking, the majority of the circuits are referred to as S/H circuits even though they behave as T/H circuits.

Figure 3.1 (a) S/H circuit and (b) T/H circuit output waveforms.

The most basic form of an S/H circuit combines a switch and a capacitor, as shown in Figure 3.2. The operation of the circuit proceeds as follows. In sampling mode the switch is “on”, creating a signal path that allows the capacitor to track the input voltage. When the switch is “off” an open circuit is created that isolates the capacitor from the input, hence changing the circuit from sampling mode into holding mode.

Figure 3.2 Simple sample-and-hold circuit.

Figure 3.3 shows one stage of the pipelined architecture. Each stage comprises a low-resolution sub-analog-to-digital converter (sub-ADC) and an arithmetic unit called the multiplying digital-to-analog converter (MDAC) that performs a sample-and-hold (S/H) operation, coarse D/A conversion, subtraction, and amplification. In operation, each stage performs an A/D conversion of Bi effective bits with r-bit redundancy, converts the digital output back to analog and subtracts it from the sampled and held analog input. This residue is amplified with a gain of

2^{B i} 1 ^r

G i = ^{+ −} (3.1)

and fed to the next stage. The stages operate concurrently; that is, at any time, the first stage operates on the most recent sample while all other stages operate on residues from previous samples. Serial stages operate in opposite clock phases. The digital outputs of the stages 1B +r B.... _k+ are delayed so that their values correspond to r_k the same input sample.

Figure 3.3 Block diagram of one pipeline stage

The analog transfer function of a Bi+r-bit pipeline stage follows the equation

Vout,i = GiVin,i+DiVref (3.2)

where Di is an integer, the value of which is dependent on the output of the sub-ADC and with a step of 2 when r = 0 and 1 otherwise. The other terms Gi and Vin,i and the addition in Equation 3.2 are provided by the MDAC [17].

(

)

Di∈ −⎡⎣ Bi− + Bi− ⎤⎦

3.2.1 Per-Stage Resolution

The pipelined ADC architecture allows a designer flexibility in the choice of sub-ADC resolution for each stage. As such, the most common implementation of the pipelined ADC is a 1.5 bits-per-stage structure. The reduction in stage resolution allows for very fast conversion times and small power consumptions. This is due to the relaxed requirement of the sub-ADC, and is most effective in designs for low-to-medium resolution.

The most other pipelined ADCs fall into a class of pipelines known as multi-bit pipeline ADCs. These are pipelines with greater than 1.5 bits-per-stage sub-ADC resolution, and are most useful in design situations requiring large overall ADC resolutions. The advantage of a multi-bit pipeline is the large gain at output of the first MDAC – noise power contributions of all following stages are reduced by the squared MDAC gain. High-resolution designs place stringent requirements on the ADC noise and the size and power consumption of the back-end stages can be decreased effectively with the large gain from a multi-bit stage. The aggressive scaling leaves

The most other pipelined ADCs fall into a class of pipelines known as multi-bit pipeline ADCs. These are pipelines with greater than 1.5 bits-per-stage sub-ADC resolution, and are most useful in design situations requiring large overall ADC resolutions. The advantage of a multi-bit pipeline is the large gain at output of the first MDAC – noise power contributions of all following stages are reduced by the squared MDAC gain. High-resolution designs place stringent requirements on the ADC noise and the size and power consumption of the back-end stages can be decreased effectively with the large gain from a multi-bit stage. The aggressive scaling leaves