THESIS ORGANIZATION

The chapter 2 of this thesis will be the introduction of the LVDS standard. The specification is presented in detail and the applications for the standard are shown.

The chapter 3 is devoted to the PLL. The design of PLL should be the most critical part in the transmitter. Therefore, the design and verification by the simulation is described in this chapter. In the chapter 4, discussions of the serial-links are presented and the design of the transmitter is presented. The measurement results are shown in chapter 5 and the conclusion and future work are given in chapter 6.

Parallel-based technology

Serial-based technology

Figure 1.1 The parallel-based technology & the serial-based technology

Figure 1.2 The data rate required for the flat panel display systems

Figure 1.3 The architecture utilizing the differential mode to reduce the EMI

Figure 1.4 The clock-timed signals (upper part) and the phase-timed signals (lower part)

Figure 1.5 Industrial standards for high-speed serial link.

Chapter 2

Specifications of Low Voltage Differential Signaling (LVDS)

2.1 I

For the advance in the process technology, the application is more powerful and less expansive. At present, not only the concept of user-friendly-interface but also the application of multimedia demands increasingly data transfer. Because they give users better experience and more entertainment, this trend will not stop in the near future.

Besides, since the operating speed of the chip approaches several giga-hertz, the data transfer between the chips also requires very high speed I/O interface, otherwise the system performance degrades importantly.

However, the standards, serviceable in the past decades, such as RS-422, RS-485, SCSI and so forth, can not do the job. These standards all have their own notable degradation while transferring raw data across a medium. Challenges, such as power consumption, fast data transfer and economical solution, remain to be solved.

However, these factors often have relations of trade-off. Fast data transfer always requires higher power consumption. Lower power consumption always implies higher circuit complexity, therefore higher cost. Also these challenges should be solved under the requirement of lower voltage level, which is a severe terms.

Therefore, some standards have been proposed. The Low-Voltage-Differential-signaling (LVDS) is one of them. It has lower voltage swing (about 400 mV), higher data rate (above 400Mb/s) and lower power

consumptions. It can solve the bottleneck problems while serving as the high speed I/O interface in a wide range of application areas.

There are two industry standards that define LVDS [3]. The more common of the two is the generic electrical layer standard defined by the TIA (Telecommunications Industry Association) [4], which is known as ANSI/TIA/EIA-644, and the other is the IEEE (Institute for Electrical and Electronics Engineering) standard which is titled SCI (Scalable Coherent Interface).

2.1.1 ANSI/TIA/EIA-644

The editor position of this specification is held by the National Semiconductor Corporation. The electric characteristic of the driver output and the receiver input is defined. The functional specifications and the protocols are not defined. Therefore it is the more generic of the two standards and is intended for multiple applications. The electrical-only ANSI/TIA/EIA-644 standard is shown in Table 2.1, and it is intended to be referenced by other standards that specify the complete interface (connectors, protocol, etc.). The standard implies a recommended maximum data rate of 655 Mb/s and a theoretical limitation of 1.923 Gb/s. However, the speed achievable is not definite as its recommendation. It is application (desired signal quality, such as SNR) and device (such as transition time) specific. At present, the LVDS standard is feasible under the operating speed ranging from 500 Mb/s to 1.5 Gb/s above. Also the media specification is supplied in this standard and the failsafe operations of the receiver under fault conditions are given. Besides, other configurations are discussed, such as multi-drop or bidirectional half-duplex configurations, as shown in the figure 2.1.

2.1.2 IEEE 1596.3 SCI-LVDS

This standard, SCI-LVDS, is defined as a subset of SCI and is specified in the IEEE 1596.3 standard, which is approved in Mar. 1994. Originally, the SCI standard referenced a differential ECL (Emitter-Couple-Logic) within the SCI 1596-1992 IEEE standard [5]. However, the ECL standard is although high-speed with the disadvantage of massive power consumptions. Besides, ECL and PECL require more complex termination than the one-resistor solution for LVDS [6]. PECL drivers commonly require 220Ω pull down resistors from each driver output, along with 100Ω resistor across the receiver input. Therefore, this SCI standard only addressed the high-speed aspect but ignore the low-power requirement. Thus, the SCI-LVDS is introduced to include the power consumption issues.

The SCI-LVDS standard specified the electric signaling levels for the purpose of high-speed data transfer and low-power requirement. The electric characteristic is similar to the TIA version, but differs in some electric requirements and load conditions. Both standards feature similar driver output levels, receiver thresholds and data rates. However, the SCI-LVDS also defines the encoding for packet switching used in SCI data transfer, which is not within the scope of TIA version. Packets are constructed from 2-byte (doublet) symbols, which is the fundamental 16-bit symbol size. The media specification is not given. Also the data transfer speed is not noted as the former one. It is in the order of 500 Mb/s based on serial or parallel transmission of 1, 4, 8, 16, 32 and 64 … bits.

In the interest of promoting a wider standard, no specific process technology, medium, or power supply voltages are defined by either standard. This means that LVDS can be implemented in CMOS, GaAs or other applicable technologies, migrate from 5V to 3.3V to sub-3V supplies, and transmit over PCB traces or cable, thereby serving a broad range of applications in many industry segments.

National Semiconductor Corporation held the chairperson position for this standard. As discussed, the generic property of ANSI/TIA/EIA-644 makes it more popular than the IEEE 1596.3 SCI-LVDS standard. Therefore, this design is based on the ANSI/TIA/EIA-644 standard.

2.2 S

LVDS

The basic principle and characteristic of the Low-Voltage Differential Signaling (LVDS) is discussed as following.

2.2.1 Basic Concepts of LVDS standard

The basic topology of LVDS is shown in figure 2.2, which shows a simplified driver and receiver connected via 100Ω differential impedance media. As shown in figure 2.3, it has four switches, constructed by MOS here, and two current sources.

The signaling is operating on a differential pair line, such as two balance PCB traces or balance cable lines. Based on the transmitted data, these four switches will change the current path to induce the voltage polarity change. The receiver has a DC impedance of 100Ω and the switched-current across the impedance will generating the essential part of the voltage sensed by receiver, which is about 350 mV.

For the method of differential signaling, LVDS is less susceptible to common-mode noise than single-ended schemes. Therefore the electromagnetic emission will have less impact on the signal quality. Differential transmission uses two wires with opposite current/voltage swings instead of the one wire used in single-ended methods to convey data information. The advantage of the differential approach is that if noise is coupled onto the two wires as common-mode (the noise appears on both lines equally) and is thus rejected by the receiver which detects only

the voltage difference between the two signals. The differential signals also tend to radiate less noise than single-ended signals due to the canceling of magnetic fields.

The current-mode driver is not prone to ringing and switching spikes, further reducing noise. Because differential technologies such as LVDS reduce concerns about noise, they can use lower signal voltage swings. This advantage is crucial, because it is impossible to raise data rates and lower power consumption without using low voltage swings. The low swing nature of the driver means data can be switched very quickly.

Since the driver is also current-mode, very low almost flat power consumption across frequency is obtained. Switching spikes in the driver are very small, so that total current consumption does not increase exponentially as switching frequency is increased. Also, the power consumed by the load (3.5 mA × 350 mV = 1.225 mW) is very small in magnitude.

The differential data transmission method although has lots of advantages, but the cost of extra cable lines or PCB traces seems to be a disadvantage, compared with the single-ended scheme. However, the single-ended scheme always consumes massive power, and a great deal of ground pins are demanded for acceptable signal quality. Since the ground of such scheme is not always clear, the number of ground pins demanded is large. Therefore, extra pins required by the differential data transmission method should not be a major problem. At the same time, the PCB design is a challenge of both scheme, which is out of the scope of this paper.

Dedicated point-to-point links provide the best signal quality due to the clear paths they provide. LVDS has many advantages that make it likely to become the next famous data transmission standard rates from hundreds to thousands of megabits per second and short haul distances in the tens of meters. In this role, LVDS far exceeds the 20 Kb/s to 30 Mb/s rates of the common RS-232, RS-422, and RS-485 standards.

2.2.2 Several Configurations

As shown in Fig. 2.2, the point-to-point configuration is the most general and basic scheme used for LVDS standard [3]. However, other topologies/configurations are also possible.

The configuration, as shown in the upper part of Fig. 2.1, allows bi-directional communication over a single twisted pair cable. Data can flow in only one direction at a time. The requirement for two terminating resistors reduces the signal (and thus the differential noise margin), so this configuration should be considered only where noise is low and transmission distance is short (< 10 m).

In the lower part of Fig. 2.5, a multi-drop configuration connects multiple receivers to a driver. These are useful in data distribution applications. They can also be used if the stub lengths are as short as possible (less than 12 mm, which is application dependent). Use receivers with power-off high impedance if the network needs to remain active when one or more nodes are powered down. This application is good when the same set of data needs to be distributed to multiple locations.

Also, multi-point configuration supports multiple drivers, but only one is allowed to be active at any given time. With such scheme, double terminated busses can be used without trading off signal swing and noise margin. Termination should be located at both ends of the bus. Besides, failsafe operation should be considered.

When all drivers, constructed in tri-state type, are in the high impedance state, a known state on the bus is required. As with the multi-drop bus, stubs off the mainline should be kept as short as possible to minimize transmission line problems, such as reflection or decay.

2.2.3 Discussion of the termination, connecter and cables

The distance and the speed requirements seem to be a simple question at first.

However, after some study, the question is rather a system level one than a device level one. A number of other parameters besides the switching characteristics of the drivers and receivers must be known. The cables, connectors and PCB used are application dependant and have essential effects on the system performance. Also, the performance criteria for the system should be identified. Therefore, discussion for termination, cables and connectors are given as below and the signal quality criteria is discussion in the next subsection.

It is very common for designers to automatically use any off-the-shelf cables and connectors and 50 Ω auto-routing when doing new designs. While this may work for some LVDS designs, it can lead to noise problems. Remember that LVDS is differential and does have low swing, current-mode outputs to reduce noise, but that its transition times are quite fast. This means impedance matching (especially differential impedance matching) is very important. Those off-the-shelf connectors and that cheap blue ribbon cable are not meant for high-speed signals (especially differential signals) and do not always have controlled impedance.

As discussed above, the termination is an important issue considering high frequency signaling. The signal quality will be impacted severely with bad termination, because of the electromagnetic effect. The signal will reflect from the far terminal and corrupt the signal characteristic. Whether the LVDS transmission medium consists of cables or controlled impedance traces on a printed circuit board, the transmission medium must be terminated to its characteristic differential impedance to complete the current loop and terminate the high-speed signals. If the medium is not properly terminated, signals reflect from the end of the cables or traces and may interfere with succeeding signals.

Proper termination also reduces unwanted electro-magnetic emissions and provides the optimum signal quality. To prevent reflections, LVDS requires a

terminating resistor that is matched to the actual cables or PCB traces differential impedance. Commonly a 100 Ω termination is employed. This resistor completes the current loop and properly terminates the signal. This resistor is placed across the differential signal lines as close as possible to the receiver input. Also, Center tap capacitance termination may also be used in conjunction with two 50Ω resistors to filter common-mode noise at the expense of extra components if desired. This is shown in the figure 2.5. This termination is not commonly used or required.

The simplicity of the LVDS termination scheme makes it easy to implement in most applications. ECL and PECL (Positive Emitter Coupled Logic) require more complex termination than the one-resistor solution for LVDS [6]. PECL drivers commonly require 220 Ω pull down resistors from each driver output, along with 100 Ω resistor across the receiver input. For more stringent specification, impedance control should be employed or the signal quality will be corrupted by signal reflection.

As shown above, the LVDS standard is intended to be referenced by other standard [7], [8]. It does not define the functional properties or system protocols. Also, the media is not given, for the generic purpose. The referencing standard should include the media, data rate, length, connectors, function, and pin assignments, etc.

The connectors and cables required are application specific.

For high-speed operation, it suggests that to use differential cables is better choice for LVDS standards, such as twisted pair cables (shown in figure 2.6), twin-ax cables (shown in figure 2.7) or flex circuits (shown in figure 2.8) with closely coupled differential traces. CAT 3, suitable for distance about 10 m, and CAT 5, for longer distance, is readily available.

Twisted pair cables are a relatively low cost solution with good balance. It is flexible and an appropriate medium for long distance transmission, based on the

application.

Twin-ax cables are also flexible and have low skew compared with the twisted pair cables. This type of cable shields around each pair for isolation. For being not twisted, they tend to have very low skew within a pair and between pairs. These cables are for the purpose of long distance. Twin-ax cables have been commonly utilized in Channel Link and FPD-Link applications.

Flex circuits is a good choice for very short runs. However, as shown in figure 2.7, it is difficult to be shielded. It is often used as interconnects between boards within systems. The members of differential pairs should be closely coupled (S < W) and use ground shield traces between the different differential pairs.

Since the system always deviates from one to the other, the connectors are also application dependent. The connectors depend upon the cable system being used, the number of pins, the need for shielding and other mechanical footprint concerns.

Depending on the data rate, the standard connectors, for medium speed, and the optimized, low skew connectors, for higher speed, are readily available and less expansive.

2.2.4 The criteria for Signal Quality

As mentioned yet, signal quality may be measured by a variety of means, such as rise time at the load, jitter at the eye pattern and bit error rate test, etc [9]. The eye pattern and bit error rate test is the most common methods in design the high speed I/O interface. They are described as following.

Eye pattern measurements are useful in measuring the amount of jitter versus the unit internal, to establish the data rate versus cable length curves. Therefore the method is a very accurate way to measure the expected signal quality and severed as system level performance criteria.

The eye pattern is used to measure the effects of inter-symbol interference (ISI) on random data transmitted through a particular medium. The signal transition time is data dependant. For example, in the most general NRZ encoding scheme, a transition high after a long series of low will have a sharper edge. And a fast transition will have softer edge. Overlaid the signal, the so-called eye pattern is shown. The effect is shown in the figure 2.9. The left side is the ideal eye pattern and the right side is the practical eye pattern at the end of cables. As it shows, the practical one has not only slower transition edge but also wider width of the crossing points. Besides, for the receiver end, the appropriate eye pattern should be identified. The figure 2.10 is an simplified example. It describes the sampling locations for minimum jitter.

Peak-to-peak jitter is defined as the width of the signal crossing the optimal receiver thresholds. However, the receiver is specified to switch between + 100 mV and – 100 mV. Therefore for a worse case jitter criterion, a box should be drawn between ± 100 mV and the jitter is measured between the first and last crossing at ± 100 mV. If the vertical axis units in Fig. 2.10 were 100mV/division, the worse case jitter is at ± 100 mV levels.

Eye patterns can show the effects of a random data pattern after transmitting through medium. Therefore, they provide a useful tool to analyze jitter and the resulting signal quality. They served as a criterion to determine the maximum cable length for a given data rate or vice versa. The acceptable amount of jitter is different from system to system. Commonly 5 %, 10 %, or 20 % is acceptable, with 20 % jitter usually being an upper practical limit. It will be difficult to make error-free recovery of NRZ data, with more than 20% jitter, which is usually close down the eye opening.

The other popular method is the bit error rate test. Bit error rate testing is one way to measure of the performance of a communications system. The standard equation for a bit error rate measurement is:

Bit Error Rate = (Number of Bit errors)/(Total Number of Bits) Common measurement points are bit error rates of:

≤ 1 x 10-12 => One or less errors in 1 trillion bits sent

≤ 1 x 10-14 => One or less errors in 100 trillion bits sent

Note that BER testing is time intensive. The time length of the test is determined by the data rate and also the desired performance benchmark. For example, if the data rate is 50Mbps, and the benchmark is an error rate of 1 x 10-14 or better, a run time of 2,000,000 seconds is required for a serial channel. 2,000,000 seconds equates to 555.6

Note that BER testing is time intensive. The time length of the test is determined by the data rate and also the desired performance benchmark. For example, if the data rate is 50Mbps, and the benchmark is an error rate of 1 x 10-14 or better, a run time of 2,000,000 seconds is required for a serial channel. 2,000,000 seconds equates to 555.6