Conclusion of the LVDS standard

Consumers are demanding more realistic, visual information in the office and in the home. This is driving the need to move video, 3-D graphics and photo-realistic image data from camera to PCs and printers through LAN, phone, and satellite systems to home set top boxes and digital VCRs. Solutions exist today to move this high-speed digital data both very short and very long distances: on a printed circuit board (PCB) and across fiber or satellite networks. Moving this data from

board-to-board or box-to-box, however, requires an extremely high-performance solution that consumes a minimum of power, generates little noise (must meet increasingly stringent FCC/CISPR EMI requirements), is relatively immune to noise and is inexpensive. Many kinds of specifications are purposed for these requirements, such as ECL, PECL, LVDS and RSDS [10].

As shown above, the LVDS standard can solve these problems and severed as a high performance I/O interface. The high speed signaling is achieved by the differential signaling with lower swing. The differential signaling also provides the advantage of reducing EMI, power, complexity and better noise immunity. Besides, since the high speed achievable by the LVDS standard, it allows designers to implement a simple point-to-point link without complex termination issues. Also, the low power and differential signaling makes the integration with the digital core and PLL a reliable solution. Therefore, a compact, low cost high speed interface is achievable. When gigabits at mW are required, the LVDS solution can be a simple and high-performance choice. Merits and drawbacks of different I/O interface technologies are summarized in table 2.2 and table 2.3.

Table 2.1 The electrical-only ANSI/TIA/EIA-644 (LVDS) standard of LVDS.

Parameter Description Min Max

VOD Differential Output Voltage 247 mV 454 mV VOS Output Offset Voltage 1.125 V 1.375 V

Table 2.2 Merits and drawbacks of different I/O interface technologies.

Advantages LVDS PECL Optics RS-422 GTL TTL

Data rate up to 1 Gb/s + + + – – –

Table 2.3 Quick comparison of the differential signaling standards

parameter LVDS PECL RS-422

Differential output voltage ± 250~450 mV ± 600~1000 mV ± 2~ ± 5 Receiver input threshold ± 100 mV ± 200~300 mV ± 200 mV

Data rate >400 Mb/s >400 Mb/s <30 Mb/s Supply current quad driver* 8 mA (max) 32~65 mA (max) 60 mA (max) Supply current quad receiver* 15 mA (max) 40 mA (max) 23 mA (max) Propagation delay of driver 1.7 ns (max) 4.5 ns (max) 11 ns (max) Propagation delay of receiver 2.4 ns (max) 7.0 ns (max) 30 ns (max) Pulse skew (driver or receiver) 400 ps (max) 500ps (max) N/A

Figure 2.1 Bidirectional half-duplex and multi-drop configurations

Figure 2.2 Basic point-to-point configuration

Figure 2.3 Basic topology of LVDS standard

Figure 2.4 Multi-point configuration

Figure 2.5 Termination configuration

Figure 2.6 Cross section drawing of a twisted pair cable

Figure 2.7 Cross section drawing of a twin-ax cable

Figure 2.8 Cross section drawing of a flex circuit

Figure 2.9 Cause of the eye pattern

Figure 2.10 Eye pattern of the NRZ

Figure 2.11 The signal level of LVDS standard

Figure 2.12 The scope of the LVDS applications

Chapter 3

Design of PLL

3.1 I

Monolithic phase-locked loops, ever since their introduction, have found wide use in a number of applications. The commercial success of local area networks and the demand for higher data rates have recently increased the need for inexpensive high-frequency phase-locked loops. Data storage and RF data communications applications have also added to this need. Silicon CMOS is a natural technology for these circuits because the high production volume of digital CMOS circuits has significantly reduced the unit cost. Also, with advance of technology, the system operating speed is increasing. The high speed data transmission is transmitted between chips or even inside the chip. Therefore, the timing accuracy is an important issue in the high performance digital system. The PLL or DLL (delay-locked loop) is often utilized to reduce the timing skew. In addition, phase-locked loop is developed in such a delicate way that the integration with the digital block is possible. Therefore, the PLL is often one of the important blocks of a high performance system.

The serial-based data transmission is one of the solutions to the increasing demand of high speed data transfer. The clock-timed data signals are transformed to the phase-timed data signals and the better termination schemes are introduced to achieve better signal quality. The phase-locked loop is a traditional method to this transform. The multiple data bits are retimed to the phase edge and transmitted in a single clock cycle. Therefore, higher data rate is available in an inexpensive way.

However, DLL is sometimes a better choice in some application, for its

simplicity and better jitter performance. However, the lack of ability to frequency synthesis is major drawback of DLL. Therefore, PLL is more popular than DLL in many high performance systems.

Therefore, the PLL is the core of the design of serial-based data transmission.

This chapter is devoted to this important circuit block.

3.2

PLL

At first, because PLL is utilized in a variety of applications, the design of PLL is application specific. For example, requirement of PLL is very different in the purpose of de-skew and of frequency synthesis. The former is achievable even by DLL, a less complicate method. However, the latter is impacted by lots of factors, such as switching speed, frequency range, accuracy, etc.

Therefore, the topology of this transmitter is shown as figure 3.1. The seven parallel data signals are retimed to a single data signal by parallel-to-serial converter.

The driver then signals the serial-based data through the channel, like PCB traces or cable lines. Because the targeted data rate is about 1.2 Gb/s, the PLL required is a relative simple and relax. The operating frequency is around 200 MHz. Therefore, a simpler circuit implementation can be chose.

3.3

PLL

The basic architecture of PLL is shown in figure 3.2 [11]. This is a conceptual plot of this so-called “Charge-pump PLL”, which is a popular configuration of PLL.

However, the PLL will not work properly under the PVT deviation conditions.

Therefore, the self-bias technique is employed to combat with this difficulty [12].

The technique of self-bias is employed in this PLL. It can provide a bandwidth

that tracks operating frequency. This tracking bandwidth can in turn provide a very broad frequency range, minimizing the supply and substrate noise induced jitter with a high input tracking bandwidth. Besides, fixed damping factor and input offset phase error cancellation are also advantage of this architecture.

At first, the phase-frequency detector (PFD) senses the phase difference between CLK_ref and the feedback signal, and then produces signals to determine whether the current source or the current sink is on. The loop filter transforms this current into voltage, which is used to control the voltage control oscillator (VCO).

The loop filter is 2^nd order here, the C² is utilized for the purpose of filtering the high frequency signals, which will disturb the VCO and corrupt the timing accuracy. Then the output of VCO is feedback to the PFD through a frequency divider. This divider is included to achieve the important characteristic of PLL, frequency synthesis.

3.3.1 The basic analysis of PLL

Analysis of PLL is often complicated, for it is a mixed-signal system. The input signal is sampled at PFD, and transform to analog signal through loop filter and VCO.

Besides, the frequency divider is usually constructed as a simple digital counter.

Therefore, discrete and continuous analysis is required to accurately predict the behavior of PLL. Which makes the problem even more complicated is that PLL is a system focus on the timing information not a normal voltage or current signal.

Consequently, there exists some approximate analysis of PLL, which may help designer to achieve the basic property of PLL, such as stability, settling, noise property, etc.

The classic analysis is shown in figure 3.3, which is a continuous, phase space conceptual plot. This model will be reasonable, for the loop bandwidth of PLL is generally lower than the operating frequency about 10 times, which is often true for

most cases.

As shown in figure 3.3, after some algebraic manipulation, the equation is as below:

The Eq. (3.4) is approximately the unit-gain frequency of the open loop frequency response.

(3.6) As we will see later, for the consideration of stability, the value of C2 and R1 can not be too large. Therefore, the approximate in Eq. (3.6) should be reasonable for general cases. This relation between the close loop response and the open loop response can be shown in figure 3.4. The ωn is the geometric mean of the zero and the unit-gain frequency of the open loop frequency response. Therefore, in log scale, this plot shows ωn is at the middle of zero and the unit-gain frequency.

Besides, the damping factor ζ is important in the settling property of PLL. The

small ζ means the change in input phase error will induce a large peaking in the output phase, which is always not desired for most application. The clock and data recovery circuit (CDR) which utilizes PLL as a timing regenerator will suffer from this characteristic. Besides, because the data transmission may through a long distance, like optical system, sometimes circuits as repeaters will be introduced to lessen the impact of channel loss. The amount of peaking in the phase domain must be well controlled, or the error-less data recovery will become very difficult in such case. In most cases, the ζ is often chosen to be larger than one. Sometimes, the value will be vary large, which makes the loop filter inside the chips is not acceptable.

3.3.2 The stability of PLL

However, as a general problem in all kinds of feedback system, the stability problem should deserve some attention. Figure 3.4 also shows the phase response of the open loop PLL. The zero is introduced to offer larger noise margin and improve the stability property. However, the loop filter is 2^nd order, which makes stabilizing the total feedback system a more complicated problem. Since PLL may require a as wide operating bandwidth as possible, the K^vco value is sometimes vary larges, such as several hundred MHz per volt. The zero created by the C1 and R1 pair improves the stability, but every time the charge pump turns on, the voltage jump on R¹ is unavoidable. Hence, a second capacitor, C2 is introduced. The value of C2 should suffer from the tradeoff relation between stability and timing accuracy. The impact of C2 can be seen as below:

(3.7)

The Eq. (3.7) also shows that the not only the phase response is changed but also the amplitude response is changed. The unit-gain frequency is smaller than Eq. (3.4).

In general practice, the position of ωz, ωt, ωp2 is often chosen to be four times apart.

In such case, the phase margin is about 60° and the damping factor is one. The phase margin is enough for most application, and it is suitable for the design of LVDS transmitter. Also, the damping factor of one indicates the settling behavior of PLL will not be a severe problem.

Based on the equation given above, the parameter of PLL can be chosen. At first, the PLL specification is examined, and the operating frequency range will determine the rough value of Kvco . The value of Ip is chosen to be around 100μA to 1mA for an off-chip loop filter. If an on-chip filter is employed, decrease the value of Ip so that the reasonable trade off between chip area and charge pump current could be reached.

Depending on the application, the reasonable value of N can be chosen. The frequency synthesis property of PLL may introduce few problems. However, for the LVDS driver, the frequency switching is not a necessary function. The unit-gain frequency of open loop should be about 1/10 of the operating frequency; the reason will be seen latter.

Now, the basic parameter is ready. The loop filter is the major problem of the design. As shown above, the value of R¹, C¹, C² can be determined after some algebraic manipulation. This is shown as below:

(3.8) The value of C² above is an upper limit. In general, the C² will be less than 1/20 of C¹. Therefore, the PLL analysis can be simplified.

3.3.3 The discrete property of PLL

However, as described at first, the PLL can not be analyzed without assumptions of small phase error, limited operating frequency range. The continuous linear analysis is a simplified model for intuitively understanding. However, in this model, the operating frequency has no effect, which is not practically true. The ratio between operating frequency and the loop bandwidth can not be too large, or the phase error will not be eliminated as expected from the PLL. The reason is mainly from the ignorance of the mixed-signal property of PLL [13], [14]. The digital sampling property of PFD and charge pump will introduce extra phase shift. Besides, the digital frequency divider will also degrade the phase margin of the total feedback system.

Therefore, by this approximated model, the parameter can be chosen, but extra verification is needed.

However, in order to determine the optimal parameter of PLL, the device level simulation will be a time-consuming work. Therefore, a behavior model for such mixed-signal PLL is built. This model can be seen in figure 3.5. The sampling property of PFD is modeled by multiplying the phase error with a narrow width, unity height pulse. And this signal will control the current source to drive approximately equal charge into the loop filter. The voltage on the loop filter controls VCO and the output of VCO is feedback to the PFD trough the divider. This model can help us to determine the rough parameter to reduce the time required for simulation.

The z-domain stability problem can be shown in the figure 3.6. Besides, the limit of operating frequency for a specific PLL can be shown as below:

(3.9)

These equations give us a simple relation to consider the limit of PLL. Besides, the loop delay induced extra phase shift can be added to the design procedure easily.

3.3.4 The noise property of PLL

The noise property of PLL has been surveyed for many years and it is not fully solved for the progress of technology and the complexity of applications. More and more applications demands better PLL for its property of easy integration with the digital core and varieties of functionality. However, since PLL is such a complicate system, a fully predictable model is not available. Compared with the power noise or ground noise, the electric noise of the device, which is often ignored in traditional analysis, is no longer ignorable.

The noise in the PLL can be analyzed in figure 3.7. For practical reasons, all the building blocks like PFD, LPF, VCO and frequency divider is made by the transistor.

Therefore, the electric noise always intrudes some error, deviating from ideal case.

The noise contributing from each block can be shown as below:

(3.10)

(3.11)

(3.12)

(3.13)

(3.14) From the equations above, equations (3.10), (3.11), (3.14) imply a low-pass

property of the noise source at input, PFD and frequency divider. (3.12) and (3.14) suggests that noise at VCO is filtered with high-pass property and noise at LPF is filtered with band-pass property. Those noise characteristic will set different conditions for different applications. Besides, the periodic reset property of the digital PFD can reduce the impact caused by the 1/f noise.

The noise analysis can be done by summing all the power spectrums induced by those building blocks. However, the noise source at input and the VCO is generally more important than others. Thus, (3.10) and (3.14) is generally the basic equation for the PLL noise analysis. Due to these two equations, a trade-off relation is suggested.

The higher loop bandwidth will filter the noise at VCO severely and the input noise will be passed to the output. However, for general cases, the input source is often a crystal oscillator, which is a relatively clearer source than VCO. Therefore, higher loop bandwidth is preferred. The noise at output is mainly affected by the noise at VCO. However, the loop bandwidth is limited by the stability problem, which is addressed in the sector 3.3.2.

3.4

PLL

3.4.1 The phase-frequency detector (PFD)

For some application, the phase detector (PD) and the frequency detector (FD) are utilizing separately. The PD can adjust the phase difference but the frequency error can not be distinguished from the phase difference for the PD. Therefore, a FD is required for such case. Besides, the PD sometimes requires 50% duty-cycle inputs, or a steady phase offset will be introduced. However, for our application, the digital PFD is appropriate for its simplicity.

The PFD is a circuit block which senses the phase and frequency difference

between its two inputs, ϕin and ϕfeedback. A linear PFD is capable of generating a voltage level proportional to the phase difference and frequency error. The basic block diagram of PFD is shown in figure 3.8. As shown in the figure 3.8, the rising edge of the inputs will define the phase error. At first, the Fin is form low to high and the UP signal is pulled high. Then, as long as the F^feedback goes high, the down signal will be pulled high and reset UP and DOWN signals at the same time. The functionality can be shown as state diagram in figure 3.9. The rising edge of input will change the state.

Also, the general characteristic of the PFD can be shown in the figure 3.10, which shows the characteristic curve of the PFD, combined with charge pump (CP) and the low-pass filter (LPF). Form figure 3.10, we can see the reason that PFD can be the PD and FD at the same time. Since the frequency error will constantly increase the phase error, which will be sensed by the PFD. Therefore, a positive area at the figure 3.10, means a increasing voltage level is resulted. The control voltage of VCO is higher and the frequency of the output steps up. Hence, the PFD can generate a voltage level proportional to the phase error and frequency error.

Ideally the linear PFD should generate any voltage level for any phase difference.

However, for a small phase error, the PFD can’t work properly, which results in the dead zone region in the characteristic curve. The dead zone region is an undetectable phase error for the PFD, which is highly undesirable for the PLL for accumulating timing error. However, the reason of dead zone is that a small phase error will change the state quickly, which equivalently requires fast switching of the CP. The CP can not be activated unless enough turn on time is provided. Hence, a general solution to this problem is to insert the delay cell to increase the turn on time for the CP. The delay cell may increase the sensibility of the PFD but narrower operating frequency will be the disadvantage. This drawback is mainly because the extra delay will result in a longer recovery time for the PFD to sense the next event. The maximum operating

frequency can be shown as below:

(3.15) where Td is the delay time of the delay cell.

The circuit implementation is shown in the figure 3.12, which is based on the

The circuit implementation is shown in the figure 3.12, which is based on the