CHAPTER 3 DESIGN OF PLL
3.3 THE BASIC ARCHITECHURE OF PLL
The basic architecture of PLL is shown in figure 3.2 [11]. This is a conceptual plot of this so-called “Charge-pump PLL”, which is a popular configuration of PLL.
However, the PLL will not work properly under the PVT deviation conditions.
Therefore, the self-bias technique is employed to combat with this difficulty [12].
The technique of self-bias is employed in this PLL. It can provide a bandwidth
that tracks operating frequency. This tracking bandwidth can in turn provide a very broad frequency range, minimizing the supply and substrate noise induced jitter with a high input tracking bandwidth. Besides, fixed damping factor and input offset phase error cancellation are also advantage of this architecture.
At first, the phase-frequency detector (PFD) senses the phase difference between CLK_ref and the feedback signal, and then produces signals to determine whether the current source or the current sink is on. The loop filter transforms this current into voltage, which is used to control the voltage control oscillator (VCO).
The loop filter is 2nd order here, the C2 is utilized for the purpose of filtering the high frequency signals, which will disturb the VCO and corrupt the timing accuracy. Then the output of VCO is feedback to the PFD through a frequency divider. This divider is included to achieve the important characteristic of PLL, frequency synthesis.
3.3.1 The basic analysis of PLL
Analysis of PLL is often complicated, for it is a mixed-signal system. The input signal is sampled at PFD, and transform to analog signal through loop filter and VCO.
Besides, the frequency divider is usually constructed as a simple digital counter.
Therefore, discrete and continuous analysis is required to accurately predict the behavior of PLL. Which makes the problem even more complicated is that PLL is a system focus on the timing information not a normal voltage or current signal.
Consequently, there exists some approximate analysis of PLL, which may help designer to achieve the basic property of PLL, such as stability, settling, noise property, etc.
The classic analysis is shown in figure 3.3, which is a continuous, phase space conceptual plot. This model will be reasonable, for the loop bandwidth of PLL is generally lower than the operating frequency about 10 times, which is often true for
most cases.
As shown in figure 3.3, after some algebraic manipulation, the equation is as below:
The Eq. (3.4) is approximately the unit-gain frequency of the open loop frequency response.
(3.6) As we will see later, for the consideration of stability, the value of C2 and R1 can not be too large. Therefore, the approximate in Eq. (3.6) should be reasonable for general cases. This relation between the close loop response and the open loop response can be shown in figure 3.4. The ωn is the geometric mean of the zero and the unit-gain frequency of the open loop frequency response. Therefore, in log scale, this plot shows ωn is at the middle of zero and the unit-gain frequency.
Besides, the damping factor ζ is important in the settling property of PLL. The
small ζ means the change in input phase error will induce a large peaking in the output phase, which is always not desired for most application. The clock and data recovery circuit (CDR) which utilizes PLL as a timing regenerator will suffer from this characteristic. Besides, because the data transmission may through a long distance, like optical system, sometimes circuits as repeaters will be introduced to lessen the impact of channel loss. The amount of peaking in the phase domain must be well controlled, or the error-less data recovery will become very difficult in such case. In most cases, the ζ is often chosen to be larger than one. Sometimes, the value will be vary large, which makes the loop filter inside the chips is not acceptable.
3.3.2 The stability of PLL
However, as a general problem in all kinds of feedback system, the stability problem should deserve some attention. Figure 3.4 also shows the phase response of the open loop PLL. The zero is introduced to offer larger noise margin and improve the stability property. However, the loop filter is 2nd order, which makes stabilizing the total feedback system a more complicated problem. Since PLL may require a as wide operating bandwidth as possible, the Kvco value is sometimes vary larges, such as several hundred MHz per volt. The zero created by the C1 and R1 pair improves the stability, but every time the charge pump turns on, the voltage jump on R1 is unavoidable. Hence, a second capacitor, C2 is introduced. The value of C2 should suffer from the tradeoff relation between stability and timing accuracy. The impact of C2 can be seen as below:
(3.7)
The Eq. (3.7) also shows that the not only the phase response is changed but also the amplitude response is changed. The unit-gain frequency is smaller than Eq. (3.4).
In general practice, the position of ωz, ωt, ωp2 is often chosen to be four times apart.
In such case, the phase margin is about 60° and the damping factor is one. The phase margin is enough for most application, and it is suitable for the design of LVDS transmitter. Also, the damping factor of one indicates the settling behavior of PLL will not be a severe problem.
Based on the equation given above, the parameter of PLL can be chosen. At first, the PLL specification is examined, and the operating frequency range will determine the rough value of Kvco . The value of Ip is chosen to be around 100μA to 1mA for an off-chip loop filter. If an on-chip filter is employed, decrease the value of Ip so that the reasonable trade off between chip area and charge pump current could be reached.
Depending on the application, the reasonable value of N can be chosen. The frequency synthesis property of PLL may introduce few problems. However, for the LVDS driver, the frequency switching is not a necessary function. The unit-gain frequency of open loop should be about 1/10 of the operating frequency; the reason will be seen latter.
Now, the basic parameter is ready. The loop filter is the major problem of the design. As shown above, the value of R1, C1, C2 can be determined after some algebraic manipulation. This is shown as below:
(3.8) The value of C2 above is an upper limit. In general, the C2 will be less than 1/20 of C1. Therefore, the PLL analysis can be simplified.
3.3.3 The discrete property of PLL
However, as described at first, the PLL can not be analyzed without assumptions of small phase error, limited operating frequency range. The continuous linear analysis is a simplified model for intuitively understanding. However, in this model, the operating frequency has no effect, which is not practically true. The ratio between operating frequency and the loop bandwidth can not be too large, or the phase error will not be eliminated as expected from the PLL. The reason is mainly from the ignorance of the mixed-signal property of PLL [13], [14]. The digital sampling property of PFD and charge pump will introduce extra phase shift. Besides, the digital frequency divider will also degrade the phase margin of the total feedback system.
Therefore, by this approximated model, the parameter can be chosen, but extra verification is needed.
However, in order to determine the optimal parameter of PLL, the device level simulation will be a time-consuming work. Therefore, a behavior model for such mixed-signal PLL is built. This model can be seen in figure 3.5. The sampling property of PFD is modeled by multiplying the phase error with a narrow width, unity height pulse. And this signal will control the current source to drive approximately equal charge into the loop filter. The voltage on the loop filter controls VCO and the output of VCO is feedback to the PFD trough the divider. This model can help us to determine the rough parameter to reduce the time required for simulation.
The z-domain stability problem can be shown in the figure 3.6. Besides, the limit of operating frequency for a specific PLL can be shown as below:
(3.9)
These equations give us a simple relation to consider the limit of PLL. Besides, the loop delay induced extra phase shift can be added to the design procedure easily.
3.3.4 The noise property of PLL
The noise property of PLL has been surveyed for many years and it is not fully solved for the progress of technology and the complexity of applications. More and more applications demands better PLL for its property of easy integration with the digital core and varieties of functionality. However, since PLL is such a complicate system, a fully predictable model is not available. Compared with the power noise or ground noise, the electric noise of the device, which is often ignored in traditional analysis, is no longer ignorable.
The noise in the PLL can be analyzed in figure 3.7. For practical reasons, all the building blocks like PFD, LPF, VCO and frequency divider is made by the transistor.
Therefore, the electric noise always intrudes some error, deviating from ideal case.
The noise contributing from each block can be shown as below:
(3.10)
(3.11)
(3.12)
(3.13)
(3.14) From the equations above, equations (3.10), (3.11), (3.14) imply a low-pass
property of the noise source at input, PFD and frequency divider. (3.12) and (3.14) suggests that noise at VCO is filtered with high-pass property and noise at LPF is filtered with band-pass property. Those noise characteristic will set different conditions for different applications. Besides, the periodic reset property of the digital PFD can reduce the impact caused by the 1/f noise.
The noise analysis can be done by summing all the power spectrums induced by those building blocks. However, the noise source at input and the VCO is generally more important than others. Thus, (3.10) and (3.14) is generally the basic equation for the PLL noise analysis. Due to these two equations, a trade-off relation is suggested.
The higher loop bandwidth will filter the noise at VCO severely and the input noise will be passed to the output. However, for general cases, the input source is often a crystal oscillator, which is a relatively clearer source than VCO. Therefore, higher loop bandwidth is preferred. The noise at output is mainly affected by the noise at VCO. However, the loop bandwidth is limited by the stability problem, which is addressed in the sector 3.3.2.