CHAPTER 4 DESIGN OF TRANSMITTER
4.6 R ETIMING THE DATA
For serializing multiple parallel signals, the transition of signals should be avoided. This problem can be shown as below. The configuration without synchronization is shown in figure 4.18. The CLK signal will set the timing of the internal digital circuit and the PLL will generate seven signals with equal phase separation. These signals with different phase will be employed to serialize the data.
As shown in figure 4.19, the phase of PH0 and the digital signals should be approximately the same as the CLK signal. Nevertheless, PH0 and PH3 will set the bit time of D0 in the serialized signal. Therefore, there may not be enough time left for D0 to switch the multiplexer. Hence, the performance of the whole transmitter will be corrupted. For the same reason, the D6 may also has the same problem, which is shown in the figure 4.20.
In this case, the technique of synchronization is utilized. The configuration is shown in figure 4.21. The main idea of synchronization is to put the transition edge out of the sampling pulse period. For this purpose, at least two DFF must insert into the path. However, the sequence of the data will not be in order. Besides, the PLL may not be exactly in phase with CLK, and that will introduce another ambiguity into the sterilization process. With seven DFF switched by different phase signals, the data sequence still will not in order. Therefore, the synchronization scenario as figure 4.22 is shown. The data will be retimed to the output of PLL, which will actually determine the real timing of the data bits. Then, the extra DFF is inserted to serialize the data in order. The data sequence after synchronization is shown in figure 4.23
Figure 4.1 The basic architecture of the transmitter
Figure 4.2 The traditional method of signaling
Figure 4.3 Several types of output drivers
Figure 4.4 The 1st output buffer with CMFB
Figure 4.5 The 2nd output buffer with CMFB
Figure 4.6 The self-bias circuit
Figure 4.7 The basic architecture of PLL
Figure 4.8 The circuit blocks of the PFD
Figure 4.9 The VCO
Figure 4.10 The charge pump and loop filter
Figure 4.12 The bias-gen circuit
Figure 4.13 The PRBS
Figure 4.14 The simulation result of the PRBS
Figure 4.15 The multiplexer
Figure 4.16 The timing diagram of the multiplexer
Figure 4.17 The improved multiplexer
Figure 4.18 The circuit blocks of the non-synchronization configuration
Figure 4.19 The timing diagram for non-synchronization configuration
Figure 4.20 The timing diagram for configuration without synchronization
Figure 4.21 The configuration with synchronization
Figure 4.22 The scenario of synchronization
Figure 4.23 The timing diagram for configuration with synchronization
Chapter 5
Measurement Results
5.1 I
NTRODUCTIONThis measurement result is shown in this chapter. Two measurement results are described. The first one is the PLL and the second one is transmitter.
5.2 M
EASUEMENT FOR THE1
ST TAP-
OUTThe 1st tap-out is mainly a PLL. The layout of the PLL is in figure 5.1. The PLL output is droved by LVDS transmitter. The die photo is shown in figure 5.2. Also, PCB for measurement is shown in figure 5.3. The chip is packaged and large decouple capacitor is employed to reduce the supply noise. In figure 5.4, the measurement setup is shown. HP 8131A is used as a function generator. TEK. DSA 601A is the oscilloscope. As shown in figure 5.5, the measured output of the transmitter is shown.
The operating frequency is 100 MHz. The Pk-Pk jitter is about 83ps at 100 MHz, which is shown in figure 5.6. In figure 5.7, the measurement at 250 MHz is shown.
Also the Pk-Pk jitter is about 89ps in the figure 5.8. The measurement results is concluded in table 5.1.
5.3 M
EASUEMENT FOR THE2
ND TAP-
OUTAs described before, the second measurement is the transmitter. The layout of the transmitter is shown in figure 5.9. There two kinds of output buffers and PLL with
slightly difference. They are shown in figure 5.10 and figure 5.11. The output buffers are different in the CMFB and the PLL is different in the VCO. The third quadrant is the main blocks for this measurement. However, measurement for the rest will be shown. In figure 5.12, the die photo is shown. The PCB and the measurement setup is shown in figure 5.13 and figure 5.14 separately. Since the transmitter has two outputs, one is for clock signal and the other is for data signal. The clock signal is droved by the PLL output. The output for the PLL is shown in figure 5.15 at 390 MHz. In figure 5.16 the difference between single ended output and the differential output is shown.
As expected, the differential ended output should have better performance than single ended output. Figure 5.17, the measured eye diagram of the transmitter at 930 Mb/s with 30 cm cable. The peak-to-peak jitter is 10.4 %. Figure 5.18, the measured eye diagram of the transmitter at 1.4 Gb/s with 30 cm cable. The peak-to-peak jitter is 16.1 %. Figure 5.19, the measured eye diagram of the transmitter at 1.8 Gb/s with 30 cm cable. The peak-to-peak jitter is 17.1 %. Figure 5.20, the measured eye diagram of the transmitter at 2 Gb/s with 30 cm cable. The peak-to-peak jitter is 25 %. Then, the cable length is increased to 70 cm. The measurement result is as below. Figure 5.21, the measured eye diagram of the transmitter at 930 Mb/s with 70 cm cable. The peak-to-peak jitter is 15.2 %. Figure 5.22, The measured eye diagram of the transmitter at 1.4 Gb/s with 70 cm cable. The peak-to-peak jitter is 18.9 %. Figure 5.23, The measured eye diagram of the transmitter at 1.8 Gb/s with 70 cm cable. The peak-to-peak jitter is 24.1 %. Figure 5.24, The measured eye diagram of the transmitter at 2 Gb/s with 70 cm cable. The peak-to-peak jitter is 36 .4%. Besides, the measurement for the other quadrants is shown in figure 5.25, 5.26 and 5.27. The operating speed is 1.4 Gb/s. As we can see, these blocks have similar results.
However, the 4th quadrant is biased by external pin. The voltage level is set to 0.7 V, according to the simulation value. As we can see, the output voltage swing is smaller,
which is mainly because process deviation. This may prove that the employment of the self-bias technique is appropriate. The measurement result for the 2nd tap-out is shown in table 5.2.
Table 5.1 the measurement results for the PLL in the 1st tap-out
Function PLL
Simulation Results
Operate Voltage 3.3 V Charge Pump Current 80 μA Divided by N N = 1 VCO Gain 220 MHz/V
C1 15.5 pF
C2 0.3 pF
R1 7 kΩ
Phase Margin 72 ° Loop Bandwidth 12 MHz Measurement Results
Technology UMC 0.13-μm 1P8M CMOS Output Clock Jitter 83ps @100 MHz
Power 50 mW @ 200 MHz
Table 5.2 the measurement results for the PLL in the 2nd tap-out
Technology UMC 0.13-μm 1P8M CMOS Output Clock Jitter 90 ps @ 200 MHz
Power 46 mW @ 200 MHz
Function Transmitter Measurement Results
Operate Voltage 3.3 V
Power Consumption (1) 125 mW@1.4 Gb/s Power Consumption (2) 162 mW@2 Gb/s Data Rate Target at 1.225 Gb/s
(Measured up to 1.8 Gb/s)
Technology UMC 0.13-μm 1P8M CMOS
Figure 5.1 1st layout for the measurement
Figure 5.2 die photo for the 1st measurement
Figure 5.3 the PCB for the 1st measurement
the measurement setup for 1st measurement Figure 5.4
Figure 5.5 The measured output of the PLL at 100 MHz with package.
Figure 5.6 The measured jitter of the PLL at 100 MHz. The Pk-Pk jitter is about 83ps.
Figure 5.7 The measured output of the PLL at 250 MHz with package.
Figure 5.8 The measured jitter of the PLL at 250 MHz. The Pk-Pk jitter is about 89ps.
Figure 5.9 The layout of the 2nd tap-out
Figre 5.10 Two different kinds of output buffers
Figure 5.11 Two different kinds of PLL with different VCO
Figure 5.12 The die photo for the 2nd tap-out
Figure 5.13 the PCB for the 2nd measurement
Figure 5.14 The measurement setup for 2nd measurement
Figure 5.15 The measured output for the clock signal at 390 MHz
Figure 5.16 The difference between single ended output and differential ended output. The operating speed is about 1.4 Gb/s.
Figure 5.17 The measured eye diagram of the transmitter at 930 Mb/s with 30 cm cable. The peak-to-peak jitter is 10.4 %.
Figure 5.18 The measured eye diagram of the transmitter at 1.4 Gb/s with 30 cm cable. The peak-to-peak jitter is 16.1 %.
Figure 5.19 The measured eye diagram of the transmitter at 1.8 Gb/s with 30 cm cable. The peak-to-peak jitter is 17.1 %.
Figure 5.20 The measured eye diagram of the transmitter at 2 Gb/s with 30 cm cable.
The peak-to-peak jitter is 25 %.
Figure 5.21 The measured eye diagram of the transmitter at 930 Mb/s with 70 cm cable. The peak-to-peak jitter is 15.2 %.
Figure 5.22 The measured eye diagram of the transmitter at 1.4 Gb/s with 70 cm cable. The peak-to-peak jitter is 18.9 %.
Figure 5.23 The measured eye diagram of the transmitter at 1.8 Gb/s with 70 cm cable. The peak-to-peak jitter is 24.1 %.
Figure 5.24 The measured eye diagram of the transmitter at 2 Gb/s with 70 cm cable.
The peak-to-peak jitter is 36 .4%.
Figure 5.25 The measurement result for the 1st quadrant at 1.4 Gb/s
Figure 5.26 The measurement result for the 2nd quadrant at 1.4 Gb/s
Figure 5.27 The measurement result for the 4th quadrant at 1.4 Gb/s
Chapter 6
Conclusion and Future Work
6.1 C
ONCLUSIONSA transmitter that supports LVDS standard is developed and implemented. The transmitter can convert seven parallel signals into one serial signal. The measured data rate can be up to 1.8 Gb/s, which can support the UXGA resolution of flat panel displays for sure. Besides for this high data rate achievable, the transmitter can also embedded into other system to enhance the performance at lower cost.
The first important building block examined is the PLL. The PLL needs to generate seven phases required for the 7:1 multiplexer to serialize seven parallel data signals into one signal. Therefore the jitter of the PLL should be propagated to the transmitter output as the essential part. Then the transmitter is developed with the PLL and a self-test PRBS. The measurement results are shown in chapter 5. The circuit was implemented in a UMC 0.13μm 1P8M CMOS process with 3.3V device.
6.2 F
UTURE WORKFrom the measurement result, the transmitter can operate properly at 1.8 Gb/s, which verified the function described. There are still many issues need to be improved.
The bandwidth-limited channels effect should be carefully treated for higher data rate.
Techniques such as modulation, equalization, and coding can provide significant improvement in data bandwidth through transmitting more complex symbols instead of simple bits. The power supply noise should be took care more importantly. The jitter of the PLL should be reduced. The power noise and the PLL layout should be
more carefully handled. The bandwidth of the multiplexer should be enhanced to reduce the ISI problem of the transmitter output.
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