CHAPTER 3 DESIGN OF PLL
3.4 THE BUILDING BLOCKS OF PLL
3.4.5 The voltage controlled oscillator (VCO)
In this PLL, a voltage controlled ring oscillator is employed. The oscillator frequency is proportional to the bias voltage. The fundamental building block is shown in the figure 3.19. The voltage controlled delay cell contains a source-coupled pair with symmetric load, which consists of diode-connected NMOS devices. Since low jitter design for PLL is preferred, delay cell, which has low sensitivity of supply noise and substrate interfere, is preferred. The delay cell utilized here can improve the performance under noisy condition.
Also, the noise characteristic of VCO has been studied. For a differential type delay cell, the impact induced by the device electric noise is not necessarily better than single-ended delay cell. Since the device electric noise is not ignorable, the noise in the differential type delay cell may be independent for each half circuit. Hence, larger noise may be appeared.
Besides, the noise in the VCO can not be analyzed accurately as a simple linear-time-invariant system. It has been shown that the noise property in the VCO is a liner-time-variant system. This property can be shown as figure 3.20. The device electric noise is model as a simple impulse. For typical delay cell, the amplitude limiting mechanism will be an important property of the VCO. As shown in the figure
3.20, the noise impulse interferences the VCO at different time. If the noise corrupts the signal at the zero-crossing point, the maximum phase error was introduced in the output signal. However, if the noise interferences the signal at the highest point, the amplitude limiting mechanism will reduce the impact heavily. Hence, the phase error caused by this case will be minimized. Therefore, the time-variant property of VCO is shown clearly. Also, the linear property is proved a valid model even with time-variant characteristic. Besides, from the discussion, the VCO delay cell should be designed to have good symmetric characteristic. The diode connected NMOS device can improve the linearity of the delay cell. Hence the symmetric load utilized here can improve the jitter performance of the VCO.
As we can see, in order to minimize the jitter of the PLL, the VCO delay cell should be well designed. The PMOS source-coupled pair is employed for the consideration of the body effect. The removal of the body effect will reduce the uncertainty from the differential pair. A seven stage VCO is utilized in the PLL. The characteristic of the VCO is shown in figure 3.21. The Kvco is about 250 MHz/V.
The output of the VCO is not full swing and an extra circuit is included. The differential-to-single-ended converter is shown in figure 3.22. The converter is composed by two differential amplifiers, which will amplify the small swing signal at VCO output. Then a inverter is employed to ensure full swing signal. A 50% duty cycle waveform is generated. The differential pair is biased by a simple self-bias circuit, which is shared all over the chip.
Figure 3.1 The topology of this transmitter
Figure 3.2 The basic architecture of PLL with self-bias technique
Figure 3.3 The simplified continuous approximate plot of PLL
Figure 3.4 The relation between open loop frequency and close loop response
Figure 3.5 The mixed-signal model of the PLL
Figure 3.6 Root-locus plot for s-domain and the z-domain
Figure 3.7 The noise in the PLL
Figure 3.8 The block diagram of PFD
Figure 3.9 The state diagram of PFD
Figure 3.10 The characteristic curve of PFD
Figure 3.11 The TSPC DFF
Figure 3.12 The circuit implementation of PFD
Figure 3.13 The characteristic of PFD
Figure 3.14 The circuit of CP
Figure 3.15 The characteristic of the control voltage
Figure 3.16 The loop filter
Figure 3.17 The simplified bias-generate circuit
Figure 3.18 The bias-generate circuit
Figure 3.19 The basic cell of the VCO
Figure 3.20 The linear-time-variant property of the VCO
Figure 3.21 The seven stage VCO
0 50 100 150 200 250 300 350 400 450 500
1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5
Vctrl
o s c ila tio n fre q u e n c y (M H z )
Figure 3.22 The simulated characteristic of VCO
Figure 3.23 The differential-to-single-ended converter
Chapter 4
Design of Transmitter
4.1
INTRODUCTIONThis chapter is devoted to the design of the transmitter. The purpose of the transmitter is to signaling the electric message outside the chip. As process technologies continue to scale down, the on-chip data rate moves faster than the off-chip data rate and the interface between systems will become an even more significant bottleneck. Therefore, how to design high-speed I/O interface circuits is an important issue [16]. The basic architecture of transmitter is shown in figure 4.1. For measurement, the PRBS is built inside the chip. The PRBS is tried to simulate the random signal that may be transmitted. Besides, the PLL will adjust the VCO according to the input clock and generate fourteen phase, full swing signals to serialize the seven parallel signals. The driver will be switch by this serialized signal and drive the transmission outside the chip to transfer electric message.
For higher operation frequency, the equalization technique can be employed to enhance the performance [17]. Besides, the LVDS transmitter can support very high speed data rate. Therefore, they can be embedded in the transmitter to have variety applications [18], [19]. The heavy data transmission requirement in the display system can be solved by LVDS solution [20].
4.2 T
HE DRIVERAs shown in figure 4.2, the traditional method, using simple taper buffer as driver and simple inverter as input buffer, is not appropriate for high speed signaling.
For the transmitted signal across the transmission line terminated by MOS gate, the signal reflection will be severe. Besides, for high speed signaling the performance merit is not just the rise/fall time but also timing accuracy. Therefore, severe signal reflection will corrupt the signal quality, which is not acceptable. Besides, the power consumption issue and the electromagnetic interfere are not ignorable in such case.
Therefore, driver with small swing and proper termination is introduced and employed in many applications. For this purpose, there are several types of drivers which are often employed, depending on the application specification. They can be seen in figure 4.3. The first two, (a) and (b), are single ended and the latter two, (c) and (d) is differential ended. As discussed before, the differential ended one is preferred for its noise immunity properties. The driver choused is (d) for the termination scheme used in LVDS is double termination. Since the proposed output buffer is intended for operation in the gigabits-per-second range, the double termination scheme is used and the termination resistors are integrated in the output buffer (RT-T) and in the receiver input buffer (RT-R) [21], [22]. From the LVDS specification, the output DC voltage level should be well controlled. Hence a CMFB (common mode feedback circuit) should be employed to stabilize the DC voltage level. As shown in figure 4.4, the CMFB is done by average the two outputs to extract the DC voltage level [23], [24]. Then, this voltage will be compared with a reference voltage to adjust the current of the output buffer, hence the common mode voltage of outputs. However, the DC voltage level is extracted by two large resistors, which should not disturber the output. Hence, these two large resistors will consume large die area. For this reason, the other kind of output buffer is designed. As shown in figure 4.5, the output buffer with CMFB but not resistors is proposed. This is done by utilizing two equal-sized differential amplifiers to adjust the output current of the driver. However, which is not shown in these two figures is the compensation
capacitors and resistors. The driver with CMFB sometimes will be unstable. Therefore, extra care for stabilizing the feedback loop is important. Besides, as shown in this two figures, the Vsb is the bias voltage generated by a simple self-bias circuit. The figure 4.6 is the circuit of the self-bias circuit. Also, the generated by self-bias circuit is fed to PLL. The self-bias technique can reduce the error cause by PVT deviation.
4.3 P
HASE-
LOCKED-
LOOP(PLL)
The PLL is the most critical part of the transmitter. The basic architecture of the PLL is shown in figure 4.7. As discussed before, the PFD, shown in figure 4.8, will compare the phase difference between the input clock and the VCO output, and then generate two signals to switch the charge pump. The control voltage of the VCO is then filtered by loop filter and adjusts the VCO to reduce the phase error. The VCO is shown in figure 4.9 and the chare pump and the loop filter is shown in figure 4.11.
Besides, the PLL may not work properly for the PVT deviation. Hence the self-adjust technique is employed. The bias-gen circuit is shown in figure 4.12.
4.4 P
SEUDO RANDOM BIT SEQUENCE(PRBS)
A pseudo random binary sequence (PRBS) is a test pattern that appears to be random, but is actually a predictable and periodical sequence with a very long interval, depending upon the structure. The period of the PRBS is not always increased with the increased stages. The feedback point is also an important factor. A PRBS is an algorithmically determined bit sequence that has the same statistical characteristics as a truly random sequence and simulates live traffic. The transmitter has a PRBS generator as shown in figure 4.13, it uses D-type flip flops and one OR logic gate to
realize algorithmically determined bit sequence. The circuit implementation of the D-type flip-flop which is utilized in the PRBS is true single-phase clock logic (TSPC) as shown in figure 3.11. The RESET pin in the PRBS is employed to trigger the PRBS in case of the all zero state and the CLK pin is connected to the external pulse generator in order to generate the same frequency pseudo random patterns as the external clock source. When the RESET pin is logic low, the PRBS is forced to enable. After a while, the RESET pin should be changed to logic high in order to keep the patterns correct. Since the PRBS is not really random but a predetermined sequence of ones and zeroes, the data can be captured and checked for errors. The bit length of the PRBS is 28-1. Fig. 5.6 shows the simulated output signals of the seven PRBS outputs.
4.5 M
ULTIPLEXERFor the serial-link, to serialize the parallel signal channels into a single signal is the basic principle. The general multiplexer is shown in figure 4.15. Also, the timing diagram of the multiplexer is shown in figure 4.16. However, there are some drawbacks in this configuration. The serial connected NMOS switched by different phase clocks will induce a data dependant jitter, which is always referred as ISI. The ISI stands for inter-symbol interference. Charge-sharing and the memory will cause this multiplexer failed when operating at high frequency. Besides, for the purpose of high speed operation, the serial connected NMOS should be large devices. Or the multiplexer will not suitable for high speed operation.
The improved multiplexer is shown in figure 4.17. The ISI problem should be less severe for this configuration.
4.6 R
ETIMING THE DATAFor serializing multiple parallel signals, the transition of signals should be avoided. This problem can be shown as below. The configuration without synchronization is shown in figure 4.18. The CLK signal will set the timing of the internal digital circuit and the PLL will generate seven signals with equal phase separation. These signals with different phase will be employed to serialize the data.
As shown in figure 4.19, the phase of PH0 and the digital signals should be approximately the same as the CLK signal. Nevertheless, PH0 and PH3 will set the bit time of D0 in the serialized signal. Therefore, there may not be enough time left for D0 to switch the multiplexer. Hence, the performance of the whole transmitter will be corrupted. For the same reason, the D6 may also has the same problem, which is shown in the figure 4.20.
In this case, the technique of synchronization is utilized. The configuration is shown in figure 4.21. The main idea of synchronization is to put the transition edge out of the sampling pulse period. For this purpose, at least two DFF must insert into the path. However, the sequence of the data will not be in order. Besides, the PLL may not be exactly in phase with CLK, and that will introduce another ambiguity into the sterilization process. With seven DFF switched by different phase signals, the data sequence still will not in order. Therefore, the synchronization scenario as figure 4.22 is shown. The data will be retimed to the output of PLL, which will actually determine the real timing of the data bits. Then, the extra DFF is inserted to serialize the data in order. The data sequence after synchronization is shown in figure 4.23
Figure 4.1 The basic architecture of the transmitter
Figure 4.2 The traditional method of signaling
Figure 4.3 Several types of output drivers
Figure 4.4 The 1st output buffer with CMFB
Figure 4.5 The 2nd output buffer with CMFB
Figure 4.6 The self-bias circuit
Figure 4.7 The basic architecture of PLL
Figure 4.8 The circuit blocks of the PFD
Figure 4.9 The VCO
Figure 4.10 The charge pump and loop filter
Figure 4.12 The bias-gen circuit
Figure 4.13 The PRBS
Figure 4.14 The simulation result of the PRBS
Figure 4.15 The multiplexer
Figure 4.16 The timing diagram of the multiplexer
Figure 4.17 The improved multiplexer
Figure 4.18 The circuit blocks of the non-synchronization configuration
Figure 4.19 The timing diagram for non-synchronization configuration
Figure 4.20 The timing diagram for configuration without synchronization
Figure 4.21 The configuration with synchronization
Figure 4.22 The scenario of synchronization
Figure 4.23 The timing diagram for configuration with synchronization
Chapter 5
Measurement Results
5.1 I
NTRODUCTIONThis measurement result is shown in this chapter. Two measurement results are described. The first one is the PLL and the second one is transmitter.
5.2 M
EASUEMENT FOR THE1
ST TAP-
OUTThe 1st tap-out is mainly a PLL. The layout of the PLL is in figure 5.1. The PLL output is droved by LVDS transmitter. The die photo is shown in figure 5.2. Also, PCB for measurement is shown in figure 5.3. The chip is packaged and large decouple capacitor is employed to reduce the supply noise. In figure 5.4, the measurement setup is shown. HP 8131A is used as a function generator. TEK. DSA 601A is the oscilloscope. As shown in figure 5.5, the measured output of the transmitter is shown.
The operating frequency is 100 MHz. The Pk-Pk jitter is about 83ps at 100 MHz, which is shown in figure 5.6. In figure 5.7, the measurement at 250 MHz is shown.
Also the Pk-Pk jitter is about 89ps in the figure 5.8. The measurement results is concluded in table 5.1.
5.3 M
EASUEMENT FOR THE2
ND TAP-
OUTAs described before, the second measurement is the transmitter. The layout of the transmitter is shown in figure 5.9. There two kinds of output buffers and PLL with
slightly difference. They are shown in figure 5.10 and figure 5.11. The output buffers are different in the CMFB and the PLL is different in the VCO. The third quadrant is the main blocks for this measurement. However, measurement for the rest will be shown. In figure 5.12, the die photo is shown. The PCB and the measurement setup is shown in figure 5.13 and figure 5.14 separately. Since the transmitter has two outputs, one is for clock signal and the other is for data signal. The clock signal is droved by the PLL output. The output for the PLL is shown in figure 5.15 at 390 MHz. In figure 5.16 the difference between single ended output and the differential output is shown.
As expected, the differential ended output should have better performance than single ended output. Figure 5.17, the measured eye diagram of the transmitter at 930 Mb/s with 30 cm cable. The peak-to-peak jitter is 10.4 %. Figure 5.18, the measured eye diagram of the transmitter at 1.4 Gb/s with 30 cm cable. The peak-to-peak jitter is 16.1 %. Figure 5.19, the measured eye diagram of the transmitter at 1.8 Gb/s with 30 cm cable. The peak-to-peak jitter is 17.1 %. Figure 5.20, the measured eye diagram of the transmitter at 2 Gb/s with 30 cm cable. The peak-to-peak jitter is 25 %. Then, the cable length is increased to 70 cm. The measurement result is as below. Figure 5.21, the measured eye diagram of the transmitter at 930 Mb/s with 70 cm cable. The peak-to-peak jitter is 15.2 %. Figure 5.22, The measured eye diagram of the transmitter at 1.4 Gb/s with 70 cm cable. The peak-to-peak jitter is 18.9 %. Figure 5.23, The measured eye diagram of the transmitter at 1.8 Gb/s with 70 cm cable. The peak-to-peak jitter is 24.1 %. Figure 5.24, The measured eye diagram of the transmitter at 2 Gb/s with 70 cm cable. The peak-to-peak jitter is 36 .4%. Besides, the measurement for the other quadrants is shown in figure 5.25, 5.26 and 5.27. The operating speed is 1.4 Gb/s. As we can see, these blocks have similar results.
However, the 4th quadrant is biased by external pin. The voltage level is set to 0.7 V, according to the simulation value. As we can see, the output voltage swing is smaller,
which is mainly because process deviation. This may prove that the employment of the self-bias technique is appropriate. The measurement result for the 2nd tap-out is shown in table 5.2.
Table 5.1 the measurement results for the PLL in the 1st tap-out
Function PLL
Simulation Results
Operate Voltage 3.3 V Charge Pump Current 80 μA Divided by N N = 1 VCO Gain 220 MHz/V
C1 15.5 pF
C2 0.3 pF
R1 7 kΩ
Phase Margin 72 ° Loop Bandwidth 12 MHz Measurement Results
Technology UMC 0.13-μm 1P8M CMOS Output Clock Jitter 83ps @100 MHz
Power 50 mW @ 200 MHz
Table 5.2 the measurement results for the PLL in the 2nd tap-out
Technology UMC 0.13-μm 1P8M CMOS Output Clock Jitter 90 ps @ 200 MHz
Power 46 mW @ 200 MHz
Function Transmitter Measurement Results
Operate Voltage 3.3 V
Power Consumption (1) 125 mW@1.4 Gb/s Power Consumption (2) 162 mW@2 Gb/s Data Rate Target at 1.225 Gb/s
(Measured up to 1.8 Gb/s)
Technology UMC 0.13-μm 1P8M CMOS
Figure 5.1 1st layout for the measurement
Figure 5.2 die photo for the 1st measurement
Figure 5.3 the PCB for the 1st measurement
the measurement setup for 1st measurement Figure 5.4
Figure 5.5 The measured output of the PLL at 100 MHz with package.
Figure 5.6 The measured jitter of the PLL at 100 MHz. The Pk-Pk jitter is about 83ps.
Figure 5.7 The measured output of the PLL at 250 MHz with package.
Figure 5.8 The measured jitter of the PLL at 250 MHz. The Pk-Pk jitter is about 89ps.
Figure 5.9 The layout of the 2nd tap-out
Figre 5.10 Two different kinds of output buffers
Figure 5.11 Two different kinds of PLL with different VCO
Figure 5.12 The die photo for the 2nd tap-out
Figure 5.13 the PCB for the 2nd measurement
Figure 5.14 The measurement setup for 2nd measurement
Figure 5.15 The measured output for the clock signal at 390 MHz
Figure 5.16 The difference between single ended output and differential ended output. The operating speed is about 1.4 Gb/s.
Figure 5.17 The measured eye diagram of the transmitter at 930 Mb/s with 30 cm cable. The peak-to-peak jitter is 10.4 %.
Figure 5.18 The measured eye diagram of the transmitter at 1.4 Gb/s with 30 cm cable. The peak-to-peak jitter is 16.1 %.
Figure 5.19 The measured eye diagram of the transmitter at 1.8 Gb/s with 30 cm cable. The peak-to-peak jitter is 17.1 %.
Figure 5.20 The measured eye diagram of the transmitter at 2 Gb/s with 30 cm cable.
The peak-to-peak jitter is 25 %.
Figure 5.21 The measured eye diagram of the transmitter at 930 Mb/s with 70 cm cable. The peak-to-peak jitter is 15.2 %.
Figure 5.21 The measured eye diagram of the transmitter at 930 Mb/s with 70 cm cable. The peak-to-peak jitter is 15.2 %.