The power efficiency optimization unit controls the clock frequency of variable clock generator and optimizes the power efficiency of 1V generator according to the loading condition. When the loading of 1V generator is changed, the transfer power efficiency will changed if the supply clock frequency is fixed.
Generally, the heavy loading condition will need high frequency clock to achieve high transfer power efficiency; the light loading condition will need low frequency clock to achieve high transfer power efficiency. To remain high transfer power efficiency through different loading condition, it needs a detecting mechanism to decide the loading condition. In the power efficiency optimization
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unit the voltage detector is used as to decide the loading condition.
Fig 5.4 shows the architecture of power efficiency optimization unit.
The voltage detector detects the output voltage of 1V generator to decide the loading condition. When loading increase to heavy, the output voltage of 1V generator will decrease, vice versa. In the solar cell power management system, the power issue is the main concern. The complicated detection and operation is not suite in this system since the power overhead is too much. Simple and efficient system is desire. The voltage detector in the power optimization unit is a one bit detector. It detect the output voltage of 1V generator is up or below to the designed voltage level. The detecting flag will generate to present these two conditions.
There are two proposed voltage generators. The first one is the oscillating voltage detector. The second one is the bias voltage detector. The following part will discuss this two voltage detectors, both two voltage detectors had been simulated with system to verify the performance.
The oscillating voltage detector is first designed with the feature that no bias voltage is needed. Fig 5.5 shows the oscillating voltage detector.
1V Generator
Fig 5.4 The architecture of power efficiency optimization unit
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The oscillating voltage detector consist of an oscillator, the power supply of the oscillator is the output of 1V generator. When the output of 1V generator decrease, the output frequency of the oscillator also decreases, and vice versa.
The output of oscillator is connected to the charge-detecting line (CDL) as present in chapter 3. The CDL will capture the charge condition and generate the detecting Flag. The CDL is designed to measure the specify frequency condition. When the output voltage of 1V generator is decrease, the output frequency of the oscillator is decrease, and the period increase. In the positive phase of the output clock, the CDL start to charge and the D flip-flop will capture the output node of inverter at the falling edge of oscillator output. The lower the output voltage of 1V generator is, the longer the charge time will be. If the output voltage of 1V generator is lower than the threshold voltage we decided, the long charge time will make the capacitor node over the inverter threshold voltage and the CDL will capture the “LOW” detecting flag. Similarly the high output voltage of 1V generator will increase the frequency and decrease the period of oscillator, this will shorten the charge time and the CDL will capture the “HIGH” detecting flag to represent high output voltage of 1V generator.
The detecting point is defined as below; when the voltage of 1V generator’s output is over the detecting point, the voltage generator will capture the “HIGH”. When the voltage of 1V generator’s output is below the detecting point, the voltage generator will capture the “LOW”. The detecting point is the detecting threshold point of the voltage detector, and it can be set arbitrary by change the capacitor sizes. Fig 5.6 shows the detecting point of oscillating voltage detector versus different temperature conditions.
Fig 5.5 The oscillating voltage detector
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Fig 5.6 The detecting point of oscillating voltage detector versus different temperature conditions.
Although the oscillating voltage detector can detect voltage but the power consumption is large. The oscillator is a power consuming component, and it consumes the output power of 1V generator, this will reduce power efficiency. To reduce power consumption and make voltage detector consumes less output power of 1V generator, the bias voltage detector is designed.
Fig 5.7 shows the bias voltage detector. The operation is describe as follow;
when the output voltage of 1V generator decrease, vd will increase and it will be compare to the vref. The vref is generated from the reference voltage generator circuit. The compare result generates the detecting flag. The detecting point of bias voltage detector can be adjusted by the vref and the N,PMOS of lower part of Fig 5.7. The most improvement of bias voltage detector is the power consumption is reduced and it consumes very low power of the output of 1V generator, since the output of 1vV generator is connected to the gate of NMOS.
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The power efficiency optimization unit also contain counter, it will count up or down according to the voltage detecting flag. In the design 5 bits counter was used. The binary words of counter will send to bias circuit of clock system to control the output frequency of clock. The power efficiency optimization unit can thus detecting the loading condition through the output voltage of 1V implemented in UMC 90nm CMOS technology model. The simulation of power efficiency optimization unit has been done to compare with constant clock
Fig 5.7 The bias voltage detector