The power efficiency optimization unit also contain counter, it will count up or down according to the voltage detecting flag. In the design 5 bits counter was used. The binary words of counter will send to bias circuit of clock system to control the output frequency of clock. The power efficiency optimization unit can thus detecting the loading condition through the output voltage of 1V implemented in UMC 90nm CMOS technology model. The simulation of power efficiency optimization unit has been done to compare with constant clock
Fig 5.7 The bias voltage detector
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Fig 5.8 shows the power efficiency measurement of the 1V generator.
The power efficiency of 1V generator is measured as
(Power pumpout) / ((Clk Power) + (Power pumpin)) * %
The constant clock cases are simply cut off the voltage detector feedback control, and fix the clock frequency supply to 1V generator.
Fig 5.9 shows the power efficiency comparison of the dynamic detection of the power efficiency optimization unit to constant clock frequency supply using oscillating voltage detector. The detecting point is set to 900mV. As we can see the dynamic detection of the power efficiency optimization unit has better power efficiency compare to two constant clock frequencies supply 66MHz and 180MHz. When the load current is low, the voltage detector sent the flag which represent the output voltage of 1V generator is high enough, thus it’s will decrease the clock frequency to the lowest clock frequency. The dynamic detection can have better power efficiency over 66MHz because at this region the dynamic detection operates at frequency below 66MHz. When the loading increase the flag will send to clock system to increase clock frequency and handle the system operation with high loading.
Fig 5.8 The power efficiency measurement of the 1V generator
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Fig 5.10 shows the power efficiency comparison of the dynamic detection of the power efficiency optimization unit to constant clock frequency supply using bias voltage detector. The detecting point is set to 900mV. The dynamic detection of power efficiency optimization unit shows the better power efficiency, and compare to Fig 5.9 we can see that the power efficiency has been improved and the maximum allowable load current also increase. This is because the bias voltage detector consumes less power of 1V generator’s output.
0 . 0 0 % 1 0 . 0 0 % 2 0 . 0 0 % 3 0 . 0 0 % 4 0 . 0 0 % 5 0 . 0 0 % 6 0 . 0 0 %
0 30 60 90 120
150 180
210 240
l o a d c u r r e n t ( u A )
efficiency (%) 1 8 0 M H z
6 6 M H z
D y n a m ic d e t e c t io n
Fig 5.9 The power efficiency of the 1V generator (oscillating voltage detector)
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Consider the PV variation impact to the solar cell power management, we simulated it to verify. In this simulation the supply current of PV cell is varying from 4mA to 0mA. The result is shown in Fig. 5.11. The PV cell outputs zero current in 10us. The first row is output voltage of PV cell. It varies from 840mV to 177mV. The PV cell drains a little current from battery. The second row is output voltage of voltage regulator. It varies from 592mV to 482mV. The third row is 1V generator. It varies from 1.11V to 0.9V. The fourth row is -0.5V generator. It varies from -547mV to -440mV. In the simulation it also can be seen that when the PV cell voltage is too low, the solar cell power management switch the power supply from the PV cell to the battery, and keep the system to work.
Fig 5.10 The power efficiency of the 1V generator (bias voltage detector)
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The difference of power management system without CU and with CU is shown in Fig 5.12. In this simulation, the PV cell is set to output zero current and the power management system is supplied by battery.
If the power management system without control unit that is the PV cell is connected to voltage regulator, the output current of battery is 961uA in 30ns.
With the control unit, the output current of battery is reduced to 200uA in 30ns.
The simulation result shows that with CU, the power consumption of battery will be reduced 80% compare to power management system without CU.
This will increase the using time of battery.
Fig 5.11 The three different output voltage with variation of current from PV cell
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The layout view of the solar cell power management system is shown in Fig 5.13. The specification of power management system is summarized in TABLE III.
O ut put c ur re nt o f ba tte ry ( A )
Without CU With CU
Time
Fig 5.12 Comparison of power management system with CU and without CU
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TABLE III
POWER MANAGEMENT SYSTEM FOR SOLAR ENERGY HARVESTING
Technology UMC 90nm CMOS Technology Output current of
PV cell
4mA~0mA Output voltage of
PV cell
840mV~177mV Output power of
PV cell
2.3mW~0mW 0.5V output 592mV~482mV
1V output 1.11V~0.9V -0.5V output -547mV~-440mV Maximum total power
efficiency
69%
Fig 5.13 The layout view of solar cell power management system
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An efficient power management system for solar energy harvesting applications is implemented in UMC 90nm CMOS technology. The output current of PV cell varies from 4mA to 0mA and its output voltage varies from 840mV~177mV. The power management system outputs voltage of 0.5V, 1V and -0.5V to loading circuitry. The 0.5V output is vary from 592mV~482mV. The 1V output is vary from 1.11V~0.9V. The -0.5V output is vary from -547mV~
-440mV. The power efficiency optimization unit is designed and applied to the 1V generator to make the transfer power more efficient when the loading is varied. With control unit and power efficiency optimization unit, the battery supplies energy efficiently and the power consumption is down to one fifth (20%). The maximum total power efficiency is 69%.
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