Thesis Content - 具有高介電質閘極氧化層(二氧化鉿、氧化鑭)之三五族金氧半電容其電性提升之研究

Chapter 1 Introduction

1.2 Thesis Content

This thesis focuses on the study on the performance improvement of InXGa1-XAs metal-oxide-semiconductor capacitors (MOS-capacitors).

In chapter 2, the overview includes the basic operating mechanism of MOS-capacitors, and the performance of high-κ dielectrics and III-V high carrier-mobility channels are described. The detailed fabricating processes of the InXGa1-XAs MOS-capacitors are introduced in chapter 3. In chapter 4, the fundamentals of electrical characteristics of devices are described.

The experimental results and discussions are presented in chapter 5 and are divided into three parts. The first part discusses the effect of different post deposition annealing (PDA) temperatures on the electrical characteristics and the surface qualities of the HfO2/n-InAs MOS-capacitors, the results are also compared to the Al2O3 capacitors. Due to the strong interaction between high-κ and III-V materials, high dielectric constant rare-earth oxides (REOs) are difficult to be used as gate dielectrics on III-V MOS-devices. Thus, inserting a thin HfO2 interlayer (IL) between the rare-earth oxide and the III-V channel was tried and the results are discussed in the second part. The improvement of device performance by using the REO/HfO2 bilayer gate dielectrics is also demonstrated. In the third part of chapter 5, the effects of thermal treatment of two-steps annealing process on the HfO2/p-In0.7Ga0.3As MOS-capacitors performance are studied. Finally, the conclusion of the thesis is given in chapter 6.

Fig. 1-1 The trend of transistor technology

Table 1-1 & Fig. 1-2 Channel materials properties Beyond Si

Candidates

Adopted from Robert Chau, Intel

Chapter 2 Overview of Metal-Oxide-Semiconductor Capacitors

2.1 The Theory of MOS-Capacitors [2-1]

Metal-Oxide-Semiconductor field-effect transistors (MOSFETs) are the most important devices which were used in digital integrated circuit applications today. In general, the major core of MOSFETs is Metal-Oxide-Semiconductor capacitors (MOSCAPs) which determine the device performance.

As shown in Fig. 2-1, a basic MOS-capacitor structure consists of, from bottom to top, the back side metal, the semiconductor substrate, a thin oxide layer, and the gate metal. Based on the type of the substrate, p-type or n-type, MOS-capacitors can be divided into two categories.

The main operation conditions of MOS-capacitors include accumulation, depletion, and inversion.

Fig. 2-1 Basic metal-oxide-semiconductor capacitor structure

2.1.1 MOS-Capacitor with P-type Substrate

Fig. 2-2 shows the band diagram of a MOS-capacitor with the p-type substrate. Under a negative gate voltage, the valence band at the oxide/semiconductor interface bent upward and could be close to the Fermi level, and it means that there is hole-accumulation at the semiconductor surface as shown in Fig. 2-2(a).

Under a small positive gate voltage, conduction band and intrinsic Fermi level bent downward and could be close to the Fermi level as shown in Fig.

2-2(b), and there is a depletion region occurs at the semiconductor surface. The depletion region expands with the increase of positive gate voltage.

As a much larger positive gate voltage is applied, the band bent even more as shown in Fig. 2-2(c). The intrinsic Fermi level at the interface is now lower than the Fermi level, so that it is n-type like at the oxide/semiconductor interface, which means the positive gate voltage starts to induce electrons at the interface.

In this case, the amount of minority carriers (electrons) is greater than that of majority carriers (holes) leading to the formation of an inversion layer.

By applying a high enough positive gate voltage, the carriers on the p-type substrate surface are inverted from p (holes) to n (electrons), and it is called the NMOS-capacitors.

(a) Accumulation

(b) Depletion

Fig. 2-2 Band diagram of a MOS-capacitor with a p-type substrate

2.1.2 MOS-Capacitor with N-type Substrate

Fig. 2-3 shows the band diagram of a MOS-capacitor with the n-type substrate. Under a positive gate voltage, the conduction band at the oxide/semiconductor interface bent downward and could be close to the Fermi level, and it means that there is electron-accumulation at the semiconductor surface as shown in Fig. 2-3(a).

Under a small negative gate voltage, valence band and intrinsic Fermi level bent upward and could be close to the Fermi level as shown in Fig. 2-3(b), and there is a depletion region occurs at the semiconductor surface. The depletion region expands with the increase of negative gate voltage.

As a much larger negative gate voltage is applied, the band bent even more as shown in Fig. 2-3(c). The intrinsic Fermi level at the interface is now higher than the Fermi level, so that it is p-type like at the oxide/semiconductor interface, which means the negative gate voltage starts to induce holes at the interface. In this case, the amount of minority carriers (holes) is greater than that of majority carriers (electrons) leading to the formation of an inversion layer.

By applying a high enough negative gate voltage, the carriers on the n-type substrate surface are inverted from n (electrons) to p (holes), and it is called the PMOS-capacitors.

(a) Accumulation

(b) Depletion

Fig. 2-3 Band diagram of a MOS-capacitor with a n-type substrate

2.1.3 MOS-Capacitor Characterization

The C-V measurements are widely used to quantitatively study MOS-capacitors. There are three important factors to evaluate the device performance, including flat-band voltage, hysteresis, and frequency dispersion.

All of these factors are highly related with the quality of dielectric/semiconductor interface, as well as the interface trap density (Dit).

Flat-band Voltage

Flat-band voltage is used to determine the gate voltage at the condition of no bending in the semiconductor energy band diagram, which leads to no charge in the semiconductor, as shown in Fig. 2-4. And it is regarded as the ideal flat-band voltage. However, the real flat-band voltage would shift ΔVFB due to there are trap charges exiting at the dielectric/semiconductor interface.

Fig. 2-4 Band diagram of flat-band condition of a MOS-capacitor [2-1]

Hysteresis

Hysteresis is measured a C-V curve under a certain frequency by sweeping the gate voltage forth and back. The amount of hysteresis is related with the amount of charges trapped by the defects in the gate dielectric, so that it can be used to determine the dielectric quality. The clockwise hysteresis implies the negative charges are trapped；On the other hand, the counterclockwise hysteresis implies the positive charges are trapped. The defects extracted from hysteresis are called as slow trapping states, and the interface traps are fast trapping states.

Frequency Dispersion

Frequency dispersion is the phenomenon of accumulation capacitance varying with different operated frequencies. The origin of frequency dispersion is related to the poor quality of dielectric/semiconductor interface, where there are a large amount of interface traps exiting. The interface traps are frequency dependent, and they would capture and emit charges leading to frequency dispersion of a C-V curve. Seriously, interface traps would cause Fermi level pinning degrading device performance.

2.2 Requirements for Gate Dielectrics

The number of transistors in a chip would be greatly increased following Moore’s law [2-2, 2-3]. Based on the scaling rule proposed by Dr. R. Dennard, scaling down of MOSFETs brings not only integration of transistors but also improvement of device performance. The concept of scaling rule is illustrated in Fig. 2-5 and Table 2-1 [2-4].

Fig. 2-5 Concept of scaling rule

Table 2-1 Scaling down of MOSFETs by a scaling factor of k

Scaled Device Original Device

However, ITRS roadmap predicts the limit of the size of transistors about 22 nm node, which probably leads to a serious gate leakage current due to an ultra-thin gate oxide layer. As shown in Fig. 2-6, the equivalent oxide thickness (EOT) lead to be 1nm after 2010, so it is hard to suppress the gate leakage current by using a sub-1nm SiO2. Thus, semiconductor technology focused on the alternative gate dielectrics with high dielectric constant (κ) compared to SiO2

[2-5]. In the last decade, high-κ gate dielectrics have shown necessary for scaling down the equivalent oxide thickness (EOT) with a physically thicker film and a low gate leakage current, as shown in Fig. 2-7. The relationship between physical thickness of SiO2 and high-κ gate oxides extracted by the same capacitance value (C) is expressed as：

C＝

- ＝

(2-1) where high- is the dielectric constant of high-κ materials, thigh- is the physical thickness of high-κ gate oxides, SiO2 is the dielectric constant of SiO2 (κ＝3.9).

EOT (equivalent oxide thickness) is expressed as：

t

EOT＝

tphy (2-2)

where tphy is the physical thickness of gate oxide materials.

Fig. 2-6 Required physical gate length, equivalent oxide thickness (EOT) and supply voltage for the next 15 years reported on ITRS 2008 update

(a) (b)

Fig. 2-7 Schematic illustration of gate leakage current under the different gate dielectrics of the MOS structure with (a) SiO₂(b) High-κ

2.3 High-κ Gate Materials

The possible candidates of metal oxides to be used as gate dielectric materials are shown in the white squares of Table 2-2. Among these materials, Al2O3 is the most attractive material for the high-κ gate dielectric which has been widely experimented in MOS devices in the last decade [2-6~2-10]. Al2O3

shows the excellent dielectric properties, including a high dielectric constant (κ~9), a large energy band-gap (~9eV), a high breakdown electric field (5-30 MV/cm), high thermal and chemical stability, and its amorphous crystal structure can be used as the gate leakage tunneling barrier.

Table 2-2 Candidates for the metal, oxide of which has possibility to be used as high-κ gate insulator on periodic table

In recent years, the group of Hf-based oxide materials has been gradually emphasized as shown in Fig. 2-8. Due to the eminent dielectric properties, such as the higher dielectric constant compared to Al2O3 (κ~20-25), a large energy band-gap (~6eV), low bulk trap densities and a large band offset (1.3-1.5eV).

Hf-based oxides were adopted as the gate dielectric for the 45nm transistors in 2007 by Intel [2-11].

On the other hand, rare-earth oxides (REOs) are also regarded as the selection for the next generation of technology nodes. Among rare-earth oxides, La2O3 is considered one of the most attractive materials due to its promising properties such as a high dielectric constant ( ~27), a large band gap (~6eV) and conduction-band offset (2.3eV), a high breakdown electric field (>13MV/cm), and a low leakage current. Also, CeO2 exhibits a wide dielectric constant range ( ~25-52) based on its crystal structure, but the smaller band gap and conduction-band offset can cause a larger leakage current [2-12].

Fig. 2-8 Recent high-κ reports had been published in VLSI and IEDM symposium

2.4 III-V Compound Semiconductors as Channel Materials

Besides the gate oxide limitation, it is also difficult to continually improve the transistor performance as the device dimension decreases, which gives rise to some serious problems, such as short-channel effect, velocity saturation of channel carrier, large series resistance of source/drain layers, increase of source/drain leakage current [2-13]. Thus, conventional Si MOS-devices are confronted by the scaling limit for the gate length under 15~20nm.

According to the drain current equation of MOSFETs, Id =

μ

eff

(V

-V

)V

d, it can be also the alternative method to improve device performance without scaling down by increasing effective carrier-mobility. In fact, enhancing carrier mobility has already been investigated by means of strained channel [2-14~2-16]. The most effective method is replacing Si with high carrier mobility materials as the channel layer, thus, high carrier-mobility materials attracted a lot of attention recently. Especially, III-V compound semiconductors have been extensively studied due to the much higher carrier mobility compared to Si as listed in Table 2-3. Therefore, performance improvement of MOS-devices with a high carrier-mobility channel is expected.

Table 2-3 Electron and hole mobility of various semiconductors

Si Ge GaAs InP In

Ga

1-X

As

electron mob.

μ_e (cm²/Vs) 1350 3900 8500 5400 8000~30000 hole mob.

μ_h (cm²/Vs) 480 1900 400 200 400~600

Chapter 3 Fabrication of III-V Metal-Oxide-Semiconductor Capacitors

3.1 Experimental Process Flow

Fig. 3-1 summaries the fabrication flow of InXGa1-XAs MOS-capacitors. The first step was wafer cleaning by using ACE and IPA to remove the contamination on the wafer surface. After that, surface treatment was performed before the gate dielectric deposition. For the surface treatment, dilute HF solution was first used to eliminate the native oxide on the wafer surface, and then treated with (NH4)SX solution for 20～30 minutes at room temperature. A passivation layer which was favorable for the gate dielectrics deposition would be formed on the wafer surface. After the surface treatment, high-κ gate materials were deposited by electron-beam deposition in an ultra high vacuum chamber at a pressure of 10^-8 Pa, and then annealed by the RTA system to improve the quality of oxide/semiconductor interface. Finally, tungsten (W) was chosen as the gate metal and the backside ohmic metal used was gold (Au), which were deposited by the E-gun evaporation system.

Fig. 3-1 Fabrication process flow of III-V MOS-capacitors

3.2 Electron Beam Epitaxy (MBE) [3-1]

The high-κ gate dielectrics were deposited under an ultra-high vacuum by the MBE system as shown in Fig. 3-2. The background pressure in the chamber was in the 10^-8 Pa range and was in the 10^-7 Pa range during the deposition process. In the chamber, the sintered high-κ target was the evaporation source and was heated up by irradiating with electron beam accelerated to 5keV. Then, an ultra-thin high-κ film was deposited on the substrate. Physical thickness of the film was monitored by a film thickness monitor using the crystal oscillator.

The temperature of the substrate was controlled by a substrate heater and was measured by a thermocouple.

Fig. 3-2 Schematic of the MBE chamber for the deposition of high-κ gate materials

Chapter 4 Fundamentals of Electrical Characteristics for III-V MOS-Capacitors

4.1 Capacitance-Voltage (C-V) Characteristics [4-1]

C-V characteristic measurements were carried out under various frequencies

by precision LCR meter. The energy band diagram of a MOS-capacitor on a p-type substrate is shown in Fig. 4-1. The intrinsic energy level Ei or potential Φ in the neutral part of device is taken as the zero reference. The surface potential,

Φ

S, is measured from the reference level. The capacitance is defined as：

C =

^(4-1)

where QG

and V

are the gate charge and the gate voltage, respectively. It is the

change of charge due to a change of voltage and is most commonly given in units of farad/units area.

During capacitance measurements, a small-signal ac voltage is applied to the device. The resulting charge variation gives rise to the capacitance. Looking at a MOS capacitor from the gate, C = dQG

/ dV

G, where QG

and V

are the gate

charge and the gate voltage. Since the total charge in the device must be zero, assuming no oxide charge, QG

= − (Q

+ Q

it), where QS

is the semiconductor

charge, and Qit

is the interface charge. The gate voltage is partially dropped

across the oxide and partially across the semiconductor. This gives VG

= V

+

V

+Φ

S, where VFB

is the flatband voltage, V

OX is the oxide voltage, and ΦS

is

the surface potential, allowing Eq. (4-1) to be rewritten as：

The minus sign in Eq. (4-3) cancels in either case. Eq. (4-4) is represented by the equivalent circuit in Fig. 4-2(a). Under negative gate voltages, the surface is heavily accumulated and Qp dominates. Cp is very high approaching a short circuit. Hence, the four capacitances are shorted as shown by the heavy line in Fig. 4-2(b) and the overall capacitance is Cox. For small positive gate voltages, the surface is depleted and the space-charge region charge density, Qb = qNAW, dominates. Trapped interface charge capacitance also contributes. The total capacitance is the combination of Cox in series with Cb in parallel with Cit as shown in Fig. 4-2(c). In weak inversion Cn begins to appear. For strong inversion, Cn dominates because Qn is very high. If Qn is able to follow the applied ac voltage, the low-frequency equivalent circuit (Fig. 4-2(d)) becomes

the oxide capacitance again. When the inversion charge is unable to follow the ac voltage, the circuit in Fig. 4-2(e) applies in inversion, with Cb = Ks εo / Winv

with Winv the inversion space-charge region width.

Fig. 4-1 Cross-section and band diagram of a MOS-capacitor

Fig. 4-2 Capacitances of MOS-capacitors under the different bias conditions

4.2 Leakage Current Density-Voltage (J-V) Characteristics

To reduce the power consumption, it is essential to suppress the gate leakage current of MOS devices as small as possible. J-V measurement is used to estimate the leakage current density. The measurement started at 0 V and sweep towards accumulation region until breakdown occurs.

4.3 Interface Trap Density (D

_it

) by Conductance Method

The conductance method, proposed by Nicoliian and Goetzberger in 1967, is one of the most sensitive methods to determine Dit

[4-2]. The technique is based

on measuring the equivalent parallel conductance Gp

of a MOS capacitor as a

function of bias voltage and frequency. The conductance, representing the loss mechanism due to interface trap capture and emission of carriers, is a measure of the interface trap density.

The simplified equivalent circuit of a MOS-capacitor appropriate for the conductance method is shown in Fig. 4-3(a). It consists of the oxide capacitance

C

ox, the semiconductor capacitance Cs, and the interface trap capacitance Cit. The capture-emission of carriers by Dit

is a lossy process, represented by the

resistance Rit. It is convenient to replace the circuit of Fig. 4-3(a) by that in Fig.

4-3(b), where Cp and Gp

are given by：

C

p = Cs＋

1＋ )²

^(4-5)

1＋ )² (4-6)

where Cit

= q

D

it, = 2πf (f = measurement frequency) and it

= R

C

it, the interface trap time constant, given by it

= [υ

thσp

N

Aexp(-qφs

/kT)]

^-1. Dividing Gp

by makes Eq. (4-6) symmetrical in it. Equations (4-5) and (4-6) are for interface traps with a single energy level in the band gap. Interface traps at the insulator/semiconductor interface, however, are continuously distributed in energy throughout the semiconductor band gap. Capture and emission occurs primarily by traps located within a few kT/q above and below the Fermi level, leading to a time constant dispersion and giving the normalized conductance as

＋

)

^(4-7)

The conductance is measured as a function of frequency and plotted as Gp

/

versus . Gp

/ has a maximum at = 1/

and at that maximum D

= 2G

/q .

For Eq. (4-7), one can find ~ 2/ it

and D

= 2.5G

/qω at the maximum. Hence,

one can determine Dit from the maximum Gp

/ and determine

from at the

peak conductance location on the -axis.

An approximate expression of the interface trap density in terms if the measured maximum conductance is

D

it = 2 5

)

max (4-8)

Capacitance meters generally assumed the device consist of the parallel

C

-G

combination in Fig. 4-3(c). A circuit comparison of Fig. 4-3(b) to 4-3(c)

gives Gp

/ in terms of the measured capacitance C

m, the oxide capacitance, and the measured conductance Gm

as

＋ ² － )²

^(4-9)

assuming negligible series resistance. The conductance measurement must be

carried out over wide frequency range. The portion of the band gap probed by conductance measurements is typically from flat-band to weak inversion. The measured frequency should be accurately determined and the signal amplitude should be kept at around 50mV or less to prevent harmonics of the signal frequency giving rise to spurious conductance.

Fig. 4-3 Equivalent circuit for conductance measurement (a) MOS-C with interface trap time constant _it = R_itC_it, (b) simplified circuit of (a), (c) measured circuit

Chapter 5 Experimental Results and Discussion

5.1 Study on Electrical Characteristics of HfO

/n-InAs Metal-Oxide-Semiconductor Capacitors with Different Post Deposition Annealing Temperatures

5.1.1 Introduction

For future scaling of complimentary metal-oxide-semiconductor (CMOS) technology in accordance with Moore’s Law, it will require novel solutions such as high-κ dielectrics, metal gates, and high carrier-mobility channels. Recently, III-V metal-oxide-semiconductor field-effect transistors (III-V MOSFETs) have been extensively investigated for future high speed and low power logic applications by using the use of III-V high mobility channels and high-κ gate dielectrics [5-1]. Among III-V materials, InAs has much higher carrier-mobility exhibiting the superior transport property for device performance [5-2~5-4].

Therefore, InAs is an excellent candidate as the channel material for the next generation of CMOS logic circuits. In addition, a high-κ gate dielectric has been used to improve MOS-device performance, including reducing the gate leakage current with a physically thicker gate dielectric thickness, and enhancement of logic characteristics [5-5]. Among high-κ dielectrics, Hf-based dielectrics, especially HfO2, are considered as ideal high-κ materials for the next CMOS generation due to their high dielectric constant (κ~20-25) and high energy

band-gap (~6eV).

Before realization of III-V CMOS utilizing InAs as the channel material, it is essential to obtain the high quality of dielectric/InAs interface with the minimal hysteresis and a low interface trap density (Dit). Thus, the HfO2/n-InAs MOS-capacitors were fabricated and the device performance was evaluated under the different post deposition annealing (PDA) temperatures in this study.

Moreover, the device performance of HfO2/n-InAs MOS-capacitor was also compared with that of Al2O3/n-InAs MOS-capacitor.

5.1.2 Experiment

The structure of the n-InAs MOS-capacitor in this study is as shown in Fig.

5-1-1, and the wafer structure was grown by molecular beam epitaxy (MBE) on

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