III-V Compound Semiconductors as Channel Materials

Chapter 2 Overview of Metal-Oxide-Semiconductor Capacitors

2.4 III-V Compound Semiconductors as Channel Materials

Besides the gate oxide limitation, it is also difficult to continually improve the transistor performance as the device dimension decreases, which gives rise to some serious problems, such as short-channel effect, velocity saturation of channel carrier, large series resistance of source/drain layers, increase of source/drain leakage current [2-13]. Thus, conventional Si MOS-devices are confronted by the scaling limit for the gate length under 15~20nm.

According to the drain current equation of MOSFETs, Id =

μ

eff

(V

-V

)V

d, it can be also the alternative method to improve device performance without scaling down by increasing effective carrier-mobility. In fact, enhancing carrier mobility has already been investigated by means of strained channel [2-14~2-16]. The most effective method is replacing Si with high carrier mobility materials as the channel layer, thus, high carrier-mobility materials attracted a lot of attention recently. Especially, III-V compound semiconductors have been extensively studied due to the much higher carrier mobility compared to Si as listed in Table 2-3. Therefore, performance improvement of MOS-devices with a high carrier-mobility channel is expected.

Table 2-3 Electron and hole mobility of various semiconductors

Si Ge GaAs InP In

Ga

1-X

As

electron mob.

μ_e (cm²/Vs) 1350 3900 8500 5400 8000~30000 hole mob.

μ_h (cm²/Vs) 480 1900 400 200 400~600

Chapter 3 Fabrication of III-V Metal-Oxide-Semiconductor Capacitors

3.1 Experimental Process Flow

Fig. 3-1 summaries the fabrication flow of InXGa1-XAs MOS-capacitors. The first step was wafer cleaning by using ACE and IPA to remove the contamination on the wafer surface. After that, surface treatment was performed before the gate dielectric deposition. For the surface treatment, dilute HF solution was first used to eliminate the native oxide on the wafer surface, and then treated with (NH4)SX solution for 20～30 minutes at room temperature. A passivation layer which was favorable for the gate dielectrics deposition would be formed on the wafer surface. After the surface treatment, high-κ gate materials were deposited by electron-beam deposition in an ultra high vacuum chamber at a pressure of 10^-8 Pa, and then annealed by the RTA system to improve the quality of oxide/semiconductor interface. Finally, tungsten (W) was chosen as the gate metal and the backside ohmic metal used was gold (Au), which were deposited by the E-gun evaporation system.

Fig. 3-1 Fabrication process flow of III-V MOS-capacitors

3.2 Electron Beam Epitaxy (MBE) [3-1]

The high-κ gate dielectrics were deposited under an ultra-high vacuum by the MBE system as shown in Fig. 3-2. The background pressure in the chamber was in the 10^-8 Pa range and was in the 10^-7 Pa range during the deposition process. In the chamber, the sintered high-κ target was the evaporation source and was heated up by irradiating with electron beam accelerated to 5keV. Then, an ultra-thin high-κ film was deposited on the substrate. Physical thickness of the film was monitored by a film thickness monitor using the crystal oscillator.

The temperature of the substrate was controlled by a substrate heater and was measured by a thermocouple.

Fig. 3-2 Schematic of the MBE chamber for the deposition of high-κ gate materials

Chapter 4 Fundamentals of Electrical Characteristics for III-V MOS-Capacitors

4.1 Capacitance-Voltage (C-V) Characteristics [4-1]

C-V characteristic measurements were carried out under various frequencies

by precision LCR meter. The energy band diagram of a MOS-capacitor on a p-type substrate is shown in Fig. 4-1. The intrinsic energy level Ei or potential Φ in the neutral part of device is taken as the zero reference. The surface potential,

Φ

S, is measured from the reference level. The capacitance is defined as：

C =

^(4-1)

where QG

and V

are the gate charge and the gate voltage, respectively. It is the

change of charge due to a change of voltage and is most commonly given in units of farad/units area.

During capacitance measurements, a small-signal ac voltage is applied to the device. The resulting charge variation gives rise to the capacitance. Looking at a MOS capacitor from the gate, C = dQG

/ dV

G, where QG

and V

are the gate

charge and the gate voltage. Since the total charge in the device must be zero, assuming no oxide charge, QG

= − (Q

+ Q

it), where QS

is the semiconductor

charge, and Qit

is the interface charge. The gate voltage is partially dropped

across the oxide and partially across the semiconductor. This gives VG

= V

+

V

+Φ

S, where VFB

is the flatband voltage, V

OX is the oxide voltage, and ΦS

is

the surface potential, allowing Eq. (4-1) to be rewritten as：

The minus sign in Eq. (4-3) cancels in either case. Eq. (4-4) is represented by the equivalent circuit in Fig. 4-2(a). Under negative gate voltages, the surface is heavily accumulated and Qp dominates. Cp is very high approaching a short circuit. Hence, the four capacitances are shorted as shown by the heavy line in Fig. 4-2(b) and the overall capacitance is Cox. For small positive gate voltages, the surface is depleted and the space-charge region charge density, Qb = qNAW, dominates. Trapped interface charge capacitance also contributes. The total capacitance is the combination of Cox in series with Cb in parallel with Cit as shown in Fig. 4-2(c). In weak inversion Cn begins to appear. For strong inversion, Cn dominates because Qn is very high. If Qn is able to follow the applied ac voltage, the low-frequency equivalent circuit (Fig. 4-2(d)) becomes

the oxide capacitance again. When the inversion charge is unable to follow the ac voltage, the circuit in Fig. 4-2(e) applies in inversion, with Cb = Ks εo / Winv

with Winv the inversion space-charge region width.

Fig. 4-1 Cross-section and band diagram of a MOS-capacitor

Fig. 4-2 Capacitances of MOS-capacitors under the different bias conditions

4.2 Leakage Current Density-Voltage (J-V) Characteristics

To reduce the power consumption, it is essential to suppress the gate leakage current of MOS devices as small as possible. J-V measurement is used to estimate the leakage current density. The measurement started at 0 V and sweep towards accumulation region until breakdown occurs.

4.3 Interface Trap Density (D

_it

) by Conductance Method

The conductance method, proposed by Nicoliian and Goetzberger in 1967, is one of the most sensitive methods to determine Dit

[4-2]. The technique is based

on measuring the equivalent parallel conductance Gp

of a MOS capacitor as a

function of bias voltage and frequency. The conductance, representing the loss mechanism due to interface trap capture and emission of carriers, is a measure of the interface trap density.

The simplified equivalent circuit of a MOS-capacitor appropriate for the conductance method is shown in Fig. 4-3(a). It consists of the oxide capacitance

C

ox, the semiconductor capacitance Cs, and the interface trap capacitance Cit. The capture-emission of carriers by Dit

is a lossy process, represented by the

resistance Rit. It is convenient to replace the circuit of Fig. 4-3(a) by that in Fig.

4-3(b), where Cp and Gp

are given by：

C

p = Cs＋

1＋ )²

^(4-5)

1＋ )² (4-6)

where Cit

= q

D

it, = 2πf (f = measurement frequency) and it

= R

C

it, the interface trap time constant, given by it

= [υ

thσp

N

Aexp(-qφs

/kT)]

^-1. Dividing Gp

by makes Eq. (4-6) symmetrical in it. Equations (4-5) and (4-6) are for interface traps with a single energy level in the band gap. Interface traps at the insulator/semiconductor interface, however, are continuously distributed in energy throughout the semiconductor band gap. Capture and emission occurs primarily by traps located within a few kT/q above and below the Fermi level, leading to a time constant dispersion and giving the normalized conductance as

＋

)

^(4-7)

The conductance is measured as a function of frequency and plotted as Gp

/

versus . Gp

/ has a maximum at = 1/

and at that maximum D

= 2G

/q .

For Eq. (4-7), one can find ~ 2/ it

and D

= 2.5G

/qω at the maximum. Hence,

one can determine Dit from the maximum Gp

/ and determine

from at the

peak conductance location on the -axis.

An approximate expression of the interface trap density in terms if the measured maximum conductance is

D

it = 2 5

)

max (4-8)

Capacitance meters generally assumed the device consist of the parallel

C

-G

combination in Fig. 4-3(c). A circuit comparison of Fig. 4-3(b) to 4-3(c)

gives Gp

/ in terms of the measured capacitance C

m, the oxide capacitance, and the measured conductance Gm

as

＋ ² － )²

^(4-9)

assuming negligible series resistance. The conductance measurement must be

carried out over wide frequency range. The portion of the band gap probed by conductance measurements is typically from flat-band to weak inversion. The measured frequency should be accurately determined and the signal amplitude should be kept at around 50mV or less to prevent harmonics of the signal frequency giving rise to spurious conductance.

Fig. 4-3 Equivalent circuit for conductance measurement (a) MOS-C with interface trap time constant _it = R_itC_it, (b) simplified circuit of (a), (c) measured circuit

Chapter 5 Experimental Results and Discussion

5.1 Study on Electrical Characteristics of HfO

/n-InAs Metal-Oxide-Semiconductor Capacitors with Different Post Deposition Annealing Temperatures

5.1.1 Introduction

For future scaling of complimentary metal-oxide-semiconductor (CMOS) technology in accordance with Moore’s Law, it will require novel solutions such as high-κ dielectrics, metal gates, and high carrier-mobility channels. Recently, III-V metal-oxide-semiconductor field-effect transistors (III-V MOSFETs) have been extensively investigated for future high speed and low power logic applications by using the use of III-V high mobility channels and high-κ gate dielectrics [5-1]. Among III-V materials, InAs has much higher carrier-mobility exhibiting the superior transport property for device performance [5-2~5-4].

Therefore, InAs is an excellent candidate as the channel material for the next generation of CMOS logic circuits. In addition, a high-κ gate dielectric has been used to improve MOS-device performance, including reducing the gate leakage current with a physically thicker gate dielectric thickness, and enhancement of logic characteristics [5-5]. Among high-κ dielectrics, Hf-based dielectrics, especially HfO2, are considered as ideal high-κ materials for the next CMOS generation due to their high dielectric constant (κ~20-25) and high energy

band-gap (~6eV).

Before realization of III-V CMOS utilizing InAs as the channel material, it is essential to obtain the high quality of dielectric/InAs interface with the minimal hysteresis and a low interface trap density (Dit). Thus, the HfO2/n-InAs MOS-capacitors were fabricated and the device performance was evaluated under the different post deposition annealing (PDA) temperatures in this study.

Moreover, the device performance of HfO2/n-InAs MOS-capacitor was also compared with that of Al2O3/n-InAs MOS-capacitor.

5.1.2 Experiment

The structure of the n-InAs MOS-capacitor in this study is as shown in Fig.

5-1-1, and the wafer structure was grown by molecular beam epitaxy (MBE) on a 3-in n⁺-InP substrate. The structure layers, from bottom to top, are composed of a 10-nm-thick n-In0.53Ga0.47As (Si：5х10¹⁷cm^-3 ), a 3-nm-thick n-In0.70Ga0.30As (Si：5х10¹⁷cm^-3 ), and a 5-nm-thick n-InAs (Si：5х10¹⁷cm^-3 ).

The wafers were first cleaned in a dilute HF (50%) solution for 3 minutes, and then followed by surface treatment in a (NH4)2SX solution for 30 minutes at room temperature. The cleaned wafers were deposited an HfO2 layer of 15nm at 300^oC by the MBE system. After the gate oxide deposition, the post deposition annealing (PDA) process was performed with the different temperature conditions for 5 minutes, ranging from 400^oC to 550^oC. After the PDA process, tungsten (W) metal contact size: 50μm in diameter) was deposited as the gate metal by the lift-off process and gold (Au) metal was deposited by the sputtering process as the backside ohmic contact.

Gate HfO

₂

5nm n-InAs Si:5х10

¹⁷

cm

^-3

3nm n-In

0.7

Ga

0.3

As

Si:5х10

¹⁷

cm

^-3

10nm n-In

_0.53

Ga

_0.47

As Si:5х10

¹⁷

cm

^-3

n

⁺

-InP

Backside Ohmic

Fig. 5-1-1 Structure of the HfO₂/n-InAs MOS-capacitor

5.1.3 Results and Discussion

Transmission Electron Microscopy (TEM) Analysis

The interface of HfO₂/n-InAs MOS-capacitor was observed by the cross-sectional transmission electron microscopy (TEM) analysis as shown in Fig. 5-1-2(a). Compared to the HfO₂/n-In_0.53Ga_0.47As MOS-capacitor (Fig.

5-1-2(b)) with the similar process conditions, there was less interfacial oxide formed at the HfO₂/n-InAs interface. The interfacial oxide layer at the HfO2/n-In0.53Ga0.47As interface was identified as Ga-oxide [5-6], which was absent at the interface of HfO₂/n-InAs MOS-capacitor as observed in Fig.

5-1-2(a).

(a) HfO₂/InAs (b) HfO₂/In_0.53Ga_0.47As Fig. 5-1-2 TEM images of interface (a) HfO₂/InAs, (b) HfO₂/In_0.53Ga_0.47As

C-V Characteristics

The C-V characteristics of HfO2/n-InAs MOS-capacitors with the different PDA temperatures of 400^oC, 450^oC, 500^oC and 550^oC were shown in Fig. 5-1-3.

The device annealed at 400^oC had the highest capacitance value at the accumulation region among the annealing temperatures in this study and the capacitance value was reduced with the increase of PDA temperature.

Furthermore, there was no clear saturation observed at the inversion region for the capacitor annealed at 400^oC. The phenomenon may be due to a small amount of native oxide existed at the oxide/semiconductor interface. However, as the PDA temperature was increased to 450^oC, the native oxide at the interface was reduced, leading to the obvious saturation at the inversion region.

Fig. 5-1-3 C-V characteristics of the HfO₂/n-InAs MOS-capacitors after PDA at (a) 400^oC (b) 450^oC

Fig. 5-1-3 C-V characteristics of the HfO₂/n-InAs MOS-capacitors after PDA at (c) 500^oC (d) 550^oC

The hysteresis behaviors of HfO2/n-InAs MOS-capacitors at 100 kHz at the different annealing temperatures were investigated by using the bidirectional

C-V sweeps as shown in Fig. 5-1-4. The behavior of hysteresis occurrence

depends on the quality of the high-κ dielectric, it can be seen that the hysteresis voltage decreased with the increase of PDA temperature, which implied the quality of HfO2 film was improved, especially at the PDA temperature of 500^oC (ΔV=-37mV). However, as the PDA temperature approached 550^oC, the hysteresis became worse (ΔV = -288 mV) due to a small amount of indium (In) diffused into HfO2.

The flat-band voltage at 100 kHz shifted to a more negative value with the increase of PDA temperature from 400^oC to 500^oC, 2.15 V (400^oC), 1.32 V (450^oC), 1.11 V (500^oC), which implied that the oxide charges were reduced under a higher PDA temperature. Also, the flat-band voltage shifted to a more positive value of 2.14 V at the PDA temperature of 550^oC due to indium (In) diffusion. Furthermore, the capacitance value at the flat-band condition decreased with increasing annealing temperature.

The interface trap densities (Dit) of HfO2/n-InAs MOS-capacitors at the different PDA temperatures were estimated by the conductance method. It showed that the device at the PDA temperature of 500^oC had the lowest Dit with the value of 2 7х10¹² cm^-2·eV^-1 among all the PDA temperatures studied. The leakage current for the 15nm HfO2/n-InAs MOS-capacitor after 500^oC annealing was less than 1×10^-5A/cm² when the bias voltage was between -3.5 V to 3.5 V.

All of the C-V characteristics mentioned above were listed in Table 5-1-1.

Table 5-1-1 Comparison of electrical characteristics of the HfO₂/n-InAs MOS-capacitors at the different PDA temperatures

PDA temp. (^oC) 400 450 500 550

XPS Analysis

Fig. 5-1-5 showed the XPS spectra of HfO2/n-InAs MOS-capacitors at the different PDA temperatures from 400^oC to 550^oC. There were three values of In3d5/2, InOX, In2O3 and InAs, and two values of As3d, As2O3 and InAs, observed. The native oxide of InAs, which is mainly composed of As2O3, is known to produce a relative poor interface.

According to the XPS results, it was observed that the amount of InOX and As2O3 decreased when the PDA temperature was increased from 400^oC to 450^oC.

As the PDA temperature approached 500^oC, there was no clear As2O3 peak, and the device had the best hysteresis value of ~ 37mV as shown in Fig. 5-1-4.

However, when PDA temperature was increased up to 550^oC, a small amount of indium (In) diffused into HfO2 and both In2O3 and InOX amount increased as observed from the XPS results. And it was the reason that the electrical characteristics of HfO2/n-InAs MOS-capacitor degraded at a PDA temperature over 500^oC.

Fig. 5-1-5 XPS spectra of the HfO₂/n-InAs MOS-capacitors at the different PDA temperatures

Compared to Al2O3/n-InAs MOS-Capacitor

Al2O3 is the most mature high-κ material for III-V MOS-devices and have been investigated as the gate dielectric in recent years. Also, the study of Al2O3/n-InAs MOS-capacitors was already done by Dr. Yun-Chi, Wu before in our group [5-7]. The fabrication process of Al2O3/n-InAs MOS-capacitors was also the same as described in this thesis.

The C-V characteristic of Al2O3/n-InAs MOS-capacitor is shown in Fig.

5-1-6. Compared with the C-V characteristic of HfO2 one at the same operated frequency (f：100 kHz), the MOS-capacitor with HfO2 exhibited the capacitance value of 0.64 (pF/cm²) at the accumulation condition which is higher than that of 0.54 (pF/cm²) of Al2O3 MOS-capacitor. Furthermore, the HfO2/n-InAs MOS-capacitor had the smaller equivalent oxide thickness (EOT). Table 5-1-2 lists the comparison of Al2O3 and HfO2 n-InAs MOS-capacitors.

Fig. 5-1-6 C-V characteristics of the Al₂O₃/n-InAs MOS-capacitor

Table 5-1-2 Comparison of the Al₂O₃ and HfO₂/n-InAs MOS-capacitors κ Eg (eV)

C

Acc (pF/cm²)

The electrical characteristics of HfO₂/n-InAs metal-oxide-semiconductor capacitors with the different post deposition annealing (PDA) temperatures were demonstrated. By the use of InAs as the channel layer, it could avoid the undesired Ga-oxide formation at the dielectric/semiconductor interface compared to the In_0.53Ga_0.47As channel device. Moreover, the quality of HfO₂/ InAs interface was improved with the increase of PDA temperature. The MOS-capacitor after 500^oC PDA annealing demonstrated the lowest interface trap density (Dit) value due to the reduction of native oxide (As2O3), which was verified by the XPS results. Also, the C-V characteristics of device with 500^oC annealing exhibited the best performance such as a lowest hysteresis value, the flat-band voltage shifted to a more negative value, and the smaller frequency dispersion at the accumulation region. However, as the annealing temperature approached 550^oC, a small number of indium (In) atoms diffused into the HfO₂ layer with the increase of InOX and In2O3 formation so that the device performance was degraded. On the other hand, the HfO₂/n-InAs MOS-capacitor had the higher capacitance value and the smaller equivalent oxide thickness (EOT) compared to the device with the Al₂O₃ gate dielectric.

5.2 Performance Improvement of Bilayer High-κ Gate Dielectrics for In

Ga

_1-X

As Metal-Oxide-Semiconductor Capacitors

5.2.1 Introduction

For the CMOS technologies perhaps approach the limit of development by the forecast of Moor’s Law. To extent CMOS technique to 22 nm node and beyond, it requires alternate materials and structures for future devices for logic and low power applications. Recently, researchers have been paying attention to III-V high mobility channel materials, especially high indium (In) content InXGa1-XAs, that potentially provides high carrier transport and drive current with small effective mass [5-8~5-9]. Thus, III-V compound semiconductors are considered as the most attractive alternate channel materials to replace silicon for device performance.

High-κ metal-oxides are also required for III-V MOS-devices. Particularly, HfO2 has been extensively investigated for III-V CMOS applications due to its superior properties, including a high dielectric constant (κ~20-25), a high energy band gap (~6eV) and thermally stable on III-V [5-10~5-13]. In addition, rare-earth oxides (REOs) are also been currently researched as high-κ materials for post-Hafnium oxides due to their promising properties, such as much higher dielectric constant, large energy band-gap and conduction-band offset [5-14].

Among rare-earth oxides, La2O3 is the potential candidate due to its very high dielectric constant (κ~27) [5-15]. However, rare-earth oxides can react with III-V compound semiconductors leading to a poor quality of REO/III-V interface, which degrades the device performance. Therefore, an ultra-thin and thermal stable interlayer (IL) between the III-V high mobility channel and the

RE-gate dielectric is needed for the improvement of the device performance.

In this study, we introduced that HfO2 as the interlayer (IL) between the high indium content InXGa1-XAs channel and the RE-gate dielectric. Thus, La2O3/HfO2/n-InXGa1-XAs MOS-capacitors were fabricated and evaluated, and the device performance was compared to that of MOS-capacitors with a single-layer high-κ gate dielectric.

5.2.2 Experiment

The structures of the n-InXGa1-XAs MOS-capacitors in this study are as shown in Fig. 5-2-1, including n- In0.53Ga0.47As channel, and n-InAs channel.

The device structures were grown by molecular beam epitaxy (MBE) on a 3-in n⁺-InP substrate. The structure layer of n-In0.53Ga0.47As is 100-nm-thick with Si doping concentration of 5х10¹⁷cm^-3. The structure layers of n-InAs device, from bottom to top, are composed of a 10-nm-thick n-In0.53Ga0.47As (Si：5х10¹⁷cm^-3 ), a 3-nm-thick n-In0.70Ga0.30As (Si：5х10¹⁷cm^-3 ), and a 5-nm-thick n-InAs (Si：

5х10¹⁷cm^-3 ).

The wafers were first cleaned in a dilute HF (50%) solution for 3 minutes, and then followed by surface treatment in a (NH4)2SX solution for 30 minutes at room temperature. After cleaning, the wafer was deposited bilayer gate dielectric La2O3/HfO2 at 300^oC using the MBE system. For the test samples, pure La2O3 or pure HfO2 was also deposited under the same condition. After the gate oxide deposition, the post deposition annealing (PDA) process was performed at 400

oC. Then, W metal was deposited as the gate metal by the lift-off process and Au metal was deposited by the sputtering process as the backside ohmic contact.

Fig. 5-2-1 Structures of the n-In_XGa_1-XAs MOS-capacitors

5.2.3 Results and Discussion

JG-VG Characteristics

Fig. 5-2-2 shows the gate leakage current density of n-In0.53Ga0.47As MOS-capacitors with La2O3, HfO2, and La2O3/HfO2 bilayer gate dielectrics. The

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