The Theory of MOS-Capacitors

Metal-Oxide-Semiconductor field-effect transistors (MOSFETs) are the most important devices which were used in digital integrated circuit applications today. In general, the major core of MOSFETs is Metal-Oxide-Semiconductor capacitors (MOSCAPs) which determine the device performance.

As shown in Fig. 2-1, a basic MOS-capacitor structure consists of, from bottom to top, the back side metal, the semiconductor substrate, a thin oxide layer, and the gate metal. Based on the type of the substrate, p-type or n-type, MOS-capacitors can be divided into two categories.

The main operation conditions of MOS-capacitors include accumulation, depletion, and inversion.

Fig. 2-1 Basic metal-oxide-semiconductor capacitor structure

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2.1.1 MOS-Capacitor with P-type Substrate

Fig. 2-2 shows the band diagram of a MOS-capacitor with the p-type substrate. Under a negative gate voltage, the valence band at the oxide/semiconductor interface bent upward and could be close to the Fermi level, and it means that there is hole-accumulation at the semiconductor surface as shown in Fig. 2-2(a).

Under a small positive gate voltage, conduction band and intrinsic Fermi level bent downward and could be close to the Fermi level as shown in Fig.

2-2(b), and there is a depletion region occurs at the semiconductor surface. The depletion region expands with the increase of positive gate voltage.

As a much larger positive gate voltage is applied, the band bent even more as shown in Fig. 2-2(c). The intrinsic Fermi level at the interface is now lower than the Fermi level, so that it is n-type like at the oxide/semiconductor interface, which means the positive gate voltage starts to induce electrons at the interface.

In this case, the amount of minority carriers (electrons) is greater than that of majority carriers (holes) leading to the formation of an inversion layer.

By applying a high enough positive gate voltage, the carriers on the p-type substrate surface are inverted from p (holes) to n (electrons), and it is called the NMOS-capacitors.

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(a) Accumulation

(b) Depletion

(c) Inversion

Fig. 2-2 Band diagram of a MOS-capacitor with a p-type substrate

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2.1.2 MOS-Capacitor with N-type Substrate

Fig. 2-3 shows the band diagram of a MOS-capacitor with the n-type substrate. Under a positive gate voltage, the conduction band at the oxide/semiconductor interface bent downward and could be close to the Fermi level, and it means that there is electron-accumulation at the semiconductor surface as shown in Fig. 2-3(a).

Under a small negative gate voltage, valence band and intrinsic Fermi level bent upward and could be close to the Fermi level as shown in Fig. 2-3(b), and there is a depletion region occurs at the semiconductor surface. The depletion region expands with the increase of negative gate voltage.

As a much larger negative gate voltage is applied, the band bent even more as shown in Fig. 2-3(c). The intrinsic Fermi level at the interface is now higher than the Fermi level, so that it is p-type like at the oxide/semiconductor interface, which means the negative gate voltage starts to induce holes at the interface. In this case, the amount of minority carriers (holes) is greater than that of majority carriers (electrons) leading to the formation of an inversion layer.

By applying a high enough negative gate voltage, the carriers on the n-type substrate surface are inverted from n (electrons) to p (holes), and it is called the PMOS-capacitors.

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(a) Accumulation

(b) Depletion

(c) Inversion

Fig. 2-3 Band diagram of a MOS-capacitor with a n-type substrate

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2.1.3 MOS-Capacitor Characterization

The C-V measurements are widely used to quantitatively study MOS-capacitors. There are three important factors to evaluate the device performance, including flat-band voltage, hysteresis, and frequency dispersion.

All of these factors are highly related with the quality of dielectric/semiconductor interface, as well as the interface trap density (Dit).

Flat-band Voltage

Flat-band voltage is used to determine the gate voltage at the condition of no bending in the semiconductor energy band diagram, which leads to no charge in the semiconductor, as shown in Fig. 2-4. And it is regarded as the ideal flat-band voltage. However, the real flat-band voltage would shift ΔVFB due to there are trap charges exiting at the dielectric/semiconductor interface.

Fig. 2-4 Band diagram of flat-band condition of a MOS-capacitor [2-1]

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Hysteresis

Hysteresis is measured a C-V curve under a certain frequency by sweeping the gate voltage forth and back. The amount of hysteresis is related with the amount of charges trapped by the defects in the gate dielectric, so that it can be used to determine the dielectric quality. The clockwise hysteresis implies the negative charges are trapped；On the other hand, the counterclockwise hysteresis implies the positive charges are trapped. The defects extracted from hysteresis are called as slow trapping states, and the interface traps are fast trapping states.

Frequency Dispersion

Frequency dispersion is the phenomenon of accumulation capacitance varying with different operated frequencies. The origin of frequency dispersion is related to the poor quality of dielectric/semiconductor interface, where there are a large amount of interface traps exiting. The interface traps are frequency dependent, and they would capture and emit charges leading to frequency dispersion of a C-V curve. Seriously, interface traps would cause Fermi level pinning degrading device performance.

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