Chapter 1 Introduction
1.2 Thesis organization
3 4224 MHz 4488 MHz 4752 MHz
4 4752 MHz 5016 MHz 5280 MHz
5 5280 MHz 5544 MHz 5808 MHz
2
6 5808 MHz 6072 MHz 6336 MHz
7 6336 MHz 6600 MHz 6864 MHz
8 6864 MHz 7128 MHz 7392 MHz
3
9 7392 MHz 7656 MHz 7920 MHz
10 7920 MHz 8184 MHz 8448 MHz
11 8448 MHz 8712 MHz 8976 MHz
4
12 8976 MHz 9240 MHz 9504 MHz
13 9504 MHz 9768 MHz 10032 MHz 14 10032 MHz 10296 MHz 10560 MHz
Table 1.1 MBOA band plan
1.2 Thesis organization
This thesis discusses about the circuit design and implementation of Ultra-wideband Low-Noise amplifier and wide-band mixer, in chapter 2 and 3, respectively. In chapter 4, we will make a conclusion and discuss the future work. We will present the design flow and experimental results in TSMC 0.18-μm CMOS process. Moreover, we will discuss the reasons of differences between simulation and measurement results.
In chapter 2, this chapter includes two circuits. The first section is low-voltage ultra wide-band LNA, The second section is 3–8 GHz wideband LNA using transistor’s
- 4 -
intrinsic capacitor feedback. We will discuss these configurations, wideband input/output matching, noise and linearity of LNA. Besides, electromagnetic simulated software Sonnet and Momentum is used to approach simulated results to practical circuited property.
In Chapter 3, we will present the design and implementation of wide-band mixer for UWB applications. Firstly we review the topology and operation theory of basic mixer in section 3.1. The proposed wide-band mixer is presented in section 3.2. Section3.3 discusses layout and measurement consideration of the proposed mixer. Finally, the experiment results and comparison are presented in section 3.4.
Finally, an integrated RF receiver front-end for Ultra-wideband application is proposed in appendix. Firstly we review the architecture of receiver in section A.1. The proposed front-end circuit is presented in section A.2. Finally, the simulation results and comparison are presented in section A.3
- 5 -
Chapter 2
CMOS Low-Noise Amplifier for UWB System
2.1 Introduction
A low-noise amplifier is the first stage, after antenna in the receiver block of a communication system. For UWB applications, the criteria to judge its performances are slightly different from narrow system. Because transmitted power spreads over a wide range and is restricted to be less than -41.3 dBm per MHz, the requirement on linearity in UWB system is not such important as in narrow system. The important requirements for UWB applications are wide-band input impedance matching, low power consumption, low noise performance, and enough gain to suppress noise of the next stages.
In order to connect to an antenna port, the first problem facing is 50 Ohm wide-band input matching. Fig. 2.1.1 shows the four basic 50 Ohm input matching techniques.
However, these topologies have some drawbacks. Fig. 2.1.1 (a) is traditional source degeneration topology, because it only resonances at one frequency, it can’t achieve wide-band 50 Ohm matching. It realizes only narrow band matching. Fig. 2.1.1 (b) is the resistive termination matching, because of the loading effect, it will loss a lot of voltage if resistive termination matching is used. Fig. 2.1.1 (c) is feedback method. It can achieve wideband input matching. But because of feedback mechanism, it can’t achieve high gain to suppress noise of the next stages. Fig. 2.1.1 (d) is LC 3’rd
- 6 -
Chebyshev band-pass filter. It can perform good input matching, but it consumes large chip area because of using four inductors for input matching.
(a) (b)
(c)
(d)
Fig. 2.1.1 Conventional input matching technology
Several CMOS LNA design techniques had been reported for broadband communication applications. Recent research shows that relatively flat gain can be achieved over the 3.1- to 10.6-GHz UWB band using CMOS distributed amplifiers.
However, due to the additive nature of each transistor’s gain, the distributed amplifiers
- 7 -
cannot achieve high gain. The average gain of the reported DAs is around 8 dB, which is insufficient to amplify the received UWB signal. On the other hand, as shown in Fig.
2.1.2, it requires several area consuming inductors to perform signal delay and many stages to provide a given gain that consumes much power [4-5]
Fig. 2.1.2 Conventional distributed amplifier
2.2 Ultra Wide-band Low-Noise Amplifier
2.2.1 Low-voltage, Low noise Ultra-Wideband
Amplifier
2.2.1.1 Architectures
For the UWB technology to be widely employed in the hand-held wireless applications, it cannot be avoided that power consumption is one of the main issues. So we present low-voltage UWB LNA topology.
The fundamental architecture of the low-voltage UWB LNA as shown in Fig. 2.2.1 is composed of cascode configuration and shunt peaking method. The shunt peaking method is used for the requirement of low power consumption and flat gain
- 8 -
performance over wide bandwidth [6]. The cascode structure also has good properties of better reverse isolation, frequency response, lower noise figure and less Miller effect.
In order to achieve wideband input matching from 3.1 to 10.6 GHz, the three-section Chebyshev filter is used in the input matching network by combining the gate-drain parasitic capacitance of M1 and the inductance Ls.
Fig. 2.2.1 Fundamental architecture of the UWB LNA [6]
The proposed low-voltage, low-noise amplifier is shown in Fig. 2.2.2. The LNA circuit can be divided into three blocks –input matching stage, amplifying stage and output buffer stage. Here, we employ a common-gate stage and folded-cascode architecture with shunt peaking method to achieve good performance from 3.1 to 10.6G-Hz with only 0.75V supply.
For input matching stage: common-gate stage (M1) not only is suit for wideband input matching, but also can amplify RF signal. For amplifying stage: L1 is RF chock inductor which is open in small signal mode. The folded-cascode structure has good properties of better reverse isolation, frequency response, less Miller effect and low-voltage operation. Shunt peaking method (Lpd, Rpd) can enhance flat degree of power gain. TL is parasitic inductor of layout path and it can increase stability of the low-noise amplifier. An output buffer composed of common collector amplifier (Mb) is
- 9 -
added for measurement purposes.
Vin
Rs C1 Lgs
Lgd
L1
Lpd
Lbs Rpd
TL
VDD VDD
VDD
Vbias
Vbias
Vbias Cpass
Cpass
C2 VDD=0.75V
Vo M1
Mn Mp
Mb Rb
Rb
Fig. 2.2.2 Proposed architecture of the low voltage UWB LNA
2.2.1.2 Design considerations A. Input matching analysis
A common-gate (M1) is used to match to 50Ω, its small signal equivalent circuit is shown in Fig. 2.2.3. Cgs and Cgd respectively are the gate-to-source and the gate-to-drain parasitic capacitance; ro is the channel length modulation resistor of MOS transistor. The input impedance of the common-gate can be derived as [8]
- 10 -
Fig. 2.2.3 Input small signal equivalent circuit In equation (2-1), the third term in denominator is induced by finite channel length modulation of a MOS. To obtain more insight on the impact of ro on the input impedance, we may assume that:
) Equation (2-1) can be re-written by substituting (2-4) and (2-5) into (2-1) and we get
)) term )Xs(w dominates the imaginary part of equation (2-6).
- 11 -
Some observations can be made based on the equation (2-6): One is that the trans-conductance of the MOS transistor in common-gate configuration should be set slightly greater than 20 mS for better matching due to the effect of the MOS transistor’s finite output resistance ro, and at the resonated frequency of Ls and Cgs has the best input reflection coefficient.
B. Noise analysis a. Noise in MOSFETS
To develop good CMOS RF circuit design skills, a fundamental understanding of noise source in a MOSFET is necessary. In part a. section, we will focus on the inherent noise of a MOSFET, which can be categorized into two parts: drain noise source and gate noise source.
(i) Drain noise source
The dominant noise source in a MOSFET is the channel thermal noise, which basically is a thermal noise originated from the voltage-controlled resistor mechanism of a MOSFET. Detailed theoretically considerations lead to the following expression for the channel noise of a MOSFET, which is modeled as a shunt current noise
“ind12“in the output current of the device, as shown in Fig. 2.2.5. Another source of drain noise is flicker noise. Flicker noise appears as 1/f character and is found in all active devices, as well as in some discrete passive element such as carbon resistors. In diodes, flicker noise is caused by traps associated with contamination and crystal defects in the depletion regions. In MOSFET, charge trapping phenomena are invoked in surface, and his type of noise is much greater than that of the bipolar transistor. The flicker noise in MOSFET can be given by
f f A
f k WLC
g f
i k T
ox m
nd = .Δ ≈ . . .Δ
. 2 2
2 2
2 ω
- 12 -
where K is the process-dependent constant, and A is the area of the gate.
Hence, the total drain noise source is given by
WLC f
Fig. 2.2.5 channel thermal noise model (ii) Gate noise
In addition to drain current noise, the thermal agitation of channel charge has another important consequence: gate noise. The fluctuating channel potential couples capacitively into the gate terminal, leading to a noisy gate current. Noisy gate current may also be produced by thermally noisy resistive gate material. Although this noise is negligible at low frequencies, it can dominate at radio frequencies. The gate current noise may be expressed as
And δ is the coefficient of gate noise, classically equal to 4/3 for long-channel devices.
The gate noise is correlated with the drain noise, with a correlation coefficient expressed as
j
- 13 -
The value of -0.395j is exact for long-channel devices. The correlation can be treated by expressing the gate noise as the sum of two components, the first of which is fully correlated with the drain noise, and the second of which is uncorrelated with the drain noise. Hence, the gate noise is re-expressed as
2 2
2
. 4 ) 1 ( .
4kT g c kT g c
f i
g g
g = δ − + δ
Δ
A standard MOSFET noise model can be presented in Fig. 2-2.2.6, where ind2 is the
drain noise source, ig2 is the gate noise source, and vrg2 is thermal noise source of gate parasitic resistor rg.
Fig. 2.2.6 MOSFET noise model
b. Common-Gate Stage Noise Analyze
Based on MOSFET noise model, the equivalent noise circuit of the proposed low-noise amplifier is shown in Fig. 2.2.7. TL is omitted because of its value is small.
(a)
- 14 -
(b)
Fig. 2.2.7 Common-gate cascade common-source stage noise circuit The output noise PSD contributed by the source resistor is given as:
2
The noise contributed by the part of the induced gate noise in M1 that is fully uncorrelated with the drain noise is given by:
Rs
The output noise PSD due to the two noise sources in M1 is then given by:
Rs
Where the first term is contributed by the channel thermal noise of M1, the second term by the correlated part of the induced gate noise, and the last term arises from the correlation of these two noise sources. The noise contributions by M2 are given by:
Rs
- 15 -
The total noise factor is derived as:
Rs
F1 is the noise factor of the single common-gate stage, excluding the effect of the noise contributed by the common source stage which is given by the later two terms.
Where F1 is given by:
In equation (2-7), because gm1 is in the denominator, the trans-conductance (gm1) of M1 should be increased to decrease noise factor and at the resonated frequency of Ls and Cgs has the minimal noise figure. But the input matching will be worse than -10dB when gm1 increases to 35 mS. There is a trade-off between input matching and noise factor for common-gate circuit. For the proposed circuit , gm1 is set about 33ms to decrease noise factor, but input return loss still better than -10db.
C. Gain analysis (Shunt peaking method)
Shunt peaking is a bandwidth extension technique in which an inductor connected in series with the load resistor shunts the output capacitor C. A common-source amplifier with shunt peaking is shown in Fig. 2.2.8. For the shunt-peaked network:
- 16 -
The inductor introduces a zero in Z(s) that increases the impedance with frequency, compensates the decreasing impedance of C, and thus extends the -3 dB bandwidth.
The magnitude of the impedance, normalized to the DC value as a function of frequency, is then
so that
where ω1 is the uncompensated -3dB frequency. We can choose congruous m to achieve flat wide-band gain.
Fig. 2.2.8 A common-source amplifier with bridged-shunt peaking.
2.2.2 3–8 GHz wideband LNA Using Capacitor
Feedback
2.2.2.1 Architectures
A simple wide-band input matching network is present in a standard 0.18um CMOS technology in this section. The proposed circuit using transistor’s intrinsic capacitor
- 17 -
feedback achieve -10 dB input reflection coefficient from 2.75 GHz to 12 GHz.
Compared with traditional matching network of narrow band LNA, such matching mechanism is not an additional inductor, input broadband matching still can be reached.
The fabricated wideband LNA achieves average power gain (S21) of about 10 dB from 2.75-GHz to 7.7-GHz .From the bandwidth, the broadband LNA exhibits a noise figure of 3.64–5.5 dB. The DC supply is 1.5 V.
Fig. 2.2.9 Topology of the proposed UWB LNA
Fig. 2.2.9 shows the schematic of the proposed wideband LNA circuit composed of common source stage and common gate stage. L1 and L2 are RF choke inductors which are open in small signal mode. M1、M2、Rd、Ld form cascode amplifier with shunt-peaking load to achieve flat power gain, better reverse isolation, better frequency response, lower noise figure and less Miller effect. An output buffer composed of common collector amplifier is added for measurement purposes.
2.2.2.2 Design considerations A. Input matching analysis [30]
In this section, we focus on the design of input matching network. Fig. 2.2.10 shows
- 18 -
the small signal circuit of the proposed wide-band LNA. In order to analyze the input-matching network, the small signal circuit of the wideband LNA is decomposed into two parts. One is resistor feedback in high frequency mode, the other one is capacitor feedback in low frequency mode, as shown in Fig. 2.2.11 (a) (b), respectively.
Fig.2.2.10 LNA small signal diagram
Fig. 2.2.11 (a) LNA small signal diagram at high frequency mode
- 19 -
Fig. 2.2.11 (b) LNA small signal diagram in low frequency mode
At high frequency mode small signal circuit as shown in Fig. 2.2.11 (a): Using KCL KVL theory, approximate input impedance can be got that:
(1)
Fig. 2.2.11 (C) Low frequency mode input port equivalent circuit
At low frequency mode as shown in Fig. 2.2.11 (b): Using KCL KVL theory, approximate input impedance equivalent circuit can be shown in Fig. 2.2.11. (c).
Because Cβ Lβ are much small and Rβ is much large, B2 branch is omitted. B1 branch
- 20 -
dominates the low frequency mode impedance function. Where:
gd
The matching frequency at low frequency mode is that:
)
To make use of equation of (1) and (2), two-frequency matching mechanism is realized and wideband input matching can be achieved.
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
FF Corner SS Corner TT Corner
Fig. 2.2.12 S11 of the proposed LNA
2.3 Chip implementation and measured result
A. Measurement consideration
The two UWB Low-Noise amplifiers are designed for on-wafer testing. Therefore the arrangement of each pad must satisfy rules of CIC’s (Chip Implementation Center’s) probe station testing rules.
For folded LNA: Two six-pin dc probes are required to feed with dc voltages. In addition, two RF probes are also needed for RF signals.
- 21 -
Fig. 2.3.1 (a) On-wafer measurement of low-voltage UWB LNA test diagram
For 3-8 GHz capacitor feedback LNA: One six-pin dc probe, one three-pin dc probe and two RF probes are required. Fig 2.2.13 (a~c) shows the arrangement for dc and RF probes.
Fig. 2.3.1 (b) On-wafer measurement of 3-8 GHz LNA test diagram
Fig. 2.3.1 (c) The photo for measurement environment
- 22 -
The measurement equipments include a network analyzer ( HP8510C ), a noise analyzer ( Agilent N8975A ), a spectrum analyzer ( Agilent E4407B ), two signal generators, and several dc power supplies. The measurement setups for S-parameter, noise figure are shown in Fig. 2.2.14 (a~b). We use the RF IC measurement system powered by LabView to measure the linearity of the UWB LNA. The measurement setups for 1-dB compression point (P1dB), IIP3 are shown in Fig. 2.2.14 (c~d). We will discuss the experimental and testing resultsof this circuit in following sections.
HP-8510C network analyzer N 8975A 之雜訊分析儀
(a) (b)
- 23 -
(c)
(d)
Fig. 2.3.2 Measurement setups for (a) S-parameter (b) noise figure (c) P1dB (d) IIP3
B. Folded UWB LNA Measurement result
The layout and chip photo of the proposed folded UWB LNA is shown in Fig 2.2.15 and Fig 2.2.16, respectively. A DC block capacitor is needed in the input of the UWB LNA to isolate the dc between circuit and equipment.
- 24 -
Fig 2.3.3 Layout of the proposed low-voltage LNA
Fig2.3.4 Micrograph of the proposed low-voltage LNA
This work is designed and processed using TSMC 0.18µm mixed-signal/RF CMOS 1P6M technology. The S-parameter are shown in Fig. 2.2.17(a) (b), Fig. 2.2.18 and Fig.
2.2.19, where the measured S11 < -10dB and S22 < -9 dB from 3.1 GHz to 10.6 GHz, except the point which produces peak value. The power gain (S21) is around 7.5dB from 3.1 to 7.5 GHz, the 3dB bandwidth is 2.9-8.7 GHz. The measured noise figure of
- 25 -
4.8-7.5 dB from 2.75 to 7.7 GHz has been presented in the proposed as shown in Fig.
2.2.20. The measured P1dB are -14dBm at 5.1 GHz, and -10dBm at 7.5 GHz in Fig.
2.2.21. The measured IIP3 are -4dBm at 5.1 GHz, and -1.2dBm at 7.5 GHz in Fig.
2.2.22.Table2.2.1 summarizes the measured data of proposed wideband LNA.
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 Frequency (GHz)
-28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20
Measurement S21 Simulation S21
Fig. 2.3.5 (a) Power gain vs. Frequency
- 26 -
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 Frequency (GHz)
-90 -80 -70 -60 -50 -40 -30
Measurement S12 Simulation S12
Fig. 2.3.5 (b) Isolation vs. Frequency
1 2 3 4 5 6 7 8 9 10 11 12
Freqency (GHz) -30
-25 -20 -15 -10 -5
0 Simulation S11
Measurement S11
Fig. 2.3.6 Input return loss coefficient vs. Frequency
- 27 -
1 2 3 4 5 6 7 8 9 10 11 12
Freqency (GHz) -30
-25 -20 -15 -10 -5
0 Simulation S22
Measurement S22
Fig. 2.3.7 Output return loss coefficient vs. Frequency
3 4 5 6 7 8 9 10 11 12
Freqency (GHz) 1
2 3 4 5 6 7 8 9 10
NF (dB)
Simulation NF Measument NF
Fig. 2.3.8 Noise Figure vs. Frequency
- 28 -
-30 -25 -20 -15 -10 -5 0
Power RF (dBm) -4
Power RF (dBm) -4
- 29 -
-40 -35 -30 -25 -20 -15 -10 -5 0
Power RF (dBm) -100
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
Measurement Simulation
Fig. 2.3.10 (a) IIP3 at 5.1 GHz
-40 -35 -30 -25 -20 -15 -10 -5 0
Power RF (dBm) -100
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
Measurement Simulation
Fig. 2.3.10 (b) IIP3 at 7.5 GHz
- 30 -
Table.2.3.1 Performance summary of the proposed LNA
Specification Measurement Post Simulation
BW (GHz) 3 － 7.5 3 － 10
S11 (dB) <－10 <－10
S22 (dB) <－9 <－10
S21 (dB) 7.5 (flat gain) 10.5 (flat gain)
S12 (dB) <－34 <－50
Noise Figure (dB) 4.8-7.5 3.1-5.1
P1dB (dBm) -14 * -16 *
IIP3 (dBm) -4 * -6.5 *
Vdd (V) 0.75 V 0.75 V
Total Power (mW) 11 11.3
*at 5.1 GHz
C. Capacitor Feedback UWB LNA Measurement result
The layout and microphotograph of the UWB LNA circuit is shown in Fig. 2.3.11 and 12, respectively. The circuit is fabricated in the TSMC 0.18μm CMOS process technology. The die area including bonding pads is 0.825 mm by 0.94 mm.
Fig. 2.3.11 (a) Layout of UWB LNA (0.88*0.93mm2)
- 31 -
Fig. 2.3.12 (b) Photograph of UWB LNA (0.88*0.93mm2)
The S-parameter of simulation and measured results are plotted as shown from Fig.2.2.24 to Fig.2.2.26. The measured power gain S21 achieves the maximum value of 10.8dB at 2.7 GHz and the 3-dB bandwidth of power gain is from 1.9 GHz to 8.2 GHz.
The variation of inductor (Ld) lead to shunt peaking method don’t achieve adaptable m to enhance bandwidth and thus the power gain in high frequency will become small.
The average simulated and measured result of S22 are both smaller than -10dB, as shown in Fig.2.2.26.The S11 is shown in Fig .2.2.25. The measured result shows that the proposed circuit using transistor’s intrinsic capacitor feedback achieve -10 dB input reflection coefficient from 2.75 GHz to 12 GHz. The measurement and simulation result of noise, NF, is shown in Fig.2.2.27. The simulated minimum noise figure is 2.45dB at 5GHz, and the average noise figure is about 2.6dB. The measured minimum noise figure is 3.64dB at 3 GHz, and the average noise figure is about 4.6dB. Fig.2.2.28.
is the simulation and measurement result of the input 1 dB compression point (P1dB).
The two-tone test measured results for third-order intermodulation distortion are shown in Fig. 2.2.29. The measured result of IIP3 is -1.8 dBm and 1 dBm at 4.1 GHz and 7.5 GHz, individually. The core current of the proposed LNA is 15mA with a power supply
- 32 -
1.5V. Table 2.2.2 is the summary of simulated and measured performance of the proposed amplifier.
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 Frequency (GHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
S21(dB)
Simulation S21 Measurement S21
Fig. 2.3.13 S parameter vs. frequency
2 3 4 5 6 7 8 9 10 11 12 13
Freqency (GHz) -40
-35 -30 -25 -20 -15 -10 -5 0
S11 (dB)
Measument S11 Simulation S11
Fig. 2.3.14 S11 vs. frequency
- 33 -
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 Frequency (GHz)
-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
Simulation S12 Measurement S12
Simulation S22 Measurement S22
Fig. 2.3.15 S22 vs. frequency
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 Frequency (GHz)
2 3 4 5 6 7
NF (dB)
Fig.2.3.16 Noise Figure vs. frequency
- 34 -
3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8
Freqency (GHz) -20
-18 -16 -14 -12 -10 -8 -6 -4 -2 0
Power RF (dBm)
Simulation Measument
Fig. 2.3.17 Input 1 dB compression point vs. frequency
-40 -36 -32 -28 -24 -20 -16 -12 -8 -4 0 4 8 Power RF (dBm)
-100 -80 -60 -40 -20 0
Measurement Simulation
Fig. 2.3.18 (a) IIP3at 4 GHz
- 35 -
-40 -36 -32 -28 -24 -20 -16 -12 -8 -4 0 4 8 Power RF (dBm)
-100 -80 -60 -40 -20 0
Measurement Simulation
Fig. 2.3.18 (b) at 7.5 GHz
Table.2.3.2 Performance summary of the proposed LNA
Simulation Measurement
VDD 1.5 1.5 Band Width 3.1Ghz-8.1Ghz 2.75-7.7Ghz
3dB-bandwidth 1.9-9.5Ghz 1.8-8.3Ghz
S21max(dB) 12.8 10.8
S11(dB) < -10.1 < -10.0 S22(dB) < -12 < -10
NFaverage(dB) 2.6 4.6
P1db(dBm) >-13 >-14
IIP3(dBm) at 4 GHz -3 -1.8
UWB LNA Current 15mA 15.3mA
Buffer 5.5mA 5.8mA
- 36 -
2.4 Comparison and Discussion
Table 2.4.1 Comparison of Ultra Wide-band LNA Ref. Process BW
In the first work (Low-voltage UWB LNA) which reveal wideband performance under low voltage situation. But it is unexpected in the measured results at 3-4 GHz as simulation. Because the fabricated inductor value of TL (common source degeneration
In the first work (Low-voltage UWB LNA) which reveal wideband performance under low voltage situation. But it is unexpected in the measured results at 3-4 GHz as simulation. Because the fabricated inductor value of TL (common source degeneration