Design considerations

A common-gate (M1) is used to match to 50Ω, its small signal equivalent circuit is shown in Fig. 2.2.3. Cgs and Cgd respectively are the gate-to-source and the gate-to-drain parasitic capacitance; ro is the channel length modulation resistor of MOS transistor. The input impedance of the common-gate can be derived as [8]

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Fig. 2.2.3 Input small signal equivalent circuit In equation (2-1), the third term in denominator is induced by finite channel length modulation of a MOS. To obtain more insight on the impact of ro on the input impedance, we may assume that:

) Equation (2-1) can be re-written by substituting (2-4) and (2-5) into (2-1) and we get

)) term )X_s(w dominates the imaginary part of equation (2-6).

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Some observations can be made based on the equation (2-6): One is that the trans-conductance of the MOS transistor in common-gate configuration should be set slightly greater than 20 mS for better matching due to the effect of the MOS transistor’s finite output resistance ro, and at the resonated frequency of Ls and Cgs has the best input reflection coefficient.

B. Noise analysis a. Noise in MOSFETS

To develop good CMOS RF circuit design skills, a fundamental understanding of noise source in a MOSFET is necessary. In part a. section, we will focus on the inherent noise of a MOSFET, which can be categorized into two parts: drain noise source and gate noise source.

(i) Drain noise source

The dominant noise source in a MOSFET is the channel thermal noise, which basically is a thermal noise originated from the voltage-controlled resistor mechanism of a MOSFET. Detailed theoretically considerations lead to the following expression for the channel noise of a MOSFET, which is modeled as a shunt current noise

“i_nd1²“in the output current of the device, as shown in Fig. 2.2.5. Another source of drain noise is flicker noise. Flicker noise appears as 1/f character and is found in all active devices, as well as in some discrete passive element such as carbon resistors. In diodes, flicker noise is caused by traps associated with contamination and crystal defects in the depletion regions. In MOSFET, charge trapping phenomena are invoked in surface, and his type of noise is much greater than that of the bipolar transistor. The flicker noise in MOSFET can be given by

f f A

f k WLC

g f

i k _T

ox m

nd = .Δ ≈ . . .Δ

. 2 ²

2 2

2 ω

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where K is the process-dependent constant, and A is the area of the gate.

Hence, the total drain noise source is given by

WLC f

Fig. 2.2.5 channel thermal noise model (ii) Gate noise

In addition to drain current noise, the thermal agitation of channel charge has another important consequence: gate noise. The fluctuating channel potential couples capacitively into the gate terminal, leading to a noisy gate current. Noisy gate current may also be produced by thermally noisy resistive gate material. Although this noise is negligible at low frequencies, it can dominate at radio frequencies. The gate current noise may be expressed as

And δ is the coefficient of gate noise, classically equal to 4/3 for long-channel devices.

The gate noise is correlated with the drain noise, with a correlation coefficient expressed as

j

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The value of -0.395j is exact for long-channel devices. The correlation can be treated by expressing the gate noise as the sum of two components, the first of which is fully correlated with the drain noise, and the second of which is uncorrelated with the drain noise. Hence, the gate noise is re-expressed as

2 2

2

. 4 ) 1 ( .

4kT g c kT g c

f i

g g

g = δ − + δ

Δ

A standard MOSFET noise model can be presented in Fig. 2-2.2.6, where i_nd² is the

drain noise source, i_g² is the gate noise source, and v_rg² is thermal noise source of gate parasitic resistor rg.

Fig. 2.2.6 MOSFET noise model

b. Common-Gate Stage Noise Analyze

Based on MOSFET noise model, the equivalent noise circuit of the proposed low-noise amplifier is shown in Fig. 2.2.7. TL is omitted because of its value is small.

(a)

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(b)

Fig. 2.2.7 Common-gate cascade common-source stage noise circuit The output noise PSD contributed by the source resistor is given as:

2

The noise contributed by the part of the induced gate noise in M1 that is fully uncorrelated with the drain noise is given by:

Rs

The output noise PSD due to the two noise sources in M1 is then given by:

Rs

Where the first term is contributed by the channel thermal noise of M1, the second term by the correlated part of the induced gate noise, and the last term arises from the correlation of these two noise sources. The noise contributions by M2 are given by:

Rs

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The total noise factor is derived as:

Rs

F1 is the noise factor of the single common-gate stage, excluding the effect of the noise contributed by the common source stage which is given by the later two terms.

Where F1 is given by:

In equation (2-7), because gm1 is in the denominator, the trans-conductance (gm1) of M1 should be increased to decrease noise factor and at the resonated frequency of Ls and Cgs has the minimal noise figure. But the input matching will be worse than -10dB when gm1 increases to 35 mS. There is a trade-off between input matching and noise factor for common-gate circuit. For the proposed circuit , gm1 is set about 33ms to decrease noise factor, but input return loss still better than -10db.

C. Gain analysis (Shunt peaking method)

Shunt peaking is a bandwidth extension technique in which an inductor connected in series with the load resistor shunts the output capacitor C. A common-source amplifier with shunt peaking is shown in Fig. 2.2.8. For the shunt-peaked network:

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The inductor introduces a zero in Z(s) that increases the impedance with frequency, compensates the decreasing impedance of C, and thus extends the -3 dB bandwidth.

The magnitude of the impedance, normalized to the DC value as a function of frequency, is then

so that

where ω1 is the uncompensated -3dB frequency. We can choose congruous m to achieve flat wide-band gain.

Fig. 2.2.8 A common-source amplifier with bridged-shunt peaking.

2.2.2 3–8 GHz wideband LNA Using Capacitor

Feedback

2.2.2.1 Architectures

A simple wide-band input matching network is present in a standard 0.18um CMOS technology in this section. The proposed circuit using transistor’s intrinsic capacitor

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feedback achieve -10 dB input reflection coefficient from 2.75 GHz to 12 GHz.

Compared with traditional matching network of narrow band LNA, such matching mechanism is not an additional inductor, input broadband matching still can be reached.

The fabricated wideband LNA achieves average power gain (S21) of about 10 dB from 2.75-GHz to 7.7-GHz .From the bandwidth, the broadband LNA exhibits a noise figure of 3.64–5.5 dB. The DC supply is 1.5 V.

Fig. 2.2.9 Topology of the proposed UWB LNA

Fig. 2.2.9 shows the schematic of the proposed wideband LNA circuit composed of common source stage and common gate stage. L1 and L2 are RF choke inductors which are open in small signal mode. M1、M2、Rd、Ld form cascode amplifier with shunt-peaking load to achieve flat power gain, better reverse isolation, better frequency response, lower noise figure and less Miller effect. An output buffer composed of common collector amplifier is added for measurement purposes.

2.2.2.2 Design considerations A. Input matching analysis [30]

In this section, we focus on the design of input matching network. Fig. 2.2.10 shows

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the small signal circuit of the proposed wide-band LNA. In order to analyze the input-matching network, the small signal circuit of the wideband LNA is decomposed into two parts. One is resistor feedback in high frequency mode, the other one is capacitor feedback in low frequency mode, as shown in Fig. 2.2.11 (a) (b), respectively.

Fig.2.2.10 LNA small signal diagram

Fig. 2.2.11 (a) LNA small signal diagram at high frequency mode

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Fig. 2.2.11 (b) LNA small signal diagram in low frequency mode

At high frequency mode small signal circuit as shown in Fig. 2.2.11 (a): Using KCL KVL theory, approximate input impedance can be got that:

(1)

Fig. 2.2.11 (C) Low frequency mode input port equivalent circuit

At low frequency mode as shown in Fig. 2.2.11 (b): Using KCL KVL theory, approximate input impedance equivalent circuit can be shown in Fig. 2.2.11. (c).

Because Cβ Lβ are much small and Rβ is much large, B2 branch is omitted. B1 branch

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dominates the low frequency mode impedance function. Where:

gd

The matching frequency at low frequency mode is that:

)

To make use of equation of (1) and (2), two-frequency matching mechanism is realized and wideband input matching can be achieved.

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

FF Corner SS Corner TT Corner

Fig. 2.2.12 S11 of the proposed LNA