Chapter 3 A Folded Current-Reused Mixer for UWB Applications
3.5 Measurement results and discussion
3.5.2 Comparisons
-30 -25 -20
Isolation (dB)
RF to LO Isolation LO to RF Isolation
Fig. 3.5.8 Isolation with Frequency
3.5.2 Comparisons
The comparisons of the simulated and measured results are in Table 3.5.1. Because
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the RF port input return loss is not having good matching to 50 ohm in high frequency, the conversion power gain degenerates about 3 dB at 10.6 GHz. The measured linearity performances are worse than simulation, because that the voltage of trans-conductance MOS’s drain port is variation. The measured noise figure is worse to the simulation in high frequency owing to the degeneration of the conversion power gain in high frequency. Table 3.5.1 and Table 3.5.2 show the comparisons of this work and other recently ultra wide-band mixer paper. This work reveals highly conversion power gain comparing with other work.
Table 3.5.1 Comparison of Simulated and Measured Results Reference
Specification
This Work Sim.
This Work . Meas.
Process CMOS 0.18um CMOS 0.18um
Band Width 3.1-10.6 3.1-8
Supply Voltage(V) 1.5 1.5
RF Return Loss <-10 <-10
IF Return Loss <-10 <-10
LO Power (dBm) -3 -10
Conversion Power Gain 11.6~14.7 13.5-15.5
LO to RF Isolation N/A -40
DSB NF 11.35~15.9 11~14.5
P1db at 6.6 GHz -16 -24
IIP3 at 6GHz -4.25 -11.5
Core Circuit (mW) 10.95 11.25
Buffer (mW) 10.5 10.65
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Core Mixer Power (mW)
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Chapter 4
Conclusion and Future Work
4.1 Conclusion
This thesis contains three works: low voltage, low-noise ultra wide-band amplifier, the capacitor feedback ultra wide-band amplifier and folded current reused UWB mixer.
All of the simulated results are finished through ADS and Momentum simulator. These three circuits are fabricated in TSMC 0.18 um CMOS process. In this thesis, we have presented the design concepts and simulation versus measurement results.
4.1.1 Low voltage Ultra Wide-band LNA
The low-voltage, UWB LNA topology is fabricated and analyzed in chapter 2, including input matching, noise figure, and power gain. By way of folded cascode structure and shunt peaking method, it achieves high isolation, low voltage, and wideband performances. The measured power gain is 7.5dB from 3.1 to 7.5 GHz. The input return loss is less than -10 dB from 3.1GHz to 10.6GHz, except the point which produces peak value. The fabricated inductor value of TL (common source degeneration inductor) is not expected as simulated inductor value of TL, it causes the circuit is seemly unstable at 3-4 GHz. The measured noise figure is 4.8-7.5 from 3.1 to 7.5 GHz. The measured P1dB are -14dBm at 5.1 GHz, and -10dBm at 7.5 GHz. The measured results show the LNA achieves wideband performance at 0.75V supply voltage, and the total power consumption of the proposed LNA is only 11.3 mW.
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4.1.2 3-8 GHz capacitor feedback Wide-band LNA
The proposed 3-8 GHz wideband LNA uses cascode stage with shunt peaking method to achieve wideband power gain. By way of transistor’s intrinsic capacitor Cgd and only one inductor as input matching network, wideband input matching can be achieved.
The measured results reveal that S11 is better than -10 dB from 2.7 GHz to 12.1 GHz.
The fabricated wideband LNA achieves flat power gain (S21) of about 10dB and the 3 dB bandwidth is from 1.8 GHz to 8.3 GHz. The measured noise figure is 3.7-5.5dB from 3 GHz to 7.5 GHz. The matching mechanism of the proposed wide-band LNA can simply the matching network and reduce noise figure of the amplifier efficaciously.
4.1.3 Folded Current Reuse Ultra Wide-band Mixer
The Folded Current Reused Ultra wide-band Mixer has been designed and presented in this thesis. The proposed UWB mixer replaces the traditional common source trans-conductance stage with a folded current-reused pair. It not only reduces the supply voltage, but also increases trans-conductance effectively. Such folded current-reused structure can use DC current effectively because that the main current flows through trans-conductance stage. All measurements were finished through on-wafer testing.
With the 1.5 V supply voltage, the UWB mixer excites 13.5-15.5 dB of power gain from 3-8 GHz with -10 dBm of LO power and 11.25 mW of power consumption in core circuit. The measured noise figure is 11-14.5 dB with IF=150 MHz and IIP3 is -11.5 dBm at 6 GHz. The measured linearity performances are not as expected, because that the voltage of trans-conductance MOS’s drain port is variation. The measured results show that the folded current reused mixer exhibits a low power and high conversion power gain than the conventional Gilbert type mixer architecture.
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4.2 Future Work
In this thesis, we have finished the design and measurement of UWB LNA and UWB mixer. In ultra wide-band receiver architecture, there are many important blocks needed to be implemented: Synthesizer, AGC, and A/D converter. There are some other future works needed to be implemented. First, the on-chip bias circuit should be designed to reduce the large number of DC pads. Second, the ESD protection must be designed within the thinner gate oxide process. Finally, the EM EDA tool must be used accurately and all parasitic effects including parasitic capacitance, resistance and inductance must be considered carefully.
The proposed 3-8 GHz capacitor feedback low noise amplifier may be improved as low power ultra wide-band LNA to fit UWB communication system well. And the folded current reuse mixer may be improved for its linearity to increase the total linearity of the receiver.
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Appendix
A RF Receiver Front-End for UWB Wireless System
In this addendum, we demonstrate a 3-8 GHz RF receiver front-end for Ultra wide-band system. We also review the traditional receiver architecture and Multi-band orthogonal frequency division multiplexing (MBOA) receiver.
A.1 Traditional Receiver and MBOA Receiver Front End
The goal of radio receiver is to detect a signal from the electromagnetic spectrum. In this section, we will introduce heterodyne, low-IF, zero-IF, and MB-OFDM Ultra wide-band receiver architecture.
Super Heterodyne Receiver
Figure A.1.1 shows super heterodyne receiver architecture. Super heterodyne receiver down-converters the RF input signal to an intermediate frequency (IF) by two steps through image rejection filter, if filter and mixer. It can solve the trade-off between selectivity and sensitivity. The drawback of super heterodyne receiver architecture is that it requires many components. It is difficult to be integrated into a single chip because the on chip filter would occupy large areas.
Fig.A.1.1 Super heterodyne receiver architecture
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Zero-IF Receiver
Figure A.1.2 shows zero-IF receiver architecture. Zero-IF architecture is also called
“homodyne”, “direct-conversion”. In zero-IF receiver, where the LO signal frequency is equal to the RF input frequency and the LO signal will translate the center of the desired signal to 0 Hz. It has two chief advantages of homodyne receiver. First, the problem of image is solved because of zero-IF. Second, because of simple architecture, it is easy integrated. But the chief drawbacks of zero-IF receiver are I/Q mismatch and
“DC offset” as shown in Figure A.1.3. The problem of DC offset can be solved by using even-harmonic mixer [19].
Fig A.1.2 Zero-IF receiver architecture
(a)
(b)
Fig A.1.3 (a)(b) Mechanism of direct conversion receiver with self-mixing
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Low-IF Receiver
Low-IF receiver converts the RF signal to low IF signal. Low-IF receiver has great interest because of its higher level of integration. Comparing with the Zero-IF receiver, the drawbacks such as dc offset and LO self-mixing is not occurred in Low-IF receiver.
The problem of image can be solved by using image reject architecture (Hartley, Weaver) as shown in Figure A.1.4.
(a)
(b)
Fig A.1.4 Low-IF receiver architecture (a) Hartley (b) Weaver
MB-OFDM Ultra wide-band receiver
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Fig A.1.5 MB-OFDM Ultra wide-band receiver architecture
Figure A.1.5 shows receiver architecture for MB-OFDM UWB system. For architectural point, the MB-OFDM receiver is similar to WLAN receiver. The chief difference is in local oscillator and the bandwidth of base-band signal.
Because MB-OFDM UWB system cover 14 bands through entire spectrum, tradition signal generator can’t produce so wide bandwidth. The frequency synthesizers used in UWB system are usually designed with high frequency voltage-controlled oscillator (VCO), multi-stage dividers, and SSB mixer in order to produce multi-band LO signals.
For mode 1 is shown in Figure A.1.6.
Fig A.1.6 MB-OFDM Mode1 signal generator architecture
By 4224 MHz phase lock loop combined with divided by eight and two circuit, 264 MHz and 792MHz can be produced. Make use of 4224 MHz, 264 MHz, 792MHz, and
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SSB mixer. We can get three center frequencies of mode 1 (3432 MHz, 3960 MHz, and 4488 MHz).
A.2 Main Block Description
Figure A.2.1 shows a 3-8 GHz ultra wide-band front-end. The low noise amplifier is the first stage of the front-end circuit. The first stage must provide sufficient power gain through entire bandwidth to suppress the noise of next stage.
Fig A.2.1 The proposed 3-8 GHz front-end circuit
A.2.1 LNA
Fig A.2.2 The schematic of low noise amplifier
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Figure A.2.2 shows the schematic of the proposed wide-band LNA circuit composed of common source stage and common gate stage with shunt-peaking method. L1 and L2 are RF chock inductor. In small signal mode, the LNA is cascaded by cascode stage and common source stage. By way of transistor’s intrinsic capacitor Cgd and only one inductor (Lg) as input matching network, wideband input matching can be achieved.
This matching mechanism can simplify the matching network effectively. The main principle of the LNA is introduced in chapter2.
A.2.2 Mixer
Fig A.2.3 The schematic of down converter mixer
A Gilbert cell like mixer, shown in Fig A.2.3, follows the LNA directly on-chip. It translates the input signal from RF to a 0-256 MHz intermediate frequency. The mixer is AC coupled by the LNA output. A single-ended-to-differential converter is merged at
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mixer. In a classical Gilbert cell, only the NMOS input trans-conductor is used. This stage is designed trading between trans-conductance gain, noise, linearity, and current consumption. In this design, a PMOS trans-conductor shunts the NMOS, as shown in the figure. This allows us to save current consumption, for given gain. In the case of the double balance mixer, the AC-coupled CMOS inverter is used as the trans-conductor.
The lowest supply voltage of the mixer can be derived as below:
4 3 2
1 min
, ov ov 2 t rfdcp rfdcp ov ov
dd V V V V V V V
V = + + + − + +
We can choose adaptable Vrfdcp and Vrfdcp to increase headroom voltage efficaciously.
And Gm=(gmn+gmp) value is increased efficaciously. The biasing currents of PMOS and NMOS devices are slightly different in order to bias the switching stage and the output load. In order to achieve wide-bandwidth (264 MHz) at IF port, resistive load is used at load stage.
A.3 Layout and Simulation Results A.3.1 Layout Consideration
Figure A.3.1 is the layout of the proposed Ultra wideband front-end circuit. The proposed circuit is designed for on-wafer measurement with three DC bound wires. It follows the rules of CIC’s (Chip Implementation Center’s) probe station testing rules.
Figure A.3.2 shows the on-wafer measurement setup with four probes and three bound wires. In layout consideration, we add many by-pass capacitors to prevent oscillation in low frequency and to increase the degree of perfect ac ground. Total die area including pads is 1.16 mm2.
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Fig A.3.1 The layout of the front-end circuit
Fig A.3.2 The measurement setup of the front-end circuit
A.3.2 Simulation Results
Input impedance matching is characterized in Fig. A.3.3, which reveals the simulated
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input return loss of better than -10 dB is attained over the 3-8 GHz. Fig A.3.4 shows the simulated power gain over the group1~3 of ultra wide-band receiver front-end achieves a power gain of 19-21.5 dB. The simulated method of conversion power gain adopts to fix LO frequency at center frequency and to sweep RF frequency from low band frequency to high band frequency. Fig A.3.5 shows the simulated noise figure of the circuit, which achieves noise figure of 4.3-6.2 dB from 3.1 to 8 GHz with IF=100 MHz.
Fig A.3.6 shows the input 1-dB compression point of the circuit, which is from -25.5 to -27.5 dBm. A two-tone test for the in-band third-order intercept point (IIP3) by sweeping the input power level was simulated at 3.1 GHz, 5.1 GHz and 8.1 GHz with tone spacing of 1 MHz. The output levels of the fundamental tone and the third-order intermodulation distortion are shown in Fig A.3.7 (a)-(c). An input IP3 (IIP3) of -15~-17.5 dBm is extrapolated. The supply voltage is 1.5 V and measured core current consumption is 13.1 mA. The performance of the RF front-end is finally summarized in Table A.1. Table A.2 lists the comparison of the recently ultra wide-band front-end circuit with this work.
1 2 3 4 5 6 7 8 9 10
Frequency (GHz) -20
-18 -16 -14 -12 -10 -8 -6 -4 -2 0
S11 (dB)
Sim S11
Fig A.3.3 Simulated S11 of the front-end circuit
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3.168 3.696 4.224 4.752 5.28 5.808 6.336 6.864 7.392 7.92 Freqency (GHz)
13 14 15 16 17 18 19 20 21 22 23 24
Conversion Gain (dB)
Conversion Gain
Group1 Group2 Group3
Fig A.3.4 The simulated conversion power gain of the front-end circuit
3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.6 7.1 7.6 8.1 8.6 Frequency (GHz)
4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
NF (dB)
1 MHz 10 MHz 100 MHz
264 MHz 528 MHz
Fig A.3.5 The simulated noise figure of the front-end circuit
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Fig A.3.6 The P1dB of the front-end circuit
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10
Power RF (dBm) -140 Power RF (dBm)
-140
Power RF (dBm) -140
Fig A.3.7 Third-order intercept point of the circuit
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Table A.1 Simulated performance of the UWB receiver front-end
Table A.2 Comparison of recently UWB front-end circuit
# at 5 GHz Reference
Specification
This Work . Sim.
Process CMOS 0.18um
Band Width 3.1-8.1
Supply Voltage(V) 1.5
RF Return Loss <-10
LO Power (dBm) -5
Conversion Power Gain 19-21.5
DSB NF 4.3-6.2
Total Power (mW)
CMOS 3.1-10.6 1.5 22.9~26.4 4.8-7.7 -11.3 57.6 [25] 2005
(Meas.)
0.25um
SiGe 3.1-10.6 2.7 20.6~21.8 4.1-6.2 -12.8 83
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Vita and Publication
姓 名: 熊子豪 學 歷:
國立新竹高級中學 ( 87 年 9 月 ~ 90 年 6 月)
私立逢甲大學電子工程學系 ( 90 年 9 月 ~ 94 年 6 月) 國立交通大學電信工程所碩士班 ( 94 年 9 月 ~ 96 年 6 月)
Publication Remarks:
1. Zi-Hao Hsiung and Christina F. Jou, “Novel Wideband CMOS LNA with Only an inductor as input matching network”, IEEE TENCON Conference, October 30 – November 2, 2007, Taipei, Taiwan.
2. Hui-I Wu, Zi-Hao Hsiung and Christina F. Jou, “A 0.75V CMOS Low-Noise Amplifier for Ultra Wide-band Wireless Receiver”, PIERS 26-30 March, 2007 in Beijing, China.
3. Win-Ming Chang, Zi-Hao Hsiung, Christina F. Jou “Ka-band 0.18 um CMOS low noise amplifier with 5.2 dB noise figure” Microwave and optical technology letters, Published Online: 27 Mar 2007 (p 1187-1189)