Chapter 1 Introduction
1.3 Thesis Organization
There are six chapters in this dissertation. This thesis is organized as follow:
In chapter 1, the overview of our study and motivations of this thesis are described.
In chapter 2, the introduction of the UHVCVD system instrument used in our experiments. We have fabricated high-quality relaxed SiGe films using an intermediate Si interlayer within the channel region and SiC films.
In chapter 3, we have investigated planarization of rough surfaces of strain-relaxed Si0.8Ge0.2 buffer layer by CMP and post-CMP cleaning. The effects of polish pad conditions and slurry solid contents on SiGe CMP process were investigated. By optimizing the polishing conditions, the smooth strained-Si surface on flatten Si0.8Ge0.2 buffer layer of 0.6 nm can be achieved. The novel cleaning solutions with various surfactants and chelating agents for post-CMP SiGe were studied. The surfactant (TMAH) and chelating agent (EDTA) into the diluted ammonium solution, removal efficiency of particles and metallic impurities is increased.
In chapter 4, we have demonstrated the fabrication of Dynamic Threshold voltage MOSFET (DTMOS) using the Si1-yCy (y=0.005) incorporation interlayer channel.
Compare to conventional Si-DTMOS, the introduction of the Si1-yCy interlayer for this device is realized by super-steep-retrograde (SSR) channel profiles due to the retardation of boron diffusion. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. We have developed a novel n-channel Si1-yCy interlayer heterostructure DTMOS structure.
In chapter 5, we demonstrate the fabrication process and the electrical characteristics of n-channel polycrystalline silicon Thin-Film Transistors with different numbers of channel stripes. Poly-Si TFTs with multiple channels have better performance than conventional TFTs. Then, we fully discuss about the reliability of poly-Si TFTs with multiple channels. The effects of the number of channel stripes in multi-channel TFTs on performance and reliability have been investigated. For the fabrication of highly reliable devices and to improve the yield of multi-channel TFTs, the channel structures must be carefully designed.
In chapter 6, the improvement of polycrystalline silicon germanium thin-film transistors (poly-SiGe TFTs) using NH3 passivation and chemical mechanical polishing (CMP) process was examined. Experimental results indicated that NH3
passivation could effectively improve the turn on characteristics.
Finally, conclusions of this dissertation and recommendation for further research are presented in chapter 7. The compatibility of the propose technology can meet the trend of process requirement. It is expected that the processes in this thesis can be good choices in the future deep-submicron generation.
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Chapter 2
Deposition of SiGe and SiC Epitaxy Films by Ultra-High Vacuum Chemical Vapor Deposition
(UHVCVD) System
2.1 Introduction
In the last few years, there has been significant interest in SiGe heteroepitaxial growth on silicon substrates, because Si/ SiGe hetero-structures allow band-gap engineering to be used in conjunction with silicon technology. Of particular interest are the pseudomorphic p-type Si1−xGex channel (x =10-20%) modulation doped field effect transistor (MODFET), the n-type strained Si channel MODFET and the p-type strained Si1−xGex channel MODFET (x > 70%). Excellent review articles on these high mobility devices can be found in [1]-[5]. To minimize the number of threading dislocations inside the relaxed Si1−xGex buffer layer, it is customary to grow initially a rather thick linearly graded or step-graded SiGe layer (with a Ge composition close to zero at the beginning of the ramp and equal to x at the end of it), whose function is to accommodate gradually the lattice mismatch between Si and Si1−xGex, and thus confine the misfit dislocations inside the graded layer. The combination of a Si1−xGex
graded layer followed by a relaxed constant composition Si1−xGex buffer layer is called a virtual substrate.
Strain improves MOSFET drive currents by fundamentally altering the band structure of the channel and can therefore enhance performance even at aggressively scaled channel lengths. A relaxed Si1−xGex graded buffer creates a larger lattice constant on a Si substrate (i.e., “virtual substrates”) and can be used as an epitaxial
template for depositing Si-rich layers in a state of biaxial tension or Ge-rich layers in a state of biaxial compression. While uniaxial strain in the channel region of bulk Si MOSFETs can be intentionally induced during device processing, Si1−xGex virtual substrates allow for the fabrication of wafer-scale strained layers that can confine holes or electrons. Such band-engineered heterostructures can be optimized to allow mobility enhancement factors over bulk Si of 2 for electrons and as high as 10 for holes.
The 4.2% difference in the lattice constants of Si and Ge atoms can be used to create high-mobility strain-engineered devices. Electron mobility is enhanced in strained-Si compared with bulk-Si due to tensile strain splitting the six-fold degenerate conduction band valleys and causing the resulting two-fold band with lower energy and reduced in-plane effective mass to be preferentially filled [6]. A four-fold band with increased energy is also created, which additionally contributes to the higher electron mobility through a reduction in intervalley scattering. Tensile strained-Si layers are, thus, useful for electron channels of high mobility n-MOSFETs.
Epitaxial growth of Si on relaxed SiGe alloys creates such strained-Si layers due to the larger atomic spacing of Ge, and consequently relaxed SiGe alloys [7], compared with Si. Hole transport is improved in both tensile strained-Si and compressively strained-SiGe compared with bulk-Si. Modifications to the electronic band structure and a reduction of the hole effective mass have been found to increase mobility in strained-SiGe by five times [8]. Epitaxial growth of SiGe on either bulk-Si or relaxed SiGe alloys with a lower Ge content than the growing film can produce compressively strained-SiGe. There are some challenges in using strain to enhance the performance of CMOS devices and many of these are related to the critical thickness of a strained-layer [9]. If a strained-layer is grown above the critical thickness, strain
relaxes with the introduction of misfit defects at the strained-Si-SiGe hetero-interface and the enhanced transport properties arising from the strain are lost. Minimizing the exposure of the strained-material to high thermal budgets during processing reduces the probability of material degradation, since high temperatures cause strain to relax.
However, non-optimized processing conditions may lead to degraded extrinsic performance [10]-[12]. Reducing the thickness of the strained-layer may protect the material against strain relaxation, but very thin channel layers compromise the performance gains achievable [13]. Dual-channel structures [14] minimize the cumulative strain within the devices by the sequential growth of tensile and compressively strained-layers, thereby allowing higher thermal budgets to be used before the onset of strain relaxation. The strain-compensation within the dual channel structure can alternatively be traded off against thicker strained-channel layers. By growing a compressive strained-SiGe layer followed by a tensile strained-Si layer on a single-relaxed SiGe “virtual substrate,” the band offsets between the oppositely strained-materials can be used to create high mobility surface n- and buried p-channel MOSFETs. This dual-channel CMOS architecture has been shown theoretically to maximize the transconductance of both n- and p-channel devices for a range of achievable mobilities [15]. The benefits of using dual-channel device architectures have recently received attention [14]-[18]. Rim et al. have investigated p-channel performance in dual-channel architectures using a compressively strained-SiGe layer below a tensile strained-Si layer [16], but have only provided a limited assessment of electron mobility in such structures. Researchers at the Massachusetts Institute of Technology (MIT) have considered dual-channel structures with a view to optimizing buried p-MOS devices using relaxed Si Ge virtual substrates (VS), with [8], [17], [18], concluding that surface electron mobility is not influenced by the presence of a compressive SiGe buried p-channel layer. However, the devices had long channel
lengths and were fabricated using a low thermal budget process, unlike conventional CMOS. Optimizing the VS for n-channel performance is paramount, since n-MOSFETs often dominate circuit speed. Previously reported strained-Si n-channel MOSFETs fabricated using a high thermal budget on a dual-channel architecture, which was designed for obtaining high n-channel performance [14]. The devices were fabricated on ultrahigh vacuum chemical vapor deposition (CVD) virtual substrate material and demonstrated some of the highest performance gains reported to date compared with unstrained-Si control devices over a wide range of gate lengths.
However, the primary aim of incorporating the buried strained-SiGe layer is to
However, the primary aim of incorporating the buried strained-SiGe layer is to