Device Characteristics

In Fig. 3.7, the current vs. electric voltage of the MOS capacitor cleaned by four solutions are shown. The MOS capacitor using SC1+TE solution depicts the lowest leakage current and highest breakdown voltage among these four samples. It is obviously seen that SC1 and SC1+T samples exhibits the second breakdown effect and it could be due to the metallic and particle containment shown in Fig. 3.5 and 3.6.

Figure 3.8 shows the Weibull plot of leakage current measured at 3 Volts. The breakdown voltage distribution is shown in Fig. 3.9. A constant current stressing is used to investigate the gate oxide integrate. The charge to breakdown (Qbd) measurements were performed on the post-CMP cleaning samples. The distribution for solution SC1+TE shows high Qbd that can be attributes to efficient removal the particle and metal contaminations on strained-Si MOS capacitors. And we also applied it in MOSFET fabrications. The output characteristics of devices with channel length of 5 μm are shown in Fig. 3.11, the drain current increased about 10 % between SC1 and SC1+TE samples. The novel cleaning solutions with TMAH and EDTA showed the improvements which indicated that this solution for post-CMP on SiGe virtual substrates is a critical technique for developing high performance strained-Si MOSFET.

3.4 Summary

We have investigated planarization of rough surfaces of strain-relaxed Si0.8Ge0.2

buffer layer by CMP and post-CMP cleaning. It was found that soften polish pad can be eliminated SiGe surface roughness. The optimum conditions can achieve the strained-Si surface roughness of 0.6 nm. For the post-CMP cleaning process, various cleaning solutions have been applied to the SiGe buffer layer. By adding the surfactant (TMAH) and chelating agent (EDTA) into the diluted ammonium solution, removal efficiency of particles and metallic impurities is increased. The electrical performances of capacitors such as breakdown voltage, leakage current and Qbd are significantly improved for post-CMP cleaning. Furthermore, the optimal condition of SC1+TE sample has increased about 10 % in drive current. This post-CMP cleaning process is useful for planarization of strain-relaxed SiGe virtual substrates in MOSFET application.

References:

[1] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald and D. A. Antoniadis, “Strained silicon MOSFET technology,”in IEDM Tech.

Dig., 2002, pp. 22-26.

[2] P. M. Mooney, J. L. Jordan-Sweet, K. Ismail, J. O. Chu, R. M. Feestra, and F. K.

LeGoues, “Relaxed Si0.7Ge0.3 buffer layers for high-mobility devices,” Appl.

Phys. Lett., vol. 67, no.16, pp. 2373-2375, 1995.

[3] T. Ueno, T. Irisawa, Y. Shiraki, A. Uedono and S. Tanigawa, “Low temperature buffer growth for modulation doped SiGe/Ge/SiGe heterostructures with high hole mobility,” Thin Solid Films, vol. 369, pp. 320-323, 2000.

[4] K. Sawano, K. Kawaguchi, T. Ueno, S. Koh, K. Nakagawa and Y. Shiraki,

“Surface smoothing of SiGe strain-relaxed buffer layers by chemical mechanical polishing,” Mater. Sci. Eng. B, vol. 89, no.1-3, pp. 406-409, 2002.

[5] K. Sawano, K. Arimoto,Y. Hirose, S. Koh, N. Usami , K. Nakagawa, T. Hattori , and Y. Shiraki, “Planarization of SiGe virtual substrates by CMP and its application to strained Si modulation-doped structures,” J. Cryst. Growth, vol.

251, no.1-4, pp. 693-696, 2003.

[6] K. Sawano, K. Arimoto, Y. Hirose, S. Koh, N. Usami, K. Nakagawa, I. Hattori, Y.

Shiraki, “Planarization of SiGe virtual substrates by CMP and its application to strained Si modulation-doped structures,” in Conf. Molecular Beam Epitaxy, 2002, pp. 15-20.2002.

[7] N. Sugii, D. Hisamoto, K. Washio, N. Yokoyama and S. Kimura, “Enhanced performance of strained Strained-Si MOSFETs on CMP SiGe virtual substrate,”

in IEDM Tech. Dig., 2001, pp. 33.4.1-33.4.4.

[8] K. Sawano, S. Koh, Y. Shiraki, Y. Hirose, T. Hattori, and K. Nakagawa, “Mobility

enhancement in strained Si modulation-doped structures by chemical mechanical polishing,” Appl. Phys. Lett., vol. 82, pp. 412-415, 2003.

[9] N. Sugii, D. Hisamoto, K. Washio, N. Yokoyama and S. Kimura, “Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical- polished SiGe substrate,” IEEE Trans. Electron Devices, vol. 49, no. 12, pp.

223-2243, 2002.

[10] M. T, Currie, C. W. Leitz, T. A. Langdo, G. Taraschi, E. A. Fitzgerald and D. A.

Antoniadis, “Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates,” J. Vac. Sci. Technol. B, vol.19, no. 6, pp.

2268-2279, 2001.

[11] N. Miyashita, M. Shimomura, Y. Minami, I. Katakabe, H. Nojo, H. Ohashi and M.

Abe, “A new post CMP cleaning method for trench isolation process,” ISMIC’96, 1996, p.161.

[12] K. Sawano, K. Kawaguchi, S. Koh, Y. Hirose, T. Hattori, K. Nakagawa and Y.

Shiraki, “Surface Planarization of Strain-Relaxed SiGe Buffer Layers by CMP and Post Cleaning,”J. Electrochem. Soc., vol. 150, pp. G376-G379, 2003.

[13] T. P. Pan, T. F. Lei, T. S. Chao, M. C. Liaw, F. H. Ko and C. P. Lu, “One-step cleaning solution to replace the conventional RCA two-step cleaning recipe for pre-gate oxide cleaning,” J. Electrochem. Soc., vol. 148, pp. G315-G319, 2001.

[14] T. M. Pan, T. F. Lei, C. C. Chen, T. S. Chao, M. C. Liaw, W. L. Yang, M. S. Tsai, C. P. Lu, W. H. Chang, “Novel cleaning solutions for polysilicon film post chemical mechanical polishing,” IEEE Electron Device Lett., vol. 21, no. 7, pp.

338-340, 2003.

[15] T. M. Pan, T. F. Lei, F. H. Ko, T. S. Chao, T. H. Chiu, Y. H. Lee, C. P. Lu,

“Comparison of novel cleaning solutions with various chelating agents for post-CMP cleaning on poly-Si film,” IEEE Trans. Semiconductor Manufacturing,

vol. 14, no. 4, pp. 365-371, 2001.

[16] S. W. Lee, P. S. Chen, M. –J. Tsai, C. T. Chia, C. W. Liu, and L. J. Chen, “The growth of high-quality SiGe films with an intermediate Si layer,” Thin Solid Films, vol. 447, pp. 302-305, 2004.

[17] W. Kern, Handbook of Semiconductor Wafer Cleaning Tech., p. 152, Park Ridge, (1993).

Table 3.1 Different slurry and pad conditions for Ge01, Ge02, Ge03 and Ge04 samples.

Slurry condition Pad condition

Slurry : H2O 1 : 9

Slurry : H2O 1 : 18

Politex pad Ge01 (AFM R.M.S.) 20.6 Å → 2.52 Å

Ge03 (AFM R.M.S.) 25.3 Å → 3.39 Å

IC1400 pad Ge02 (AFM R.M.S.) 22.1 Å → 2.69 Å

Ge04 (AFM R.M.S.) 22.3 Å → 3.59 Å

(a)

(b)

(c)

(d)

Fig. 3.1 AFM images of strained-relaxed SiGe buffer layers before CMP process.

Different slurry and pad conditions for (a)Ge01, (b)Ge02, (c)Ge03 and (d)Ge04 samples.

(a)

(b)

(c)

(d)

Fig. 3.2 AFM images of strained-relaxed SiGe buffer layers after CMP process.

Different slurry and pad conditions for (a)Ge01, (b)Ge02, (c)Ge03 and (d)Ge04 samples.

0

Fig. 3.3 Removal rate of (a) time dependent and (b) pressure dependent in SiGe layers.

(a)

(b)

Fig. 3.4 AFM images of strained-Si surfaces without and with CMP process. The RMS values are (a) without CMP 1.8 nm and (b) with CMP process 0.6 nm respectively.

0 200 400 600 800 1000

SC1 SC1+T SC1+E SC1+TE

Particle Number(particles)

Clean Solution

Fig. 3.5 Particle residual number on post-CMP cleaning surface of SiGe buffer layers in different solutions.

10¹⁰ 10¹¹ 10¹²

K Ca Fe Cu Zn

SC1 SC1+T SC1+E SC1+TE

Metallic Impurity Concentration (atom/cm2 )

Element

Fig. 3.6 The metallic contaminant concentration on SiGe buffer layer by TXRF.

10^-14 10^-12 10^-10 10^-8 10^-6 10^-4 10^-2

0 5 10 15 20

SC1 SC1+T SC1+E SC1+TE

I (A)

V (V)

Fig. 3.7 The current vs. voltage characteristic of MOS capacitors with 20 nm TEOS oxide on the strained-Si with different cleaning method.

-3 -2 -1 0 1 2 3

20 40 60 80 100 120

SC1 SC1+T SC1+E SC1+TE

ln(-ln(1-p))

Leakage current @3v (pA)

Fig. 3.8 The cumulative distribution of leakage current of MOS capacitors with different cleaning method.

-3 -2 -1 0 1 2 3

0 5 10 15 20 25

SC1 SC1+T SC1+E SC1+TE

ln(-ln(1-p))

Ebd (V)

Fig. 3.9 Distribution of breakdown voltage distribution of MOS capacitors.

-3 -2 -1 0 1 2 3

0 5 10 15 20

SC1 SC1+T SC1+E SC1+TE

ln(-ln(1-p))

Qbd (C/cm²)

Fig. 3.10 The charge-to-breakdown of MOS capacitors under constant current stress in four kinds of different solutions.

0 0.005 0.01 0.015 0.02 0.025 0.03

0 2 4 6 8

SC1 SC1+TE

ID (A)

VD(V)

W/L=40um/5um VG-Vt=2~8 V Tox=200A

Fig. 3.11 The current enhancement of 10 % between SC1 and SC1+TE samples.

ID~10 %

Chapter 4

A Novel Dynamic Threshold Voltage MOSFET (DTMOS) Using Heterostructure Channel of

Si

_1-y

C

_y

Interlayer

4.1 Introduction

As MOS devices continue to be scaled down, the low supply voltage is desirable to minimize the power consumption. The Dynamic Threshold MOSFET (DTMOS) structure offers a promising technology to achieve both high speed and low power performance [1], [2]. By shorting the gate to the body, the threshold voltage operating under the DT-mode is reduced by forward biasing of the body, so its current drive can be significantly enhanced in the on state. In addition, the subthreshold swing could be attaining to the ideal value (~60 mV/dec.). To enhance the driver current under DT-mode, large body factor, γ, is necessary to increase the threshold voltage reduction. Theγ factor was strongly depended on the substrate impurity doping concentration. In order to take full advantage of the high current drive inherent in DTMOS, Chang et al. proposed the use of super-steep-retrograde (SSR) indium-channel profile [3], [4]. On the other hand, Takagi et al. also proposed a novel SiGe channel heterostructure DTMOS for reducing the threshold voltage in spite of keeping impurity doping level at the body region [5].

Transient enhanced diffusion (TED) of boron and phosphorus during annealing of implantation damage can be suppressed by incorporation of substitutional carbon [6]-[9]. Si1-yCy layer have been applied to suppress boron diffusion in hetero-junction

bipolar transistors (HBT) [10], [11]. The incorporation of substitutional carbon in silicon can reduce fast diffusion spices of boron diffusion in silicon. An explanation for this behavior has been provided that the substitutional carbon present in the silicon substrate acts as the sink for silicon self-interstitial and the carbon spices are displaced by the silicon self-interstitial during thermal treatment processes. In this paper, a novel Si1-yCy heterostructure n-channel DTMOS with boron implantation was studied.

Compare to those two samples, with and without Si1-yCy interlayer, it shows superiority over conventional DTMOS. We have successfully achieved the low threshold voltage and heavily doped substrate DTMOS with superior characteristics in terms of the higher transconductance and saturation current.

4.2 Experimental

Two samples, with and without (w/o) carbon incorporation, were prepared.

Samples in this study were grown epitaxially on (100) silicon wafer in ultra high vacuum chemical vapor deposition (UHVCVD) system with a thin 5 nm Si1-yCy

(y=0.005) layer and 30 nm silicon cap layer. The substrates were implanted with 2×

10¹³ cm^-2 BF₂ at 75 keV and annealed at 950℃ for 30 s. The 6 nm gate oxide was grown, followed by the deposition of a 200 nm polysilicon gate. After gate patterning, a self-aligned n+ poly Si gate and source/drain ion implantation with P of 1E15 cm^-2 was formed at 40 keV. The body contact junction was implanted and annealed by BF2

in the rapid thermal process (RTP) system at the same substrate annealing conditions.

Afterwards, a passivation layer was deposited and patterned to complete contact metallization. The gate and body contacts were provided separately. Electrical characteristics were performed using a HP4156 system.

4.3 Results and Discussion

The channel profiles were measured by the secondary ion mass spectroscopy (SIMS) for with and without Si1-yCy layer shown in Fig. 4.1 This profiles were measured after all thermal cycles. Compare to control sample, the samples with the Si1-yCy layer exhibit a super-steep-retrograde channel profile. In the presence of carbon, the boron concentration was dropped from 1.8×10¹⁸cm^-3 to ~10¹⁷cm^-3 over a distance of 30 nm. By introducing carbon atom, the carbon significantly reduces TED of boron atom. The substitutional carbon provides a sink for excess interstitials in crystalline Si which suppressing interstitial-enhanced boron diffusion. The efficacy of incorporation carbon has been attributed to its ability to locally suppress the silicon self-interstitial concentration [6]-[9].

From SIMS analyses (shown previously in Fig. 4.1), the sample with Si1-yCy

layer has lower surface dopant concentration than the control sample while they have the same substrate doping concentration. It can therefore have a higher bulk impurity and does not increase the threshold voltage (Vth). Fig. 4.2 shows the body effects of n-channel MOSFET with and without Si1-yCy interlayer samples. A separate terminal was used to control the body voltage. The threshold voltage at zero body bias is denoted for its initial threshold voltage. They have almost the same slope because of its similar substrate concentration. However, the surface concentration for the Si1-yCy

sample is lower than that of w/o Si1-yCy interlayer samples. We found the Si1-yCy

sample indeed depicts a lower threshold voltage for lightly doped channel surface.

Fig. 4.3 shows the drain current versus gate voltage in subthreshold region which the device size is W/L=10μm/5μm. The drain voltage was 0.1 V. In the DT-mode operation, the gate and body contacts are tied to together (i.e., VG=Vsub) and standard

mode operation (i.e., Vsub=0 V). The subthreshold swing for both samples show nearly ideal value (about 60 mV/dec.) which has been explained by Assaderaghi et al.[2].

Corresponding transconductance (Gm) is also shown in Fig. 4.3, it shows 1.2 times higher Gm between with and w/o Si1-yCy samples. We believe this is due to the lower surface doping concentration and the larger body factor of Si1-yCy sample. A low impurity surface channel and the heavily doped body enhances the body bias effect, and devices show the combination of low Vth and high body factor, simultaneously. In addition, in both operation modes, the Gm shows it superiority over the sample w/o Si1-yCy interlayer. From Fig. 4.1 and 4.2, the channel surface impurity doping concentration determines the impurity scattering phenomenon. The output characteristics of with and w/o Si1-yCy layer under standard and DT-mode operation varies from 0.2 V to 0.7 V with a 0.1 V step. The current drives of those two samples in the standard and DT-mode for the device size of W/L=10μm/5μm were shown in Fig. 4.4 (a) and (b), respectively. The drain current for the sample with Si1-yCy layer is 1.8 times larger than that of Si DTMOS. In addition, the saturation current under DT-mode was larger than that under standard mode. It is worthy to note here that the disaster under DT-mode in VG=0.7 V was due to the leakage current between the substrate and source terminals diode, which limit the operation voltage of DT-mode to VG < 0.7 V.

4.4 Summary

We have developed a novel n-channel Si1-yCy interlayer heterostructure DTMOS structure. This layer could effectively reduce the diffusion of boron beneath the channel region. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. The excellent performances obtained in the Si1-yCy interlayer

DTMOS are due to both the same substrate doping concentration and lower channel surface impurity concentration. So its surface impurity scattering could be reduces and it can offer a superior performance in future scaled devices. This device achieves 1.2 times higher Gm and 1.8 times larger drain current. It appears to be a very promising technology for nano-scale device and ultra-low voltage application.

References:

[1] F. Assaderaghi, D. Sinitsky, S. Paske, J. Boker, P. K. Ko, and C. Hu, “A dynamic threshold voltage (DTMOS) for ultra-low voltage operation,” in IEDM Tech.

Dig., Dec. 1994, pp. 809–812.

[2] F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, C. Hu,” Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI,” IEEE Trans.

Electron Devices, vol. 44, pp. 414–422, Mar. 1997.

[3] S. J. Chang, C. Y. Chang, C. Chen, T. S. Chao, Y. J. Lee,and T. Y. Huang,”

High-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel,” IEEE Trans. Electron Devices, vol. 47, pp.

2379–2384, Dec. 2000.

[4] S. J. Chang, C. Y. Chang, T. S. Chao, and T. Y. Huang,” High performance 0.1 µm dynamic threshold MOSFET using indium channel implantation,” IEEE Electron Device Lett., vol.21, pp. 127–129, Mar. 2000.

[5] T. Takagi, A. Inoue, Y. Hara, Y. Kanzawa, and M. Kubo, “A novel high performance SiGe channel heterostructure dynamic threshold pMOSFET (HDTMOS),” IEEE Electron Device Lett., vol.22, pp. 206–208, May 2001.

[6] P. A. Stolk, D. J. Eaglesham, H.-J. Gossmann, and J. M. Poate, “Carbon

incorporation in silicon for suppressing interstitial-enhanced boron diffusion,”

Appl. Phys. Lett., vol. 66, pp. 1370–1372, Mar. 1995.

[7] H. Rucker, B. Heinemann, W. Ropke, R. Kurps, D. Kruger, G. Lippert, and H. J.

Osten, “Suppressed diffusion of boron and carbon in carbon-rich silicon,” Appl.

Phys. Lett., vol. 73, pp. 1682–1684, Sep. 1998.

[8] H. Rucker, B. Heinemann, D. Bolze, R. Kurps, D. Kruger, G. Lippert, and H. J.

Osten, “The impact of supersaturated carbon on transient enhanced diffusion,”

Appl. Phys. Lett., vol. 74, pp. 3377–3379, May 1999.

[9] M. S. Carroll and J. C. Sturm, “Quantification of substitutional carbon loss from Si0.998C0.002 due to silicon self-interstitial injection during oxidation,” Appl.

Phys. Lett., vol. 81, pp. 1225–1227, Aug. 2002.

[10] L. D. Lanzerotti, J. C. Sturm, E. Stach, R. Hull, T. Buyuklimanli, and C. Magee,

“Suppression of boron outdiffusion in SiGe HBTs by carbon Incorporation,” in IEDM Tech. Dig., Dec. 1996, pp. 249–252.

[11] H. J. Osten, G. Lippert, D. Knoll, R. Barth, B. Heinemann, H. Rucker, and P.

Schley, “The effect of carbon incorporation on SiGe Heterobipolar Transistor performance and process margin,” in IEDM Tech. Dig., Dec. 1997, pp.803–806.

10¹⁶ 10¹⁷ 10¹⁸

0 50 100 150 200

0 0.1 0.2 0.3 0.4 0.5

Boron w/o SiC Boron with SIC

Carbon

CONCENTRATION (atoms/cm3 ) ION COUNTS

DEPTH (micron)

Boron

Carbon

Fig. 4.1 SIMS measurements of boron and carbon diffusion profile in the channel region.

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-0.2 0 0.2 0.4 0.6 0.8 1

SiC layer w/o SiC

Threshold Voltage (V)

Body bias (V)

Fig. 4.2 Threshold voltage versus different body bias for a W/L=10μm/5μm NMOSFET.

10^-14

Drain Current (A) Gm (mS/mm)

Gate Voltage (V)

W/L=10μm/5μm Vd=0.1 V

Fig. 4.3 Subthreshold characteristics of NMOSFET under standard-mode and DT-mode. Drain current and transconductance (Gm) for the samples with and without Si1-yCy layer.

0 0.5 1 1.5 2

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 w/o SiC

w/o SiC DT-mode

Drain Current (μΑ/μm)

(a) (b) Drain Voltage (V)

W/L=10μm/5μm Vg=0.2~0.7 V

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 SiC

SiC DT-mode

Fig. 4.4 Drain current of (a) without Si_1-yC_y , and (b) with Si_1-yC_y devices in standard-mode and DT-mode. Gate voltage varies from 0.2 to 0.7 V in 0.1 V step.

Chapter 5

Electrical Characteristics and Reliability of Multi-channel Polycrystalline Silicon Thin-Film

Transistors

5.1 Introduction

Polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted much interest because of the possibility of integrating driving circuits and pixel elements.

Poly-Si TFTs have many advantages compared with conventional amorphous-Si TFTs, including a higher driving current and greater carrier mobility. It is known that the existence of grain boundaries within the poly-Si channel region has great influence on the electrical characteristics of poly-Si TFTs [1], [2]. Some previous research reports have discussed the large number of grain boundary trap states in the poly-Si channels, and localized potential barriers are produced for the transportation of carriers from grain to grain [3]-[5]. Many suggestions have been proposed, and it have been revealed that poly-Si TFTs with narrow channels have better performance in terms of lower threshold voltage [6], smaller subthreshold swing [7], and effective kink effect suppression due to the reduction of grain boundary trap states. It has been concluded that the density of grain boundary trap states existing in the channel near the pattern edge is much lower than elsewhere. As the channel width is scaled down, the effect of the poly-Si pattern edge becomes dominant. Additionally, it has also been reported that the kink effect can be enhanced by the existence of grain boundary trap states [8], [9]. A larger number of grain boundary trap states causes a more severe impact

Moreover, the gate electrode across the channel may induce side-channels in both sides of the channel region, and these side-channels may increase the effective channel width. Especially when the channel width is scaled down, the side-channel effect is more distinct. The average carrier concentration in the channel region of the corner of the poly-Si gate electrode is increased by electrostatic focusing from the top gate and both side gates of the stripes [10]. It is believed that the gate control capability was obviously improved in narrow width devices. Accordingly, poly-Si TFTs with narrow and multiple channels have been proposed to enhance electrical characteristics [11]-[13]. However, no complete reliability analysis has been carried out in the poly-Si TFTs with narrow and multiple channels.

In this study, we demonstrate the fabrication process and the electrical characteristics of n-channel poly-Si TFTs with different channel stripes. Poly-Si TFTs with multiple channels have better performance than conventional TFTs. Finally, we fully discuss about the reliability of poly-Si TFTs with multiple channels.

5.2 Experimental

Figure 5.1 shows the process flow of the proposed poly-Si TFTs. First, 500-nm-thick thermal oxide was grown on the Si wafer using a furnace system. All experimentals devices in this study were fabricated on thermally oxidized Si wafers.

Then, 100-nm-thick amorphous silicon layers were deposited on the thermal oxide layer using low-pressure chemical vapor deposition (LPCVD) at 550°C. Then, amorphous silicon films were recrystallized by solid phase crystallization (SPC) at 600°C for 24 h in an N₂ ambient to form poly-Si films. Poly-Si films were patterned into active regions by transformer coupled plasma (TCP) etching using a gas mixture of Cl₂ and HBr.

After RCA cleaning, a 100-nm-thick tetraethylorthosilicate (TEOS) oxide was deposited by LPCVD with TEOS and O2 gases at 695°C to form the gate insulator. A 200-nm-thick poly-Si was deposited to serve as the gate electrode by LPCVD at 595°C. Then, the poly-Si film was patterned and etched by TCP etching to form the gate electrode, and the gate oxide on the source/drain was removed using dilute HF solution. The regions of source, drain, and gate were doped by self-aligned phosphorous ion implantation at a dosage and energy of 5×10¹⁵ cm^-2 and 40 keV, respectively. Dopant activation was performed by rapid thermal annealing (RTA) at 700°C for 20 s, followed by the deposition of a 400-nm-thick passivation oxide using PECVD at 350°C and the definition of contact holes. Finally, a 500-nm-thick Al was deposited by sputtering and patterned for metal pads, and devices were passivated by

After RCA cleaning, a 100-nm-thick tetraethylorthosilicate (TEOS) oxide was deposited by LPCVD with TEOS and O2 gases at 695°C to form the gate insulator. A 200-nm-thick poly-Si was deposited to serve as the gate electrode by LPCVD at 595°C. Then, the poly-Si film was patterned and etched by TCP etching to form the gate electrode, and the gate oxide on the source/drain was removed using dilute HF solution. The regions of source, drain, and gate were doped by self-aligned phosphorous ion implantation at a dosage and energy of 5×10¹⁵ cm^-2 and 40 keV, respectively. Dopant activation was performed by rapid thermal annealing (RTA) at 700°C for 20 s, followed by the deposition of a 400-nm-thick passivation oxide using PECVD at 350°C and the definition of contact holes. Finally, a 500-nm-thick Al was deposited by sputtering and patterned for metal pads, and devices were passivated by

在文檔中 矽鍺與矽碳薄膜應用於金氧半場效電晶體和複晶矽鍺與多通道薄膜電晶體之研究 (頁 54-0)