Conclusions

In this thesis, the applications of these two kinks of epitaxy films were investigated. Planarization of rough surfaces of strain-relaxed Si_0.8Ge_0.2 buffer layer was done by CMP and post-CMP cleaning. It was found that soften polish pad can be eliminated SiGe surface roughness. The optimum conditions can achieve the strained-Si surface roughness of 0.6 nm. For the post-CMP cleaning process, various cleaning solutions have been applied to the SiGe buffer layer. By adding the surfactant (TMAH) and chelating agent (EDTA) into the diluted ammonium solution, removal efficiency of particles and metallic impurities is increased. The electrical performances of capacitors such as breakdown voltage, leakage current and Qbd are significantly improved for post-CMP cleaning. Furthermore, the optimal condition of SC1+TE sample has increased about 10 % in drive current. This post-CMP cleaning process is useful for planarization of strain-relaxed SiGe virtual substrates in MOSFET application.

We have developed a novel n-channel Si_1-yC_y interlayer heterostructure DTMOS structure. This layer could effectively reduce the diffusion of boron beneath the channel region. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. The excellent performances obtained in the Si1-yCy

interlayer DTMOS are due to both the same substrate doping concentration and lower channel surface impurity concentration. DTMOS have superior characteristics in terms of the higher transconductance and saturation current. So its surface impurity

devices. This device achieves 1.2 times higher Gm and 1.8 times larger drain current.

It appears to be a very promising technology for nano-scale device and ultra-low voltage application.

Next the application of poly-Si and poly SiGe were investigated. We demonstrate the fabrication process and the electrical characteristics of n-channel polycrystalline silicon Thin-Film Transistors with different numbers of channel stripes. The device’s electrical characteristics, such as on-current, threshold voltage, and subthreshold swing, were improved by increasing the number of channel stripes due to the enhancement of gate control. However, the electric field strength near the drain side was enlarged in multi-channel structures, causing severe impact ionization. The degradation of device’s reliability under various electrical stress conditions was suggested. A severe reliability was found which can be attributed to the enlargement of the electric field at drain side. Therefore, for the fabrication of highly reliable devices and to improve the yield of multi-channel TFTs, the channel structures must be carefully designed.

The improvement of poly-SiGe TFTs using NH3 passivation and chemical mechanical polishing (CMP) process was examined. Experimental results indicated that NH3 passivation could effectively improve the turn on characteristics. Moreover, the TFTs fabricated on polished poly-SiGe film exhibit higher carrier mobility, better subthreshold swing, lower threshold voltage, and higher on/off current ratio due to the smooth poly-SiGe interface.

7.2 Further Recommendations

There are some topics that are suggested for future work:

(1) For the post CMP cleaning solution, we can study the solution used in front end application, or the TFTs fabricated on polished poly-Si or SiGe film.

(2) We have developed a super-steep-retrograde (SSR) SiC interlayer channel profiles. For short channel device consideration, the SSR can provide a heavily substrate doping concentration and lower channel surface impurity concentration. An optimized, vertically and laterally nonuniform doping profile is needed to control the short-channel effect to substitute for super halo structure.

(3) Also, by the carbon retardation boron TED effect, we can develop an ultra shallow junction in this interlayer structure.

(4) We can use the LDD structure to alleviate the electrical field near the drain side in the multi-channel TFTs.

(5) Using various plasma treatments (CF₄, N₂O), and incorporation of nitrogen and fluorine can be used to improvement the SiGe TFT chatacteristics. And the surface roughness can also be improved by introducing an interlayer by high density plasma oxide, such as ECR, ICP.

(6) Instead of CMP process, a spin on chemical solution process can be used to reduce the poly-SiGe surface roughness.

Vita

姓名: 謝明山

性別: 男

出生: 民國 63 年 08 月 17 日

籍貫: 台灣省苗栗市

住址: 台北縣中和市秀朗路 3 段 10 巷 37 弄 10 號 2 樓

學歷: 私立逢甲大學電機系 [ 82 年 9 月- 86 年 6 月]

私立逢甲大學電機研究所碩士班 [ 86 年 9 月- 88 年 6 月]

國立交通大學電子研究所博士班 [ 88 年 9 月- 95 年 6 月]

博士論文題目:

矽鍺與矽碳薄膜應用於金氧半場效電晶體和複晶矽鍺與多通道薄膜

電晶體之研究

Study on SiGe and SiC Films in MOSFETs and Poly-SiGe and Multi-Channel Poly-Si in TFTs

Publication Lists

1. International Journal:

[1] Wen Luh Yang, Ming shan Shieh, Yu Min Chen, Tien Sheng Chao,Don-Gey Liu and Tan Fu Lei, “Improvement of Polysilicon Oxide Integrity Using NF3-Annealing,” Jpn. J. Appl. Phys., vol. 39, no. 6B, pp. L562-L565, 2000.

[2] M. S. Shieh, Y. J. Lin, C. M. Yu and T. F. Lei, “Characterization of Polysilicon Thin-Film Transistors with Asymmetric Source/Drain Implantation,” Nuclear Inst.

and Methods in Physics Research, B, Elsevier Science, 237(1), pp. 223-227, 2005.

[3] Ming-Shan Shieh, Pang-Shiu Chen, M. –J. Tsai and Tan Fu Lei, “The CMP Process and Cleaning Solution for Planarization of Strain-Relaxed SiGe Virtual Substrates in MOSFET Application,” Journal of Electrochemical Society, vol. 153, no. 2, pp. G144-G148, 2006.

[4] Ming Shan Shieh, Jen Yi Sang, Chih Yang Chen, Shen De Wang and Tan Fu Lei,

“Electrical Characteristics and Reliability of Multi-channel Polycrystalline Silicon Thin-Film Transistors,” Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 3159-3164, 2006.

[5] Ming-Shan Shieh, Chih-Yang Chen, Yuan-Jiun Hsu, Shen-De Wang, Wen-Luh Yang and Tan-Fu Lei, “Improved Silicon Germanium Thin Film Transistor Characteristics and Reliability by using Chemical Mechanical Polished,”

submitted to IEEE Trans. Dev. Mater. Rel..

[6] Chih-Yang Chen, Shen-De Wang, Ming-Shan Shieh, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh, Jam-Wen Lee and Tan-Fu Lei, “Plasma-Induced Damage on the Performance and Reliability of Low Temperature Polycrystalline Silicon Thin Film Transistors,” submitted to Journal of Electrochemical Society.

[7] Chih-Yang Chen, Jam-Wen Lee, Shen-De Wang, Ming-Shan Shieh, Po-Hao Lee, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh and Tan-Fu Lei, “Negative Bias Temperature Instability in Low Temperature Polycrystalline Silicon Thin Film Transistors,” submitted to IEEE Trans. on Electron Devices.

2. International Letter:

[1] Wen Luh Yang, Chih-Yuan Cheng, Ming-Shih Tsai, Don-Gey Liu, Ming-Shan Shieh, “Retardation in the Chemical-Mechanical Polish of the Boron-Doped Polysilicon and Silicon,” IEEE Electron Device Lett., vol. 21, no. 5, pp. 218-220, 2000.

[2] Ming-Shan Shieh, Pang-Shiu Chen, M.-J. Tsai and Tan-Fu Lei, “A Novel Dynamic Threshold Voltage MOSFET (DTMOS) Using Heterostructure Channel of Si_1-yC_y Interlayer,” IEEE Electron Device Lett., vol. 26, no. 10, pp. 740-742, 2005.

3. International Conference:

[1] M. S. Shieh, Y. J. Lin, C. M. Yu, T. F. Lei, “Characterization of Polysilicon Thin Film Transistors with Asymmetric Source/Drain Implantation,” 15th International Conference on Ion Implantation Technology (IIT 2004), pp. 150-151.

[2] Ming Shan Shieh, Jen Yi Sang, Chih Yang Chen, Shen De Wang, and Tan Fu Lei,

“The Characteristics and Reliability of Multi-channel Poly-Si TFTs,” Solid State Devices and Materials (SSDM 2005), 616-617.

[3] Ming-Shan Shieh, Chih-Yang Chen, Yuan-Jiun Hsu, Shen-De Wang, and Tan-Fu Lei, “Effect of Chemical Mechanical Polish Process on Low-Temperature Poly-SiGe Thin-Film Transistors,” IEEE International Reliability Physics Symposium (IRPS 2006), pp. 711-712.

[4] Chih-Yang Chen, Shen-De Wang, Ming-Shan Shieh, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh, Jam-Wen Lee and Tan-Fu Lei, “Plasma-Induced Instability and Reliability Issues in Low Temperature Poly-Si Thin Film Transistors,” IEEE International Reliability Physics Symposium (IRPS 2006), pp. 713-714.

[5] Yuan-Jiun Hsu, Ming-Shan Shieh, Chih-Yang Chen, Wen-Luh Yang and Tan-Fu Lei, “Performance Enhancement of Low Temperature Polysilicon Thin Film Transistor with Silicon Nitride Capping Layer,” submitted to Solid State Devices and Materials (SSDM 2006).

4. Local Conference:

[1] Ming Shan Shieh, Wen Luh Yang, Tien Sheng Chao and Don-Gey Liu, “The Characterization of Fluorine-Implanted Polysilicon Oxide,” Electron Devices and Materials Symposia (EDMS 1999), pp. 153-156.

[2] M. S. Shieh, Y. J. Hsu, S. D. Wang and T. F. Lei, “Electrical Characteristics of Polycrystalline SiGe Thin Film Transistors with Chemical Mechanical Polishing Process,” Electron Devices and Materials Symposia (EDMS 2005), p. 129.

[3] Po Hao Lee, Jen Yi Sang, Shen De Wang, Ming Shan Shieh and Tan-Fu Lei,

“The Lifetime of Poly-Si Thin-Film Transistors,” Electron Devices and Materials Symposia (EDMS 2005), p. 125.