Device reliability

Finally, the reliability of conventional and proposed poly-Si TFTs with single, 2, 4, 10, and 20 stripes in the same total channel width is discussed. The hot-carrier stress test was performed at VD,stress=15 V, VG,stress=10 V, with the source electrode

grounded for 200 s to investigate the device reliability. Figure 5.11 shows the variations in the on-state current (Ion) and threshold voltage (Vth) as a function of hot carrier stress time. The variations in I_on and V_th, were defined as (Ion,stressed－ Ion,initial)/Ion,initial×100% and (Vth,stressed－Vth,initial)/Vth,initial×100%, respectively, where Ion,stressed, Vth,stressed, I_on,initial, and Vth,initial represent the measured values before and after electrical stress. Generally, lower grain boundary trap state density causes slighter impact ionization under hot carrier stress, and hence the reliability of a device is improved. However, in Fig. 5.11, the degradation rate of the on-state current and threshold voltage deteriorated as the number of stripes in the poly-Si channel increased. Therefore, we discuss this phenomenon.

Figure 5.12 presents the trap state density in the poly-Si channel before and after 4 s, 10 s, and 100 s of hot carrier stress with conditions of VDS=15 V, VGS=10 V, and with the source electrode grounded. Figure 5.13 shows the increasing ratio of trap state density within the channel after 4 s, 10 s, and 100 s of electrical stress. It was clearly demonstrated that the trap state density after hot carrier stress increased as the number of poly-Si channel stripes increased. The electric field strength at the drain side of dual-gate poly-Si TFTs is larger than that of the single-gate poly-Si TFTs under the same bias conditions (VDS=15 V, VGS=10 V). This phenomenon will be more significant in the tri-gate poly-Si TFTs. Besides electric field strength near the drain, corner effect and sidewall roughness will also enhance the device’s degradation rate. Therefore, the electric field at the drain side was enlarged as the numbers of stripes in the poly-Si channel increased under hot carrier stress to cause severe impact ionization and hence to generate more trap states.

5.4 Summary

The effects of the number of channel stripes in multi-channel TFTs performance and reliability have been investigated. As the number of stripes increased, the electrical characteristics of devices were improved significantly due to the enhancement of gate control. However, a severe reliability was found which can be attributed to the enlargement of the electric field at drain side. Therefore, for the fabrication of highly reliable devices and to improve the yield of multi-channel TFTs, the channel structures must be carefully designed.

References:

[1] J. Levinson, F. R. Shepherd, P. J. Scalom, W. D. Westwood, G. Este, and M. Rider,

“Conductivity behavior in polycrystalline semiconductor thin film transistor,” J.

Appl. Phys., vol. 53, no. 2, pp. 1193-1202, 1982.

[2] J. G. Fossum and A. Ortiz-Conde, “Effects of grain boundaries on the channel conductancem of SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 30, no. 8, pp. 933-940, 1983.

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[7] H. W. Zen, T. C. Chang, P. S. Shih, D. Z. Peng, T. Y. Hwang, and C. Y. Chang,

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[9] H. W. Zan, P. S. Shih, T. C. Chang, and C. Y. Chang, “Dimensional effects on the reliability of polycrystalline silicon thin-film transistors,” Microelectronics Reliability, vol. 40, pp. 1479-1483, 2000.

[10] T. Takeshita, T. Unagami, and O. Kogure, “Study on narrow-stripe polycrystalline silicon thin-film transistors,” Jpn. J. Appl. Phys., vol. 27, no. 10, pp. 1937-1941, Oct. 1988.

[11] T. Unagami, and O. Kogure, “Large on/off current ratio and low leakage current poly-Si TFT’s with multichannel structure,” IEEE Trans. Electron Devices, vol. 35, no. 11, pp. 1986-1989, Nov. 1988.

[12] T. Unagami, “High-voltage poly-Si TFT’s with multichannel structure,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2363-2367, Dec. 1988.

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777-780, Dec. 2004.

[14] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M.

Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys., vol. 53, pp. 1193-1202, Feb. 1982.

[15] R. E. Proano, R. S. Misage, and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistors,” IEEE Trans.

Electron Devices, vol. 36, pp. 1915-1922, Sep. 1989.

• Wet oxide 5000Å by furnace

• a -Si channel 1000Å by LPCVD

• Poly-Si channel formation by SPC

• Gate oxide 500Å by LPCVD

• Poly Gate 2000Å by LPCVD

• S/D formation by ion implantation

• Passivation by PECVD

• Metal pad

Fig. 5.1 Process flow of conventional and multi-channel poly-Si TFTs.

Poly-Si

n

⁺

n

⁺

n

⁺

Buffer Thermal Oxide Si Wafer

Fig. 5.2 The cross-section of conventional and multi-channel poly-Si TFTs is parallel to the direction of the source and drain electrodes.

Poly-Gate

G1 G1

G2 G3

G3

Gox Gox

Channel Channel

Fig. 5.3 The cross-section of conventional and multi-channel poly-Si TFTs is perpendicular to the direction of the source and drain electrode.

S D G

(a)

S D

G

(b)

Fig. 5.4 Top view of (a) the conventional and (b) multi-channel poly-Si TFTs. The effective channel width Weff = 40μm ; channel length L = 2μm.

10^-11

Drain Currnet, I D (A)

Gate Voltage, V

G (V)

W/L = 40μm/2μm

VD = 1V Tox = 50nm

Fig. 5.5 Transfer characteristics of the conventional and the proposed multi-channel poly-Si TFTs with different stripes of channel.

0 5 10 15 20 25 30 35

-5 0 5 10 15 20

S1 M8 M20 M40

Fi el d Effe c t Mo bil ity , μ

eff

(cm

2

/V.s)

Gate Voltage, V

G

(V)

W/L = 40μm/2μm VD = 0.1V

Fig. 5.6 Field effect mobility of conventional and proposed multi-channel poly-Si TFTs with different number of stripes in the channel.

Table 5.1 Summary of device parameters of conventional and proposed multi-channel poly-Si TFTs (W/L = 40μm/2μm) with different numbers of stripes in the channel.

S1 M8 M20 M40

Vth(V) 9.65 9.33 8.97 8.67

S. S. (V/dec.) 1.257 1.230 0.987 0.923

µeff (cm²V^-1s^-1) 25.3 26.1 28.5 29.6 Ion at VG=20V (A) 2.76×10^-4 2.96×10^-4 3.44×10^-4 3.76×10^-4

Ioff at VG=-5V (A) 1.56×10^-11 1.56×10^-11 1.51×10^-11 1.43×10^-11 ON/OFF Ratio 1.79×10⁷ 1.91×10⁷ 2.37×10⁷ 2.89×10⁷ Nt (cm^-2) 5.80×10¹² 5.71×10¹² 5.40×10¹² 5.06×10¹²

-12.5 -12 -11.5 -11 -10.5

0.003 0.007 0.01

S1 M8 M20 M40 ln [ I

DS

/(V

GS

-V

FB

) ] (Ω

-1

)

1/(V

GS

-V

FB

)

²

(V

^-2

)

Nt=5.06x10¹²cm^-2

Nt=5.40x10¹²cm^-2 Nt=5.71x10¹²cm^-2 Nt=5.80x10¹²cm^-2

Fig. 5.7 Trap state density of conventional and proposed multi-channel poly-Si TFTs with different number of stripes in the channel.

0 5 10 15 20 25 30 35 40

0 10 20 30 40 50

Effective channel width On-state current

Per cent a g e (%)

Number of Channel Stripes

on-state current measured at VDS=1V ; V

GS=20V W/L = 40μm/2μm

Fig. 5.8 Increasing ratio of the effective channel width and the on-state current as a function of number of channel stripes.

0 0.1 0.2 0.3 0.4 0.5 6 0.6

0 2 4 6 8 10

S1 M8 M20 M40

Drain Current, I D (mA)

Drain Voltage, V

D(V) W/L = 40μm/2μm

VG - V

th = 0.5 ; 2 ; 3.5V

Fig. 5.9 Output characteristics of conventional and proposed poly-Si TFTs with different numbers of stripes in the channel. (VG – Vth = 0.5; 2; 3.5V).

1 10^-4

Drain Currnet, I D (A)

Gate Length (μm) Field Effect Mobility, μ eff (cm2 /V.s)

Gate Length (μm) W=40μm

VD=0.1V

(b)

8 8.5 9 9.5 10 10.5 11

0 2 4 6 8 10 12

S1 M8 M20 M40

Threshold Voltage (V)

Gate Length (μm) W=40μm

(c)

Fig. 5.10 (a) On-state current, (b) field effect mobility, and (c) threshold voltage as a function of different gate lengths with the number of channel stripes.

-100

Fig. 5.11 (a) On-current, and (b) threshold voltage degradation as a function of time under hot-carrier stress.

3 Trap State Density, N t (1012 cm-2 )

Number of Channel Stripe different numbers of channel stripes.

0 5 10 15 20 25 30 35 40

0 5 10 15 20 25

4 s 10 s 100 s

N t increasing ratio (%)

Number of Channel Stripe 20μm/2μm Stress condition VG=10V ; V

D=15V

Fig. 5.13 Increasing ratio of trap state density after 4 s, 10 s, and 100 s stress with different numbers of channel stripes.

Chapter 6

Effect of Chemical Mechanical Polish Process on Low-Temperature Poly-SiGe Thin-Film

Transistors

6.1 Introduction

Thin-film transistors (TFTs) have been widely used in various applications, such as static random access memories (SRAMs) [1], electrical erasable programming read only memories (EEPROMs) [2], linear image sensors [3], thermal printer heads [4], photodetector amplifier [5], scanner [6], and integrated driver transistors for active matrix liquid crystal displays (AMLCDs) [7]-[9].

Silicon germanium (SiGe) is a promising candidate for use as the TFT channel film, as it requires lower processing temperature than Si. Since the melting point of SiGe is lower than that of Si, the lower process temperature can be used for TFTs fabrication [10]-[13]. For low-temperature solid phase crystallization (LT-SPC) applications, SiGe is particularly advantageous, as it requires substantially shorter annealing cycles than required for the crystallization of Si. SiGe TFTs fabricated using scanned rapid thermal annealing (RTA) have also been demonstrated [14]. SiGe is advantageous for scanned RTA processes, as it requires lower crystallization temperatures, reducing glass warpage. To date, using conventional SPC processing with no pre-amorphization implant, SiGe TFT performance has generally been worse than poly-Si TFT performance [13]. SiGe TFT performance has been improved substantially through the use of thin Si interlayer to improve the gate oxide interface [15]. However, little has been done to improve the intrinsic quality of the SiGe

channel film itself; the binary nature of the SiGe system complicates optimization and modeling substantially. In previously described preliminary optimization of SiGe TFT’s through the use of multifactorial design of experiment techniques [16], [17].

However, the rough surface of channel causes the poor performance and the low reliability of the device. It is shown that a planarized polysilicon surface will yield TFTs with improved performance and reliability. The CMP process has been used extensively for smoothing surface of polysilicon films [18]-[23]. Thus it is possible to be applied to smooth the poly-SiGe films. In this study, we develop optimization strategies for fabrication of high-performance SiGe TFTs.

6.2 Experimental

The main process sequence for fabricating the poly-SiGe TFTs is illustrated in Fig. 6.1 The starting materials were 6-inch dummy wafers capped with a 500-nm-thick thermal oxide. Un-doped 100-nm- thick amorphous silicon germanium (Si1-xGex ,x =0.18) films were deposited by low-pressure chemical vapor deposition (LPCVD). Then the a-SiGe films were transformed into polysilicon phase by a solid-phase re-crystallization (SPC) treatment at 550 ℃ for 12hr. The films were then polished by CMP process. The parameters of CMP process condition were shown in Table 6.1. After definition of the active channel regions, a 50-nm-thick CVD oxide layer was deposited to form the gate oxide. Subsequently, the SiGe films were deposited and patterned to form the gate electrode. For n-channel transistors, P+

implant with a dosage of 5×10¹⁵ cm^-2 at 25 KeV was performed. The implanted dopants were activated in N2 ambient at 550 ℃. Next, a 300-nm-thick passivation oxide was deposited, followed by contact hole and aluminum pad formation. The samples were then subjected to the NH3 plasma treatment in various time periods.

Electrical characteristics were performed using a HP4156 system.

6.3 Results and Discussion

6.3.1 Device Characteristics

The surface roughness of the poly-SiGe films were examined by atomic force microscope (AFM). Fig. 6.2 shows the surface image of this film before and after CMP. It can be seen that CMP is very effective in smoothing the surface. The roughness of SiGe films are 4.75nm, 1.2nm and 0.35nm for unpolished and polished in 10 and 20 seconds, respectively.

Fig. 6.3 illustrates the I-V characteristics of unpolished TFTs with various NH3

plasma treatment times. The treatment results in superior electrical characteristics because of the grain boundaries passivation. The transfer curves of samples with and without CMP process are shown in Fig. 6.4. The observable improvements were not only due to the mobility enhancement, but also due to the significantly reduced leakage current with the reduction of surface roughness. The characteristics of with and without CMP process are shown in Table 6.2. The TFTs fabricated on polished poly-SiGe film exhibits higher carrier mobility, better subthreshold swing, lower threshold voltage, higher on/off current ratio and reduction of trap state density.

6.3.2 Extraction of density of state and reliability issues

To clarify how the nitrogen passivate the trap states of poly-Si TFTs, Fig.6.5 shows the density of states (DOS) in the band gap by field-effect conductance method

states are significantly reduced in the NH₃ treated TFT. SiGe-TFTs is required lower processing temperature than Si. It exists many dangling bonds and strain bonds at the SiO₂/poly-Si interface, resulting in high deep states and tail states [25], [26]. However, for the NH3 plasma treated TFT, nitrogen atoms were introduced into the SiO2/poly-Si network to terminate the dangling bonds, release the strain bonds and form the S-N or Si-H bonds. For the long time NH3 treated TFTs, nitrogen atoms were introduced into the interface reducing the trap state and resulting in a great improvement of device characteristics.

The hot-carrier stress test was performed at V_D=15V, V_G=10V, and source electrode grounded for 200 sec to investigate the device reliability. The variation in threshold voltage (V_th)is defined as (Vth,stressed–V_th,initial)/ V_th,initial×100%, where the Vth,initial and Vth,stressed are the measured Vth prior to and after the electrical stress. As can be seen, the fluorination process can greatly alleviate the On-current degradation under a hot carrier stress.Fig. 6.6 shows the variations of the threshold voltage over hot carrier stress time. The improvement of the surface roughness at the oxide/poly SiGe interface is found to be critical to reduce the hot carrier generation rate and eliminate damage.

6.4 Summary

We have fabricated poly-SiGe TFTs using CMP process. This work examines the study of the poly-SiGe TFTs using NH3 passivation and CMP process. Experimental results indicate that NH₃ passivation could effectively improve the turn on characteristics. Moreover, the TFTs fabricated on polished poly-SiGe film exhibits higher carrier mobility, better subthreshold swing, lower threshold voltage, and higher on/off current ratio. The results clearly show that by employing the plasma and CMP

steps, significant improvement in the poly-SiGe TFTs with low thermal budget and reduction of the hot carrier generation rate can be achieved. By NH3 treated poly SiGe TFTs which could reduce the trap state and resulting in a great improvement of device characteristics.

References:

[1] T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda and T. Nagano,

“ Advanced TFT SRAM cell technology using a phase-shift lithography,” IEEE Trans. Electron Devices, vol. 42, no. 7, pp. 1305-1313, 1995.

[2] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch and I. D. French, “The fabrication and characterization of EEPROM arrays on glass using a low temperature poly-Si TFT process,” IEEE Trans. Electron Devices, vol. 43, no. 11 pp. 1930-1936, 1996.

[3] T. Kaneko, Y. Hosokawa, M. Tadauchi, Y. Kita and H. Andoh, “400 dpi integrated contact type linear image sensors with poly-Si TFT’s analog readout circuits and dynamic shift registers,” IEEE Trans. Electron Devices, vol. 38, no. 5 pp.

1086-1096, 1991.

[4] Y. Hayashi, H. Hayashi, M. Negishi and T. Matsushita, “A thermal printer head with CMOS thin-film transistors and heating elements integrated on a chop,”

IEEE Solid-State Circuits Conference (ISSCC), pp. 266, 1988.

[5] N. Yamauchi, Y. Inada and M. Okamura, “An intergated photodetector-amplifier using a-Si p-i-n photodiodes and poly-Si thin-film transistors,” IEEE Photonic Tech. Lett., vol. 5, pp. 319, 1993.

[6] M. G. Clark, “Current status and future prospects of poly-Si,” IEE Proc. Circuits Devices Syst., vol. 141, no. 1, pp. 3, 1994.

[7] Y. Oana, “Current and future technology of low-temperature poly-Si TFT-LCDs,”

Journal of the SID, vol. 9, pp. 169-172, 2001.

[8] S. Morozumi, K. Oguchi, S. Yazawa, Y. Kodaira, H. Ohshima, and T. Mano, “B/W and color LC video display addressed by poly-Si TFTs,” in SID Tech. Dig.,

pp.156, 1983.

[9] R. E. Proano, R. S. Misage, D. Jones, and D. G. Ast, “Guest-host active matrix liquid-crystal display using high-voltage polysilicon thin film transistors,” IEEE Trans. Electron Devices, vol. 38, pp. 1781, 1991.

[10] T. -J. King, K. C. Saraswat, J. R. Pfiester, “PMOS transistors in LPCVD polycrystalline silicon-germanium films,” IEEE Electron Device lett., vol. 12, no. 11, pp. 584-586, Nov. 1991.

[11] T.-J. King and K. C. Saraswat, “Deposition and properties of low-pressure chemical-vapor deposited polycrystalline silicon-germanium films,” J.

Electrochem. Soc., vol. 141, pp. 2235, 1994

[12] V. Subramanian, K. C. Saraswat, “Optimization of silicon-germanium TFT's through the control of amorphous precursor characteristics,” IEEE Trans.

Electron Devices, vol. 45, no. 8, pp. 1690-1695, 1998.

[13] T.-J. King and K. C. Saraswat, “Polycrystalline silicon-germanium thin-film transistors,” IEEE Trans. Electron Devices, vol. 41, pp. 1581, Sept. 1994.

[14] S. Jurichich, T.-J. King, K. C. Saraswat, and J. Mehlhaff, “Low thermal budget polycrystalline silicon-germanium thin-film transistors fabricated by rapid thermal annealing,” Jpn. J. Appl. Phys., vol. 33, pp. L1139, 1994.

[15] A. J. Tang, J. A. Tsai, R. Reif, and T.-J. King, “A novel poly-silicon-capped poly-silicon-germanium thin-film transistor,” in IEDM Tech. Dig., pp. 513, 1995.

[16] V. Subramanian, K. Saraswat, H. Hovagimian, and J. Mehlhaff, “Optimization and modeling of silicon-germanium thin film transistors for AMLCD applications using a Plackett-Burman experimental design,” 1st Int. Workshop Statistical Metrology Honolulu, HI, June 9, 1996.

[17] V. Subramanian, K. Saraswat, H. Hovagimian, and J. Mehlhaff, “Response

crystallized Poly-TFT's,” Proc. 2nd Int. Workshop Statistical Metrology, pp. 94, 1997.

[18] C. Y. Chang, H. Y. Lin, T. F. Lei, J. Y. Cheng, L. P. Chen and B. T. Dai,

“Fabrication of thin film transistors by chemical mechanical polished polycrystalline silicon films,” IEEE Electron Device lett., vol. 17, no. 3, pp.

100-102, 1996.

[19] H. Y. Lin, C. Y. Chang, T. F. Lei, F. M. Liu, W. L. Yang, J. Y. Cheng, H. C.Tseng and L. P. Chen, “Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors,” IEEE Electron Device lett., vol. 17, no. 11, pp. 503-505, 1996.

[20] A . B. Y. Chan, C. T. Nguyen, P. K. Ko, M. Wong, A. Kumar, J. Sin and S. S.

Wong, “Optimizing polysilicon thin-film transistor performance with chemical-mechanical polishing and hydrogenation,” IEEE Electron Device lett., vol. 17, no. 11, pp. 518-520, 1996.

[21] A . B. Y. Chan, C. T. Nguyen, P. K. Ko, S. T. H. Chan and S. S. Wong, “Polished TFT's: Surface roughness reduction and its correlation to device performance improvement,” IEEE Trans. Electron Devices, vol. 44, no. 3, pp. 455-463, 1997.

[22] H. Y. Lin, C. Y. Chang, T. F. Lei, J. Y. Cheng, H .C. Tseng and LP Chen,

“Characterization of polycrystalline silicon thin film transistors fabricated by ultrahigh-vacuum chemical vapor deposition and chemical mechanical polishing,” Jpn. J. Appl. Phys., vol. 36, no. 7A, pp. 4278-4282, 1997.

[23] P. S. Shih, T. C. Chang, C. Y. Liang, T. Y. Huang and C. Y. Chang,

“Improvements of amorphous-silicon inverted-staggered thin-film transistors using high-temperature-deposited Al gate with chemical mechanical polishing,”

Electrochemical and Solid state letters, vol. 3, no. 5, pp. 235-238, 2000.

[24] G. Fortunato and P. Migliorato, “Determination of gap state density in

polycrystalline silicon by field-effect conductance,” Appl. Phys. Lett., vol. 49, pp.

1025-1027, Oct. 1986.

[25] F. V. Farmakis, J. Brini, G. Kamarinos and C. A. Dimitriadis, “Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors,” IEEE Electron Device Lett., vol. 22, pp. 74-76, Feb. 2001.

[26] M. Cao, T. J. King, and K. C. Saraswat, “Determination of the densities of the gap states in hydrogenated polycrystalline Si and Si_0.8Ge_0.2 films,” Appl. Phys.

Lett., vol. 61, pp. 672-674, Aug. 1992.

Fig. 6.1 Process flow for SiGe TFTs.

z Si_1-xGe_x (x=18 %) z Active region 100 nm z SPC 550 ℃

z CMP surface treatment process z Gate oxide 500Å

z Ion Imp. & annealing z Plasma treatment

N

⁺

N

⁺

SiO

₂

Table 6.1 Parameters of CMP process condition

(a)

(b)

(c)

Fig. 6.2 Three-dimensional AFM images of SiGe film surface (a)before CMP process, and after CMP polishing process for (b)10 seconds and(c)20 seconds, respectively.

10^-12 10^-10 10^-8 10^-6 10^-4

-15 -10 -5 0 5 10 15 20

plasma 60min plasma 30min plasma 120min

Dr a in c u rr e n t (A )

Gate voltage (V)

unpolished SiGe TFTs VD= 0.1 V

W/L= 10um/5um

Fig. 6.3 Transfer curves of unpolished TFTs with various NH₃ plasma treatment times in 30, 60, 120 minutes.

10^-12 10^-10 10^-8 10^-6 10^-4

-15 -10 -5 0 5 10 15 20

with SiGe CMP (plasma 120min) w/o SiGe CMP (plasma 120min)

D rai n c u rr e n t (A )

Gate voltage (V)

VD= 0.1, 5 V W/L= 10um/5um

Fig. 6.4 Transfer curves of SiGe TFTs with and without CMP polishing process.

Table 6.2 Characteristics of TFTs with and without CMP process

Vth (V)

S. S.

(V/dec.)

μeff (cm²/V.s)

Ion@

VG=15V (A)

Ioff ON/OFF Ratio

Nt (cm^-2)

SiGe TFTs

w/o CMP 10.3 2.1 6.3 7.16×10^-7 1.21×10^-11 5.92×10⁴ 6.42×10¹³

SiGe TFTs with CMP

5.75 1.25 12.5 3.06×10^-6 1.42×10^-12 2.15×10⁶ 1.42×10¹³

10¹⁷ 10¹⁸ 10¹⁹ 10²⁰ 10²¹ 10²² 10²³

0 0.1 0.2 0.3 0.4 0.5 0.6

NH3 plasma120min NH3 plasma 30min

Density of state (cm-3 eV-1 )

E-Ei (eV)

polished SiGe TFTs

Fig. 6.5 Density of states in band gap of the device using the polished SiGe film as channel with different NH3 plasma treatment times.

0 10 20 30 40 50 60

1 10 100 1000

with SiGe CMP w/o SiGe CMP

Threshold voltage variation (%)

Stress time (sec) NH3 plasma 120min

Stress condition VG=10V ; V

D=15V W/L= 10um/5um

Fig. 6.6 Threshold voltage degradation as a function of stress time under hot-carrier stress.

Chapter 7

Conclusions and Further Recommendations

7.1 Conclusions

In this thesis, the applications of these two kinks of epitaxy films were investigated. Planarization of rough surfaces of strain-relaxed Si_0.8Ge_0.2 buffer layer was done by CMP and post-CMP cleaning. It was found that soften polish pad can be eliminated SiGe surface roughness. The optimum conditions can achieve the strained-Si surface roughness of 0.6 nm. For the post-CMP cleaning process, various cleaning solutions have been applied to the SiGe buffer layer. By adding the surfactant (TMAH) and chelating agent (EDTA) into the diluted ammonium solution, removal efficiency of particles and metallic impurities is increased. The electrical performances of capacitors such as breakdown voltage, leakage current and Qbd are significantly improved for post-CMP cleaning. Furthermore, the optimal condition of SC1+TE sample has increased about 10 % in drive current. This post-CMP cleaning process is useful for planarization of strain-relaxed SiGe virtual substrates in MOSFET application.

We have developed a novel n-channel Si_1-yC_y interlayer heterostructure DTMOS structure. This layer could effectively reduce the diffusion of boron beneath the channel region. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. The excellent performances obtained in the Si1-yCy

interlayer DTMOS are due to both the same substrate doping concentration and lower channel surface impurity concentration. DTMOS have superior characteristics in

interlayer DTMOS are due to both the same substrate doping concentration and lower channel surface impurity concentration. DTMOS have superior characteristics in

在文檔中 矽鍺與矽碳薄膜應用於金氧半場效電晶體和複晶矽鍺與多通道薄膜電晶體之研究 (頁 88-0)