Chapter 1 Introduction
1.2 Thesis Organization
In Chapter 2 we discuss the design of broadband flip-chip interconnect for millimeter-wave Si carrier system-on-package. This discussion includes transmission line design, transition structure design, calibration method, and the measurement results.
In Chapter 3 two VCOs are designed by using the SoP technique to integrate a CMOS chip with a high-Q MEMS inductor. The design procedure of MEMS inductor and VCOs, simulation result, and measurement consideration are discussed.
In Chapter 4 low power and low voltage bulk-driven mixer is designed. This chapter includes the overview of the fundamental of nonlinearity analysis using variant Volterra series, comparison of simulation results and calculation results, individual nonlinear contribution, how to decide the optimal bias condition, input
matching mechanism, bias circuit, and measurement results.
Finally Chapter 5 is the conclusion and future work.
Chapter 2
Broadband Flip-Chip Interconnect for
Millimeter-Wave Silicon Carrier
System-on-Package
2.1 Introduction
In the development of advanced microwave and millimeter-wave systems, the interconnect design is an essential part of the system electrical performance. As far as circuit design is concerned, the interconnection shall provide good return loss and low insertion loss over the signal frequency range. Of the available multi-chip packaging techniques, the flip-chip technique appears better than the wire-bonding technique for microwave and millimeter-wave packaging due to less and more reproducible parasitic effects [7]. It has been shown in numerous articles that the electrical performance of the conventional wire bond leads to an increase in return loss and insertion loss as the frequency or interconnection distance is increased. The flip-chip interconnect is often employed for connection because of the advantages of low parasitic element since the short interconnection length, the low assembly cost, and
the high reproducibility, as compared to the conventional wire bond. When the flip-chip technology is used, there are two main issues that determine the characteristics of a flip-chip monolithic microwave integrated circuit (MMIC):
detuning of the circuit on chip due to its proximity to the motherboard and the reflection at the bump interconnect.
Most flip-chip technology adopts a soldering bump structure [8, 9]. Signal propagation inevitably encounters discontinuity. Operated at low frequencies, the flip-chip interconnect can be still considered as a simple transition of no significant impact on electrical performance in terms of return loss and insertion loss. This gives great freedom to circuit design and system integration. As to the millimeter-wave
(a) (b)
(c)
Fig. 2.1. The transition structures: (a) staggered bumps. (b) locally matching technique. (c) high impedance compensation.
modeling on parasitic and incorporated into circuit design.
Many transition structures have been proposed for the design at millimeter-wave frequency, like those as shown in Fig. 2.1[9-11]. The basic idea is that of compensation, i.e., reducing parasitic capacitance at the transition by adding an inductive counterpart. Three approaches are investigated here: staggered bumps, a locally matching technique, and an on-carrier solution employing a high-impedance line section. As to the staggered bumps in Fig. 2.1(a), compensation is achieved by staggering center conductor and ground bumps. The center conductor of the chip is elevated and the field concentrated in the air region, which leads to a decrease in capacitance. The clear disadvantage, however, is that the interconnection now consumes additional expensive chip area. Moreover, this approach is not compatible with common chip layouts, but requires a customized chip design. In brief, this approach is effective, but not generally recommendable.
Fig. 2.1(b) shows the locally matching technique. The ground conductor is retreat by ∆ to reduce the parasitic capacitance. The typical value of ∆ for good return loss is around 100um which increase the chip area, and thus raise the cost.
In the case of the high impedance compensation technique as indicated in Fig.
2.1(c), it is clear that the return loss is improved at low frequency band only. The high impedance line which contributes more parasitic inductance will degrade the high
frequency performance, that is, it is usually narrow band in principle.
These three compensation techniques require impedance matching to compensate the parasitic inductance and capacitance due to the soldering bump and the bumping pad, respectively. Nevertheless, matching optimization causes much time consumption and very often limited bandwidth. In this chapter, bump-less flip-chip interconnect by using Au-Au thermo-compression technique for the applications at millimeter-wave frequency band is discussed. This flip-chip interconnect has the advantages of easy design, no external matching network, small area, and broadband performance.
2.2 CPW to Microstrip Line Transition Structure Design
Transition of CPW to microstrip line is widely used in packages, on wafer measurement of microstrip based MMIC, and it also interconnects in hybrid circuits
Fig. 2.2. The test structure for characterization of the proposed bump-less flip-chip transition from CPW line on the Si carrier to microstrip line on the chip fabricated in a standard 0.18 um CMOS process.
including both microstrip and CPW. So CPW to microstrip line transition is adopted to test the bump-less flip-chip technology up to millimeter-wave frequency. The test structure as shown in Fig. 2.2 is designed connecting transmission lines, a microstrip line fabricated in a 0.18 µm CMOS chip and two CPW lines built on a silicon carrier.
Bump-less contacts apply Ni/Au deposited layers for chip bonding. In this design, EM signal will be transmitted from one CPW line on the silicon carrier to the other via two flip-chip interconnects and the microstrip line. Essentially this might be considered as the worst scenario of possible transitions. As signal loss through the microstrip line is very low, the symmetric structure design provides a full investigation on the electrical performance of the flip-chip interconnects.
2.2.1 Transmission Line Design
The design target of a transmission line is to decide the physical dimension corresponding to 50Ω characteristic impedance for the measurement purpose.
(i) Microstrip Line
M6
M1 SiO2
W
6.52um 2.34um PASS
= 4 ε
r
SiO2 M1
M6
(a) (b)
Fig. 2.3. The microstrip line structure in standard 0.18um CMOS technology, (a) cross-section view.
(b) top view.
Fig. 2.3 shows the cross-section view and top view of a microstrip line fabricated in standard 0.18um 1P6M CMOS technology. The microstrip line consists of the top metal layer (M6) as the signal line and the bottom metal layer (M1) as the ground plane. The only adjustable parameter is the center width of signal line which is set as 10.5um to obtain 50Ω characteristic impedance. The EM simulation result of Zo versus frequency is shown in Fig. 2.4. As indicated from the plot, Zo is dispersive at low frequency range. This phenomenon can be understood from the equation of characteristic impedance, (2-1). It is found that dispersion in low frequency is caused by the existent dielectric loss and the conductor loss. If the dielectric and conductor is perfect, i.e. no loss, the characteristic impedance will remain constant over the signal frequency. Although Zo deviates from 50Ω at low frequency, this does not mean that return loss degrades too. Keep in mind that the S parameter is defined for an infinite
0 20 40 60 80 100
48 50 52 54 56
Zo (Ohm)
freq (GHz)
Fig. 2.4. Frequency response of characteristic impedance of the microstrip line.
jwC G
jwL Z
oR
+
= +
(2-1)(ii) Coplanar Waveguide (CPW)
The cross-section view and top view of a CPW are shown in Fig. 2.5. The CPW consists of three conductors which center metal is signal line and the other two are ground layer. The CPW metal is made of electroplated Cu of 5um thickness. The design parameters for 50Ω line impedance are the width of center metal and the gap between signal line and ground line. The signal width is set as 10.5 um, the same as the signal width of microstrip line, to have continuous line impedance at the transition.
Hence the only changeable parameter is the dimension of the gap. “gap” is set as 7.2um to have 50Ω characteristic impedance. The simulation result of Zo is shown in Fig. 2.6 which indicates that Zo at high frequency is not close to 50Ω. It is since an error in simulation setup, but this does not affect the return loss too much. After removing the error in setup, the gap ought to be 8um to own 50Ω line impedance.
Silicon SiO2
W
2.1um gap 5um
SiO2Si3N4
Cu
400um
9 .
= 11 ε
r
(a) (b) Fig. 2.5. The CPW structure in carrier. (a) cross-section view (b) top view.
The frequency dependence at low frequency is different from the case in the microstrip line. This is since that the conductor loss is greater than the dielectric loss at low frequency in microstrip line; however, in the CPW, the loss from silicon substrate is larger than the conductor loss. Consequently, from (2-1), the Zo of the microstrip line and the CPW will approach infinity and zero, respectively, at zero frequency.
2.2.2 Transition Structure Design
After decision of the physical structure of the microstrip line and the CPW, the transition of CPW to microstrip line needs to be carefully designed to have continuous electromagnetic filed and smooth current flow. The grounds are designed in the shape as shown in Fig. 2.7. The connection of ground references also goes through the M6 metal as the chip is flipped. Vias are therefore required to connect the M6 ground pads to the M1 ground layer in the microstrip line on the CMOS chip. Those ground pads
0 20 40 60 80 100
36 38 40 42 44 46 48 50
Zo (Ohm)
freq (GHz)
Fig. 2.6. Frequency response of characteristic impedance of the CPW.
not only provide the connection but also strengthen mechanical joint. Although near-zero bump height provides smooth transition between two transmission signal lines, inevitable structural discontinuity still exists which would result in extra power loss due to the formation of different propagation modes. Furthermore, the physical discontinuity in the transition between the microstrip and the CPW lines would also raise leading reactive effects which will increase the return loss and insertion loss of signal transmission at high frequencies.
In order to mitigate the problem, the M6 ground pads are selected in a tapered trapezoidal shape and placed in some distance from the signal line to avoid extra capacitive coupling between the microstrip line and the reference ground. The shape of CPW grounds is also tapered near the interface to have better smooth current and continuous filed distributions in order to reduce signal power loss. The parasitic inductances due to current crowding in the ground pads help compensate the parasitic capacitance so that the overall line impedance can still keep on the 50Ω. It is
10.5um
20um 12.75um
32.75um
12um 7.2um
30um 10.5um
20um 12.75um
32.75um
12um 7.2um
30um
Fig. 2.7. Top view of the transition structure from CPW to the microstrip line. The electrical performance is evaluated by sweeping the parameters, Gap and Length, by an EM simulator.
understood that those two parameters of the distance between the signal line and the M6 ground pads of the microstrip line, Gap, and the distance from the tapered corner to the interface, Length, might be critical for good transition performance.
Simulations have been conducted by sweeping those two parameters for the value of Gap from 7.2um to 12um, and Length from 10um to 50um. It turns out that the return loss under all conditions varies only within a limited level over the frequency up to 80GHz. This indicates the great advantage of the proposed chip assembly technique that it provides easy transition design for very high-frequency applications. In this design, the Gap and Length geometric parameters are chosen as 12um and 40um, respectively, such that the return loss is the best result of the simulated cases. The tapered angle is therefore around 6.8 degrees. Fig. 2.8 is the plot of the simulation results by HFSS EM simulator, showing the transition structure including two transitions and one microstrip line can provide better than 23dB return loss and 0.9 dB
Fig. 2.8. HFSS simulation results of the test structure. The reference plane is de-embedded to the location as shown in Fig. 2.20, the same as that in TRL measurements.
insertion loss up to 100GHz.
2.2.3 Detuning Effect
Although the bum-less flip-chip interconnect can provide good electric performance, the detuning effect should be carefully concerned if there are reactive components in the CMOS chip. The detuning effect that any circuit on the chip might be affected by the additional lossy substrate or metal on the Si carrier in close vicinity after the chip is flipped and mounted. Since the bump height is near zero in this technique, there exists only thin passivation and air between the chip circuit and the substrate. The circuit electrical performance might be detuned significantly. As to the microstrip line in the flipped condition as shown in Fig. 2.9, the carrier substrate causes extra distributed capacitance and the line impedance is expected to be lower.
EM simulations help characterize the detuning effect and the results are shown in Fig.
Fig. 2.9. The microstrip line in flipped condition. The silicon carrier detunes the characteristic of the microstrip line.
2.10. The simulation results tell that although the return loss is somewhat degraded, it is still better than 23dB up to 100 GHz. Further study indicates that the line impedance deviates about 2-Ω.
2.2.4 Calibration Method
To measure the device under test (DUT), cables and high frequency probes are inevitably used to link the DUT to equipment. Besides, the Ground-Signal-Ground (GSG) pad is placed to connect the DUT so that it is possible to make an on-wafer measurement. These interconnections and pads contribute undesired loss and phase delay so they will impact the accuracy of DUT measurement. Consequently, calibration is required to remove these non-ideal effects. THRU-RELECT-LINE (TRL) calibration and multi-line de-embedding method are used to characterize the flip-chip interconnection. The major difference of these two methods is the system
Fig. 2.10. Analysis of detuning effect of the microstrip line under consideration indicates that the line impedance is deviated around 2-Ω.
characteristic impedance for measurement which is frequency dependent in TRL and fixed to 50Ω for multi-line de-embedding method.
(i) TRL Calibration Method [12, 13]
TRL calibration is most often performed when a high level of accuracy is demanded. It does not have calibration standards in the same connector type as the DUT and the standards are easy to manufacture and characterize. Block diagram shown in Fig. 2.11 represents general measurement setup. These non-ideal effects are lumped together in a two-port error box in Fig. 2.11. So a calibration procedure is needed to characterize the error box. The TRL calibration does not rely on known standard loads, but uses three simple connections to characterize the error box
⎥⎦
Fig. 2.11. Block diagram of a general measurement setup.
⎥⎦
Fig. 2.12. Block diagram and signal flow graph for the THRU connection.
completely. These standards are THRU, REFLECT, and LINE.
Fig. 2.12 shows the block diagram and signal flow graph for THRU connection.
Using basic decomposition rules we can get the S-parameters at the measurement plane in terms of S-parameter of the error box, as indicated in (2-2) and (2-3).
2 22 zero-length THRU is more accurate because it has zero loss and no characteristic impedance. The THRU standard is to set the desired reference plane for the measurement.
The reflect connection is shown in Fig. 2.13. The arrangement effectively isolate the two measurement ports, so that R12=R21=0. The signal graph can be easily reduced to show that
Fig. 2.13. Block diagram and signal flow graph for the REFLECT connection.
22
By symmetry we have R22=R11. The Reflect standard can be anything with a high reflection, such as open or short. However, the Reflect standards must have same Γ, reflection coefficient, on both test ports.
Fig. 2.14 shows the Line connection. The signal graph can show that
2 22
By symmetry and reciprocity we have L22=L11 and L21=L12, respectively. The characteristic impedance of line must be of the same impedance as the THRU standard and its length cannot be the same as the THRU standard. The disadvantage of TRL calibration is the limited bandwidth. The LINE standard must be an appropriate electrical length for the frequency range, that is, at each frequency, the phase difference between the THRU and the LINE should be greater than 20 degrees
⎥⎦
Fig. 2.14. Block diagram and signal flow graph for the LINE connection.
and less than 160 degrees. This means in practice that a single LINE standard is only usable over an 8:1 frequency range (Frequency Span/Start Frequency). Therefore, for broad frequency coverage, multiple lines are required.
With equations, (2-2 to 2-6), the S-parameter of the error boxes can be derived, as
well as unknown reflection coefficient, ΓL, and the propagation factor, e−γL. After the S-parameter of the error box is acquired, the S-parameter is transformed into the transmission matrix so we are able to get the transmission matrix of DUT by (2-7).
⎥⎦
⎢ ⎤
⎣
⎡
' '
' '
D C
B
A = −1
⎥⎦
⎢ ⎤
⎣
⎡ D C
B
A ⎥
⎦
⎢ ⎤
⎣
⎡
m m
m m
D C
B
A −1
⎥⎦
⎢ ⎤
⎣
⎡ D C
B
A (2-7)
(ii) Multi-Line De-embedding Method [14]
Any measurement is limited by an inherent flaw due to the test pads and interconnect are required to access the DUT. Multi-line de-embedding method uses two transmission line with different length and its symmetric property to remove the effect of test pad discontinuity.
Consider two transmission line test structure of length
l1 and
l2, where l1<
l2
(Fig. 2.15). If properly designed, the structures will be symmetric about y axis.
Symmetric property means that swapping port 1 and port 2 will not change the resulting S, Z, or Y matrices.
Swap function swaps port 1 and port 2 as indicated in (2-8).
Transmission line can be decomposed into a cascade of 3 two port network, two pads and intrinsic device. Consequently the transmission matrix of test structure
li,
t
Mli, can be represented by the following product:
2
MP represents the intrinsic line segment of structure,
Mli represents the left
-l1. Assuming that the left pad can be modeled as a lumped admittance YL, we have
Fig. 2.15. Multi-line for de-embedding.
This is referred as a lumped pad assumption. The hybrid structure can be expressed in terms of Y parameters, as a parallel combination of intrinsic transmission line and the parasitic lumped pad.
⎥⎦
Because of symmetry of test structure, we can swap the Y parameters of hybrid structure to remove the contribution from test pad so that we can get the intrinsic Y parameters of transmission line with length
l2 Assume the transmission matrix of lossy transmission line can be modeled as
⎥⎦
We can extract the characteristic impedance (Zo) and propagation constant (γ) of the transmission line using
C
ABCD parameters of transmission line can be gained by transforming the
1 2 l
Yl −
into its transmission matrix counterpart. From equation (2-12), the YL parameter of
pad is also easily derived, so is its transmission matrix.
After getting the ABCD matrices of transmission line and pads, ABCD of DUT is then acquired by the following equations where MDUTMeasured is obtained after SOLT calibration.
1 1
1
1 − − −
− × × × ×
= CPW PAD DUTMeasured PAD CPW
DUT M M M M M
M (2-17)
2.3 Measurement Results and Discussion
The chip micrograph is shown in Fig. 2.16, including the bonding microstrip line in flip-chip interconnect, a microstrip line for an on-wafer measurement, and other test structure.
2.3.1 Measurement Results of the Microstrip Line
The measurement results of the on-chip microstrip line are shown in Fig. 2.17. The return loss of the microstrip line is kept low over the frequency band. The insertion
Microstrip Line for on-wafer Measurement
Bonding Microstrip Line in Flip-Chip Interconnect
Fig. 2.16. Micrograph of the microstrip line fabricated by standard CMOS 0.18um technology
loss is around -0.4dB up to 50 GHz. The measurement results include the effects of
loss is around -0.4dB up to 50 GHz. The measurement results include the effects of