The Design of VCO with a High FOM

For the VCO with a high FOM, the inductor with a high inductance value to reduce the power consumption and increase the output power level is chosen so that the phase noise can be improved. As we goes back to the Fig. 3.3, Cf connecting the source nodes of the cross-coupled pair to the VDD is used to filter out the phase noise contribution from the current source. Using current mirror for the bias of the VCO core circuit is more immune to the process variation. The device size of current source is chosen the largest to have lower flicker noise contributing to the output phase noise.

Choice of the varactor and the inductor is to have a high loaded Q.

(a) (b)

Fig. 3.7. The inductance value and the Q of the MENS inductors (a) used in the VCO with a high FOM. (b) used in the VCO with a wide tuning range.

(i) LC Tank Design

Goal of the oscillation frequency is around 5GHz. Taking the inductance and the parasitic capacitance (from the switching pair, the output buffer, and the interconnect in the layout) into account, the residue capacitance is around 75fF. The varactor group fitting the requirement is group 1 and group 2 with finger number of 15~25 and 10~20, respectively. The characteristics of the varactor are summarized in Table 3.1. Finally the varactor of group 1 with finger 20 is chosen because the LC tank can have a high parallel resistance (Rp) at the resonance so that the power consumption can be lowed down. The Q of the LC tank and the Rp are shown in Fig. 3.8 where the parasitic capacitance from the active device is not included into the simulation.

Table 3.1. The summary of MOS varactor of group 1 and group 2.

Vtune:0~1V Freq=5GHz

finger Cmin(fF) Cmax(fF) Q

10 23.5 46.92 76.8~153.2

group1

20 47 94.69 58.8~118.7

10 47.06 93.92 54.6~109 group2

20 94.48 191.8 39.5~80.3

(ii) Design of Switching Pair

The PMOS switching pair provides the energy for the VCO to maintain lasting oscillation. However, inevitably, it will contribute parasitic capacitance to degrade the tuning range of the VCO. Small size of transistor in the switching pair can give a small parasitic capacitance, but it also provides small energy to the tank of the VCO.

So the trade-off between the tuning range and the FOM are taken into consideration.

We do a sweep on the finger number of the transistors. The finger number is changed from 2 to 30 as the width of the transistor is fixed to 1.5um. The simulation results are shown in Fig. 3.9 where the simulation is done as Vtune is 0.5V. Due to the high-Q

0.0 0.2 0.4 0.6 0.8 1.0

26 28 30 32 34 36 38 40

Q

V_tune (V)

(a) (b)

Fig. 3.8. The impedance and the Q of the LC tank under different tuning voltages. (a) the impedance (b) the Q.

MENS inductor, the transistor sizes can be small, but still provide enough negative transconductances to sustain the oscillation. Final width of the switching transistors are chosen to be 1.5um*25=37.5um. The finger number is set as 25 in order to have flat phase noise response as Vtune is changed from 0V to 1V.

(iii) The C_f Effects on the Phase Noise

In general, Cf is added to filter out the flicker noise from the current source so that the phase noise can be improved. However, the phase noise response is insensitive to the value of Cf as shown in Fig. 3.10 in the designed VCO with a high FOM. The reason is that the size of the switching transistors is small in the designed VCO. The

0 4 8 12 16 20 24 28 32

Phase Noise (1MHz Offset) Power Consumption(W)

TT

Phase Noise (1MHz Offset) Power Consumption (W)

(a) (b)

Phase Noise (1MHz Offset) Power Consumption (W)

(c)

Fig. 3.9. The FOM of the VCO with a high FOM versus the finger number of the switching transistors at different corner cases. (a) TT. (b) SS. (c) FF.

contribution of the current source to the output phase noise is function of the transistor size of the switching pair [Ref]. The low frequency noise from the current source causes the amplitude variation of the carrier. And then the amplitude variation modulates the harmonics of the carrier, resulting in the modulation of the phase shift.

Variability in the phase shift results in variability in wo, or phase noise. Small transistor size in the switching pair corresponds to low harmonic distortion so that the amplitude modulation (AM) to phase modulation (PM) conversion can be reduced. So the phase noise can be improved and insensitive to the filtering capacitance Cf [16].

However, reduction of the device width is limited by two constraints, sufficient loop gain and voltage headroom. We still add capacitance of 4pF to stabilize the current of tail current source.

(iv) Pre-Simulation Results

2 4 6 8 10

-122.8 -122.7 -122.6 -122.5

Phase Noise at 1MHz Offset (dBc/Hz)

C_f (pF) TT

SS FF

Fig. 3.10. The dependence of the output phase noise on Cf under different corner cases.

about 1mW under a supply voltage of 1V. The oscillation frequency as shown in Fig.

3.11(a) is in the range from 5GHz to 5.4GHz corresponds to 8% tuning range. The output power of the high FOM VCO is shown in Fig. 3.11(b) where the right axis denotes the output power before the buffer referred to 50Ω and the left axis is the output power after the buffer stage. The figure shows that the output power referred to 50Ω before the buffer is very large. This is due to the used high-Q MEMS inductor so that the parallel resistance at the resonance is large to produce the large output voltage

0.0 0.2 0.4 0.6 0.8 1.0

Pout (dBm) Before Buffer

V_tune (V)

Pout (dBm) After Buffer

(a) (b)

Fig. 3.11. (a) The oscillation frequency. (b) The output power of the high FOM VCO before and after the output buffer.

0.0 0.2 0.4 0.6 0.8 1.0

Phase Noise@1MHz Offset (dBc/Hz)

Vtune (V) Fig. 3.12. (a) the phase noise at 1MHz offset. (b) The FOM versus the tuning voltage.

swing even the power consumption is low.

Fig. 3.12 plots the phase noise at 1MHz offset and the FOM. The worse case for the phase noise at 1MHz offset is around -120dBc/Hz in the SS corner. The worse case in FOM is about -195dBc/Hz.

(v) Post-Simulation Results

The layout of VCO is imported to Ansoft Designer for the post-simulation to include the parasitic from the interconnections into the circuit simulation. Because the VCO chip will be flipped and then bonded to the carrier, the substrate in the carrier is involved in the simulation to include the detuning effect. The simulation result is exported as a touch stone file with 85 ports and we use a data item to include the touch stone file into the SpectreRF. However, the simulation cannot converge due to too many ports in SpectreRF. So we can only change the simulation tool to other one.

We change the simulation tool to Angilent ADS to post-simulate the VCO.

Nevertheless, there are some problems to the design kit regarding to the fast-fast (FF) corner in the MOS varactor so the post-simulation results just show the typical-typical (TT) and slow-slow (SS) corner cases.

The post-simulation results are shown in Fig. 3.13 and Fig. 3.14. The circuit performance is degraded due to the interconnections and the carrier substrate resulting in larger parasitic effects. The output power is degraded about 1dBm. The frequency

tuning range is shrunk to about 300MHz.The phase noise at the higher tuning voltage degrades the most , so does the FOM. Table 3.2 summarizes the post-simulation results of the high FOM VCO in the worse cases.

0.0 0.2 0.4 0.6 0.8 1.0

Phase Noise (dBc/Hz, 1MHz Offset)

Vtune (V)

Fig. 3.14. The phase noise and the FOM versus the tuning voltage, (a) the phase noise at 1MHz offset. (b) the FOM.

Pout Before Buffer (dBm, 50Ohm)

Vtune (V) Po_TT

Po_SS PoB_TT PoB_TT

Pout After Buffer (dBm)

(a) (b) Fig. 3.13. The oscillation frequency and the output power versus the tuning voltage. (a) The

oscillation frequency. (b) The output power.

Table 3.2. Summary of post-simulation result of high performance VCO.

VDD=1V,

Vtune=1V (Worse Case)

TT SS

Operation Current (mA) 1.2(core) 1.03(core) Phase noise

@ 1 MHz offset (dBc/Hz)

-119.27 -117.23

Tuning Range (GHz) 4.73 ~ 5.06 (5.4-5.03)/5.03=7%

4.69 ~ 5.06

(5.38-4.99)/4.99=7.9%

FOM -192.6 -191.2

(vi) SoP V.S. SoC

Fig. 3.15 shows the comparison between SoP and SoC solutions for the VCO design. The tuning range and the LC cross-coupled pair are the same in these two solutions. The only difference is the inductors. It indicates that the phase noise improvement is around 6dB by using SoP technique. The operational power consumption of the SoP case is just 1.08mW, lower than the SoC solution which the power consumption is 1.38mW. This simulation results are the pre-simulation results to compare the two solutions impartially.

Fig. 3.15. Phase noise. SoP versus SoC.