Chapter 4 Design of the Low Power and Low Voltage Bulk-Driven
4.3 Low Power Bulk-Driven Mixer Design
4.3.2 AC Response
4 1
! 3
1
! 2
1 ' 2 '' 3 ''' 4
+ +
+ +
= m gs m gs m gs m gs
D g v g v g v g v
I (4-18)
4.3.2 AC Response
Above analysis is based on the large signal analysis, it cannot take the frequency effect into consideration. We use the DCM to analyze the bulk-driven mixer which is a two-port system.
In order to simplify the analysis, the circuit in Fig. 4.8 is divided into its half circuit shown in Fig. 4.9 without losing the whole story. The nonlinearity of gm , gmb , and go are taken into account here, but the nonlinearity of the capacitances, such as Cgs, are not included into calculation because the analysis later in this section shows that they can be ignored. The matching network is not taken into consideration here.
The required nonlinear parameters for the calculation are extracted by DC simulation of a single transistor at each VGS and VDS bias as VBS is fixed to zero. The calculation results followed are based on the application of WBAN. The RF signal, the LO signal, and the IF signal are locating at 1.4 GHz, 1.39GHz, and 10 MHz,
respectively. The power of the RF signal and the LO signal are -40dBm and -6dBm, respectively.
The comparison of the calculation and the simulation results of the first-order response are show in Fig. 5-2-4~Fig.5-2-8 under LO power of -6dBm. The frequencies we calculate the response are shown in the figure. The simulation results are conducted by using harmonic balance (HB) in ADS. Two curves are followed well at different VGS except some voltage offset around 0.1V. This voltage off will be discussed later in this section.
Calculation results of the second-order nonlinear responses are shown in Fig. 4.11 and 4.12. As indicated from the Fig. 4.12, the highest voltage conversion gain is about
0.35 0.40 0.45 0.50 0.55 0.60 -60
-56 -52 -48 -44 -40 -36
Output (dBm)
VGS (V)
Cal_wRF1 Sim_wRF1
0.35 0.40 0.45 0.50 0.55 0.60 -30
-28 -26 -24 -22 -20 -18 -16
Output (dBm)
VGS (V) Cal_wLO Sim_wLO
Fig. 4.10. The comparison of the simulation and the calculation results of the first-order response at the frequencies of wRF1 and wLO.
Z
LRF LO
Fig. 4.9. The half circuit of the bulk-driven mixer for the nonlinearity analysis.
10dB at the VGS of 0.5V which is near the threshold voltage. So bias the bulk-driven mixer can feature in high voltage conversion gain.
The third-order and fourth-order nonlinear response are plotted in the Fig. 4.13 and 4.14. The IM3 response as shown in the Fig. 4.14 tell us that the highest IM3 is at the VGS of 0.5V which happens to the voltage corresponds to the highest voltage conversion. So a higher voltage conversion gain corresponds to a worse linearity. So biasing VGS of the bulk-driven mixer at the voltage near the threshold voltage is not a
0.35 0.40 0.45 0.50 0.55 0.60 -60
IF Output (dBm)
VGS (V) Cal_wRF1-wLO Sim_wRF1-wLO
0.35 0.40 0.45 0.50 0.55 0.60 -100 Sim_2wRF1
Fig. 4.12. The comparison of the simulation and the calculation results of the second-order nonlinear response at the frequencies of wRF1-wLO and 2wRF1.
0.35 0.40 0.45 0.50 0.55 0.60 -90 Cal_wRF1-wRF2 Sim_wRF1-wRF2
0.35 0.40 0.45 0.50 0.55 0.60 -92
Fig. 4.11. The comparison of the simulation and the calculation results of the second-order nonlinear response at the frequencies of wRF1-wRF2 and wRF1+wRF2.
good trade-off between the conversion gain and the linearity. However, if we carefully investigated the IF and the IM3 responses, we can find that the optimal VGS bias is at the voltage of about 0.43. The IM3 has its minimum at this voltage and the IF output
0.35 0.40 0.45 0.50 0.55 0.60 -120
-110 -100 -90 -80 -70 -60 -50 -40
IM3 (dBm)
VGS (V)
Cal_2wRF1-wRF2-wLO Sim_2wRF1-wRF2-wLO
Fig. 4.14. The comparison of the simulation and the calculation results of the fourth-order nonlinear response at the frequency of the IM3.
0.35 0.40 0.45 0.50 0.55 0.60 -136
-132 -128 -124 -120 -116 -112 -108
Output (dBm)
VGS (V)
Cal_3wRF1 Sim_3wRF1
0.35 0.40 0.45 0.50 0.55 0.60 -120
-116 -112 -108 -104 -100 -96 -92 -88
Output (dBm)
VGS (V) Cal_2wRF1-wRF2 Sim_2wRF1-wRF2
0.35 0.40 0.45 0.50 0.55 0.60 -124
-120 -116 -112 -108 -104 -100 -96
Output (dBm)
VGS (V)
Cal_2wRF1+wRF2 Sim_2wRF1+wRF2
Fig. 4.13. The comparison of the simulation and the calculation results of the third-order nonlinear response.
not degraded too much as compared to the voltage with the highest IF output.
Consequently, the conversion gain can be reserved and the linearity can be improved tremendously.
Actually as the LO voltage swing is small the voltage offset between the simulation and the calculation results is around zero. The comparison of simulation and calculation results with LO power of -30dBm is shown in Fig. 4.15 to Fig. 4.19. This is because that the quantity of the nonlinear mixing to dc is very small so that it does not change the original dc bias condition, that is, it is still in the small signal condition.
0.35 0.40 0.45 0.50 0.55 0.60
-80 -75 -70 -65 -60 -55 -50 -45
Output (dBm)
VGS (V) Cal_wRF1-wRF2 Sim_wRF1-wRF2
0.35 0.40 0.45 0.50 0.55 0.60
-100 -95 -90 -85 -80 -75
Output (dBm)
VGS (V)
Cal_wRF1+wRF2 Sim_wRF1+wRF2
Fig. 4.16. Comparison of the simulation and the calculation results of the second-order response.
0.35 0.40 0.45 0.50 0.55 0.60
-60 -56 -52 -48 -44 -40 -36
Output (dBm)
VGS (V)
Cal_wRF1 Sim_wRF1
0.35 0.40 0.45 0.50 0.55 0.60
-100 -95 -90 -85 -80 -75
Output (dBm)
VGS (V)
Cal_wRF1+wRF2 Sim_wRF1+wRF2
Fig. 4.15. Comparison of the simulation and the calculation results of the first-order response.
0.35 0.40 0.45 0.50 0.55 0.60
Fig. 4.19. Comparison of the simulation and the calculation results of the fourth-order response.
0.40 0.45 0.50 0.55 0.60
-136 Sim_3wRF1
0.35 0.40 0.45 0.50 0.55 0.60
-120
0.35 0.40 0.45 0.50 0.55 0.60 -128
Fig. 4.18. Comparison of the simulation and the calculation results of the third-order response.
0.35 0.40 0.45 0.50 0.55 0.60 -96
IF Output (dBm)
VGS (V) Cal_wRF1-wLO Sim_wRF1-wLO
0.35 0.40 0.45 0.50 0.55 0.60
-96 Sim_2wRF1
Fig. 4.17. Comparison of the simulation and the calculation results of the second-order response.
The reason for the voltage offset between the simulation and the calculation results as the LO power is -6dBm is due to the high frequency nonlinear current mixing to DC at drain node which alters the DC bias condition. This decrease in the drain to source voltage called ∆VDS can be easily obtained by taking the second-order nonlinearity into consideration only. The calculation result of ∆VDS is plotted in Fig.
4.20 which agrees well with the simulation result. If we take the ∆VDS into consideration, we can make the calculation results approach simulation results very well even the LO power is large.
Furthermore, this ∆VDS can predict the true drain current as the LO signal is going to drive the bulk-driven mixer. This operation current can be obtained by add ∆VDS
into the nodal equation as shown in the equation (4-19) where VDS,HB is simulation results at drain node at zero frequency using harmonic balance. The calculation and
0.35 0.40 0.45 0.50 0.55 0.60 -0.08
-0.06 -0.04 -0.02 0.00 0.02 0.04
VDS (V)
VGS (V)
Sim Cal
Second-Order Nonlinearity Only
∆
Fig. 4.20. Nonlinear mixing to the DC at the drain node. This DC offset at the VDS will increase the consumed drain current.
even the Volterra series is generally applied to a weakly nonlinear circuit, we can modify the changed bias condition due to nonlinear mixing and iterate the calculation
to get the final converged result.
− − + ∆
= . ( . )
DD DS HB = DD DS DC DS
D
L L
V V V V V
I R R
−∆
=DC DS
L
I V
R (4-19) 4.3.3 Individual Response
The most important benefit of the direct calculation method is that we can find out the individual contribution of the nonlinear parameters to the conversion gain and IM3, respectively. The individual contribution to the voltage conversion gain and the IM3 under RF power of -40dBm and LO power of -6dBm are shown in Fig. 4.22, and
Fig. 4.23, respectively. Fig. 4.22 indicates that the most important source to the conversion gain comes from the second-order nonlinear parameter
gmb
K gm
&
2 which
depends on gm and gmb simultaneously. This observation is different from the previous
0.35 0.40 0.45 0.50 0.55 0.60 0.0
0.2 0.4 0.6 0.8 1.0
Operation Current (mA)
VGS (V)
Sim Cal
Fig. 4.21. Comparison of calculation and simulation results in operation current.
papers which claim the voltage conversion gain is from gm only. There is a sweep spot behavior [8] around 0.45V meaning that the linearity of this circuit is very
sensitive to the VGS bias and so to the process variation. This sweet spot is due to the cancellation of the
gmb value with the increase of the RL, but the value of the minimal IM3 will also raise due to the larger nonlinear effect. Besides, the minimal IM3 also depends on the device
0.35 0.40 0.45 0.50 0.55 0.60 -20
-10 0 10 20
Voltage Conversion Gain (dB)
VGS (V)
Fig. 4.22. The individual contribution to the voltage conversion gain.
0.35 0.40 0.45 0.50 0.55 0.60 -120
0.35 0.40 0.45 0.50 0.55 0.60 -180-150
making a trade-off between the conversion gain and the linearity. In our design, the sweet spot behavior is mitigated by adding a feedback capacitance Cfb to have a high IIP3 over a wide VGS range. Furthermore, we adjust the optimal gate bias to 0.4V for the purpose of low power consumption.
4.3.4 Current Mirror Bias Circuit
As shown in Fig. 4.24(a) the bias voltages for the optimal IIP3 at different corner case in the bulk-driven mixer are changed a lot if using voltage bias. Current mirror bias circuit as show in Fig. 4.25, can make the circuit more robust to process variation.
The IIP3 versus the finger numbers of the transistors in the current mirror bias circuit is shown in Fig. 4.24(b). The voltage bias for the optimal IIP3 is almost the same now.
0.28 0.32 0.36 0.40 0.44 0.48 -32
-28 -24 -20 -16 -12 -8 -4 0 4 8
IIP3 (dBm)
VGS (V) FF
TT SS
10 20 30 40 50
-20 -16 -12 -8 -4 0 4 8
IIP3 (dBm)
Finger Number(Current Mirror) TT FF SS
(a) (b)
Fig. 4.24. IIP3 versus VGS under different corner cases. (a) use voltage to bias. (b) use current mirror to bias.
4.3.5 Matching Circuit
In general, input impedance of a common source is capacitive. Due to the feedback capacitance Cgd, RL causes the input impedance to have a large real part.
Small signal equivalent is still valid as the MOS operates in the subthreshold region.
The input impedance can be computed as:
2 2 2 2 2
2 2 2 2 2 2
(1 ) [ ( )]
[ ( ) ]
gs gd m gd gs gs gd m gd
in
gd gs gs gd m gd
v w RC g R jw w R C C C C g RC
Z i w w R C C C C g RC
+ − − + +
= =
+ + +
2
2 2 2 2 2
(1 )
Re[ ]
( )
gd m
in
gd gs gs gd m gd
RC g R Z
w R C C C C g RC
= +
+ + + (4-20) As seen from the equation (4-20), the real part is zero if the Cgd is zero, that is, no feedback path. So we use an L-match technique to make the input impedance match in 50Ω in the 1.4GHz. Actually the bulk-driven mixer has the potential to merge the LNA and the mixer into a single stage so that the power consumption can be low.
Fig. 4.25. The diagram of the current mirror bias circuit.
4.4 Measurement Results
4.4.1 On-Wafer Measurement Setup
Fig. 4.26 shows the measurement setup where RF and LO signals are given by probes, and DC bias pads are bonding to the FR4 board through bond-wires. The PCB layout is shown in Fig. 4.27. LO signal goes through a balun to transform to differential signals. IF outputs are connected to the output buffer with a unit gain. The micrograph of the chip is shown in Fig. 4.28.
Fig. 4.27. PCB Layout.
Fig. 4.26. Measurement setup for the on wafer measurement.
4.4.2 Measurement Results
The frequencies of two RF signals and the LO signal in the measurement are 1.391 GHz, 1.392GHz, and 1.39 GHz, respectively. The power of the two RF signals is about -27dBm and the LO power is about -0.55dBm in the measurement. The circuit is still in the linear region as the RF power is -27dBm. So we can make the measurements on IIP3 accurately. The supply voltage is 1V and the standby power consumption is 0.25mW. The operation power is about 0.69mW. Fig. 4.29 shows the S11 measurement results under different LO power. As seen from the figure, the S11 is closed to simulation result. The Minimum of S11 moves to lower frequency as the LO power is increased. In our measurement that we set the LO power to -0.55dBm, nearly the same as simulation. The S11 is -18.1dB at 1.4GHz. The bandwidth is about 1GHz.
RF
LO+
LO-GND
GND
GND
GND
GND IF+
IF-
Fig. 4.28. Micrograph of the bulk-driven mixer.
0.4 0.8 1.2 1.6 2.0 2.4 2.8
0.30 0.35 0.40 0.45 0.50
-16
Voltage Conversion Gain (dB)
VGS (V) Measured SS TT
0.30 0.35 0.40 0.45 0.50
-44
0.30 0.35 0.40 0.45 0.50 -18
Fig. 4.30. The measurements of the conversion gain, the IM3 gain, and the IIP3 versus VGS. (a) voltage conversion gain. (b) the IM3 gain. (c) the IIP3.
Fig. 4.30 shows the measurement results of the voltage conversion gain, IM3 gain, and the IIP3 versus VGS. The VGS using the current mirror biasing is 0.39V. The measured data is between the SS and TT corner cases. The measured response is closed to the simulation.
Fig. 4.31 shows the gain and the IIP3 versus supply voltage VDD. In our design, the supply is set to 1V. As seen from Fig. 4.31, the bulk-driven mixer can operate at the supply voltage of 0.6V. The operation current at 0.6V is only 0.3mA corresponding to 0.18mW operation power. The voltage conversion gain is 13.2dB and the IIP3 is -2dBm.
The voltage conversion gain and the linearity versus the LO power is plotted in Fig.
4.32. Larger LO power has larger conversion gain and linearity, but the operation power is increased too. We are also interested in the LO power of -6dBm which is
0.6 0.8 1.0 1.2
12 14 16 18 20
Voltage Conversion Gain (dB)
VDD (V) Measured SS TT
0.6 0.8 1.0 1.2
-6 -5 -4 -3 -2 -1 0
IIP3 (dBm)
VDD (V)
Measured SS TT
(a) (b)
Fig. 4.31. The measurements of the conversion gain, and the IIP3 versus VGS. (a) voltage conversion gain. (b)IIP3.
closed to the power level in the nonlinearity calculation. With LO power of -6dBm, the voltage conversion gain and the linearity are 12dB and 0.1dBm, respectively.
Small LO power means the power consumption of the VCO can be low. So as integration of the mixer and the VCO, the whole circuit can really feature in the low power consumption.
Fig. 4.33 shows the voltage conversion gain versus the IF bandwidth. The RF
0 5 10 15 20 25 30
12 14 16 18
Voltage Conversion Gain (dB)
fIF (MHz)
Measured SS TT
Fig. 4.33. The measurements of the conversion gain versus the IF frequency.
-8 -6 -4 -2 0 2
8 10 12 14 16 18 20
Voltage Conversion Gain (dB)
PLO (dBm)
Measured SS TT
-8 -6 -4 -2 0 2
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
IIP3 (dBm)
PLO (dBm)
Measured SS TT
(a) (b)
Fig. 4.32. The measurements of the conversion gain, and the IIP3 versus the LO power. (a) voltage conversion gain. (b)IIP3.
frequency is fixed to 1.4GHz and the frequency of the LO signal is swept from 1.37 GHz to 1.399GHz. The measured IF bandwidth is narrower than that of the simulation.
This may come from the unknown factors in measurement setup associated with the PCB board and the external output buffer. Although the bandwidth is narrower, it still satisfies the required bandwidth of of 6 MHz in the WBAN application.
Fig. 4.34 shows the voltage conversion gain versus the RF bandwidth. The frequencies of the RF signal and LO signal change simultaneously to fix the IF frequency to 1MHz. The bandwidth is around 1.8 GHz. The voltage conversion gain is reduced as the high frequency because we have a low pass filter in the IF port.
Fig. 4.35 indicates the measurement results of the double sideband (DSB) noise figure(NF) of the bulk-driven mixer. The DSB NF is 19.65dB at the IF frequency of 10MHz. The measured DSB NF is around 3dB higher than the simulation results. This
0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 12
14 16 18 20
Voltage Conversion Gain (dB)
fRF (GHz)
Measured SS TT
Fig. 4.34. The measurements of the conversion gain versus the IF frequency.
may due to the external parasitic effects coming from the measurement setup. In the application of WBAN, the noise figure is not important because the transmission distance is usually short.
Fig. 4.36 shows the third-order intercept point. The IIP3 is around -0.5dBm using the current mirror for the bias of the circuit.
Table 4.6 summarizes the circuit performance and makes a comparison with the prior arts.
0 2 4 6 8 10
14 16 18 20 22 24 26 28 30
NF_DSB (dB)
fIF (MHz)
Measured SS TT
Fig. 4.35. The measurements of the DSB NF versus the IF frequency.
-32 -28 -24 -20 -16 -12 -8 -4 0 -90
-80 -70 -60 -50 -40 -30 -20 -10 0
Output (dBm)
PRF (dBm) IF IM3
~ -0.5dBm
Fig. 4.36. The measurements of the IF and the IM3 versus the RF power.
Table 4.6 Comparison of the proposed bulk-driven mixer with the prior arts.
RF=1.4GHz LO=
1.399GHz
[3]
Measured [3]
Measured
[4]
Sim
[5]
Measured
[6]
Measured
This Work Measured
RF (GHz) 2.1 6.9 0.9 12 1.9 1.4 1.4 1.4
Vdd (V) 1 1 1 1.2 0.8 1 0.6 1
Gain (dB) 6 6 2.1 3.2 1 16 13.2 12.11
LO (dBm) 2 7 N/A 9 0 -0.55 -0.55 -5.55
S11 (dB) N/A N/A N/A N/A N/A -18.06 N/A N/A
NF (dB) 9.6 (DSB) 18 (DSB) 19.8 (DSB) 17.4 (DSB) 11 (SSB) 19.65dB (DSB)
14.5dB*
(DSB)
15dB*
(DSB)
IIP3 (dBm) 10 -2 16.65 -2.1 -9 -0.5 -2.61 -0.54
Power (mW)
0.14 0.18 1.6 1.8 0.4 0.25
0.69**
0.11 0.18**
0.25 0.46**
Mixer Type Switching mixer
Switching mixer
Switching mixer
Switching mixer
Switching mixer
Nonlinear Mixer
Nonlinear Mixer
Nonlinear Mixer
Technology 0.5um 0.5um 0.8um 90nm 0.18um 0.18um 0.18um 0.18um
*simulation. **Operation Power
4.5 Re-Tapeout of the Bulk-Driven Mixer
The measured IF bandwidth is narrower than that of the simulation. We find that the interconnections from the IF output to the measurement FR4 board affects the circuit performance a lot because the bulk-driven mixer has only one transistor, that is, the isolation between the IF output and the RF input is low. We believe that the issue of the narrow IF bandwidth comes from the unknown factors originated from the
re-designed the bulk-driven mixer with an output buffer in the architecture of the source follower as shown in Fig. 4.37. The output buffer can help block out the influence of the undesired effect in the board. VGS1_Buffer, VGS2_Buffer, and VDD_Buffer are 0.6V, 1.6V, and 1.8V, respectively. The additional bias voltage of VGS2_Buffer is to keep a good linearity of the output buffer as the VGS of the core bulk-driven mixer is changed.
The simulation results are shown in Fig. 4.38 to Fig. 4.41. The circuit performance is summarized in Table 4.7.
0.8 1.0 1.2 1.4 1.6 1.8 2.0 -28
-24 -20 -16 -12 -8 -4 0
S11 (dB)
fRF (GHz)
TT FF SS
Fig. 4.38. The simulation results.
Fig. 4.37. The output buffer.
0 20 40 60 80 100
Voltage Conversion Gain (dB)
fIF (MHz)
TT FF SS
1.30 1.35 1.40 1.45 1.50
12.5
Voltage Conversion Gain (dB)
fRF (GHz)
Voltage Conversion Gain (dB)
VDD (V)
Voltage Conversion Gain (dB)
Plo (dBm)
TT FF SS
Fig. 4.39. The simulation results
Table 4.7 Summary of the circuit performance of the re-tapeout bulk-driven mixer
RF：1.4GHz，LO：1.39GHz，
LO：-0.5dBm VDD=1V，IF=10MHz
SS FF SF FS TT
Voltage Conversion Gain (dB)
15.5 13.3 14.8 14.2 14.7
IIP3 (dBm) 0.1 -0.4 0.19 -0.8 0.11
P-1dB (dBm) -12.8 -13 -12.6 -13.2 -12.7
NF,DSB(dB) 16.4 15.4 16.7 15 16
S11 (dB)@1.4GHz -19.7 -26.7 -23 -26 -24
LO to IF Isolation (dB) -24.5 -22.6 -24 -24.5 -23.7
LO to RF Isolation (dB) -70 -70 -70.8 -70.8 -70
RF to LO Isolation (dB) -25 -25.6 -25.3 -25.4 -25
RF to IF Isolation (dB) -36 -35.5 -36 -35.7 -35
Standby Power (mW) 0.24 0.33 0.28 0.28 0.27
Operation Power (mW) 0.59 0.6 0.66 0.52 0.58
Chapter 5 Summary and Future Work
5.1 Summary
In Chpater2, we designed a flip-chip interconnect for millimeter-wave application.
The measurement results of the flip-chip structure shows return loss of 15dB and insertion loss of 1.7dB up to 50 GHz.
In Chapter 3 we design two VCOs using SoP technique. One of the two VCOs features in a high FOM. The other is designed to have a wide tuning range. The simulation results shows that the high FOM VCO has worse FOM of 191.2 dB, tuning range of 7% under power consumption of 1.03mW. For the wide tuning range VCO, its worse FOM and tuning range is 188dB and 17.6%, respectively. The power consumption is 1.08mW.
In Chapter 4 use variant Volterra series to analyze the nonlinearity of the bulk-driven mixer. The nonlinearity analysis results help us how to trade off between the gain and the linearity. The measurement results of the bulk-driven mixer hve the voltage conversion gain of 16dB, third-order intercept point of 3.5dBm, input return loss of 18.1dB, and the power consumption is only 0.24mW (0.69mW) in standby mode (operation mode). The bulk-driven mixer can further operate in a supply voltage of 0,6V. The voltage conversion gain is 13.2dB and the IIP3 is -2dBb under a power
consumption (operation) of 0.18mW.
5.2 Future Work
The flip-chip technology makes it possible to realize the system building on the package. We can integrate more RF modules to complete a single IC with high integration.
Bulk-driven mixer uses only one transistor to down-convert the RF signal. As shown in Fig. 5.1, it is possible to down-convert the RF signal twice in one stage by stacking the bulk-driven mixer with an additional switching pair to increase the flexibility in the receiver design.
LO1+
LO1-RF R
LV
DDR
LIF+
IF-M
2M
1RF
LO2+
LO2-Fig. 5.1. Mixer topology for twice downconversion.
References
[1] Bert Gyselinckx, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov, “Human++: Autonomous Wireless Sensors for Body Area Networks,” IEEE Custom Integrated Circuits Conference, pp. 13-19, Sept.
2005.
[2] S. Chakraborty, K. Lim, A Sutono, E. Chen, S. Yoon, A. Obatoyinbo, S. -W.
[2] S. Chakraborty, K. Lim, A Sutono, E. Chen, S. Yoon, A. Obatoyinbo, S. -W.