Thesis Organization

This thesis is organized into five chapters. In Chapter 1, this thesis and the humidity sensor architecture are briefly introduced. In Chapter 2, the basic concepts of quantizer and quantization noise, and fundamentals of the first-order and second-order sigma-delta modulator are introduced. The non-linear effects of the sigma-delta modulator and design of analog circuits are also introduced. Finally, the performance of sigma-delta modulator is presented in detail.

In Chapter 3, the analysis of the proposed sigma-delta modulator used for capacitive sensors is done by MATLAB simulation. First, the analysis of the first-order sigma-delta modulator is presented. Then, the analysis of the second-order sigma-delta modulator is discussed and the parameters of the second-order system are determined by MATLAB.

In Chapter 4, an ultra low power sigma-delta modulator using amplifier operating in weak inversion is introduced. All transistors of the amplifier operating in weak inversion can greatly reduce the power consumption. However, it leads to a large chip area. Some other techniques used in low-voltage low-power sigma-delta modulator are presented.

In Chapter 5, the conclusions of this work are summarized. All the simulation result are also summarized in this chapter..

Polyimide Finger

Chapter 2

Fundamentals of

Sigma-Delta Modulator

2.1 Introduction

Some of the fundamental issues in the design of sigma-delta modulators will be reviewed in this chapter. The first-order sigma-delta modulator is presented in Section 2.2. It includes the basic analysis of the quantization noise, the z-domain linear model, and nonlinear effects due to finite gain of the amplifier. In Section 2.3, we introduce the second-order sigma-delta modulator. The z-domain linear model, nonlinear effects, and alternative structures are introduced. In Section 2.4, some practical design considerations of sigma-delta modulator are taken into account.

2.2 First-order sigma-delta modulator

2.2.1 Quantization noise

A 1-bit quantizer is the heart of all single quantizer sigma-delta modulators. The analysis of the behavior of a sigma-delta modulator must include the behavior of the

quantizer. Since the quantizer is a nonlinear element, the analysis is complicated even in a simple system. Before the analysis, we modeling the quantizer as the linear model shown in Figure 2-1. The signal e(n) is the adding quantization error, which is the difference between input and output signals. The linear model becomes approximate as long as the quantization error, e(n), is an independent white-noise signal[1].

Figure 2-1 Quantizer and its linear model

At the beginning, the quantization error, e(n), is assumed to be an independent random number with uniform distribution. The signal e(n) uniformly distribute between ± ∆ 2, where ∆ is the difference between two adjacent quantization levels.

Figure 2-2 is the power spectral density of quantization noise, e(n).

Figure 2-2 Power spectral density of quantization noise

Assume the total noise power is ∆² 12 and f_s is the sampling frequency. With a two-sided definition of power, the area under ^S_e

( )

^{f within}

2 fs

± is equal to the total noise power, or mathematically,

( )

²

2.2.2 Linear model of first-order sigma-delta modulator

The architecture of a first-order sigma-delta modulator is shown in Figure 2-3.

The first-order sigma-delta modulator contains a integrator, a 1-bit quantizer, and a 1-bit DAC used for the feedback. In Figure 2-3(b), a z-domain linear model is presented[4]. According to the linear model, the signal transfer function(STF) and noise transfer function(NTF) can be derived as follows.

( )

¹

( ) ( )

¹

( )

^.

Equation (2.3) can be written in the general form

( )

^{( )}

( )

^{( )}

( )

^.

V z =STF z U z +NTF z E z (2.7) Comparing to the equation (2.3), the first-order sigma-delta modulator has the signal transfer function is ^{STF z}

( )

⁼¹ and the noise transfer function is

( )

^{1 1}

NTF z = −z⁻ .

(a) (b)

Figure 2-3 (a) Topology of 1^st-order sigma-delta modulator, (b) z-domain linear model

Let z e= ^{j Tω} =e^{j2π f fs}, the noise transfer function can be written as

Take the magnitude of the noise transfer function, we have

∫ Q

( )

^2sin

Assume the signal bandwidth of the system is f_B, we define the oversampling ratio, OSR, as

Based on the above assumption, the quantization noise power over the frequency band from 0 to f_B is given by

Recalling that the quantization noise power is assumed to be ∆² 12. When f_B<< f , we can approximate _s ^sin

( ( )

π f fs

)

to be

( )

^{π f f}_s ^.

The equation (2.7) can be calculated as

2 2 1 3

And the maximum signal power ²

s M2

P = , where M is the peak amplitude of the full-scale sin wave. Hence, the in-band signal-to-quantization-noise ratio(SQNR) is approximately

( )

³

From equation (2.9), it shows that the SQNR increases by 9 dB for each doubling of the OSR[4].

2.2.3 Stability and nonlinear effects

Since the first-order sigma-delta modulator contains only one pole, the system guarantees an unconditionally stability. However, this prediction doesn’t consider the actual signal processing performance in the circuit. In time-domain analysis, the designer should take into account the nonlinearities. Consider the stability when the loop is under DC excitation. If the input is larger than the feedback, the loop will become unstable and output is not bounded.

The analysis in Section 2.2.2 is under an ideal condition. Here, we discuss an non-ideal case with finite gain. Figure 2-4 shows a simple parasitic insensitive integrator. Assume the amplifier in Figure 2-4 has an finite gain A . Then the difference equation which applies to the charge conservation on integrator capacitor

C2 is

The pole of the integrator is slightly less than 1. The integrator is therefore lossy or leaky. If A OSR> , the additional noise is less than 0.2dB. Hence, the nonlinear effect is not serious. A more important thing is to make sure that the amplifier gain is linear.

Figure 2-4 Switch-capacitor integrator

2.3 Second-order sigma-delta modulator

2.3.1 Linear model of second-order sigma-delta modulator

In the previous section, we introduce the fundamentals of the first-order sigma-delta modulator. However, the first-order sigma-delta modulator in terms of resolution and idle-tone generation is not suitable for most applications. In this section, we focus on the second-order sigma-delta modulator. Figure 2-5 shows the z- domain linear model of the second-order sigma-delta modulator.

C1 C2

Figure 2-5 Linear model of 2nd-order sigma-delta modulator

From equation (2.12), it follows that

( ) ( ) (

^{1 1}

)

²

^{( )}

V z =U z + −z⁻ E z (2.17)

Hence, the signal transfer function is ^{STF z}

( )

⁼¹, and the noise transfer function is

( ) (

^{1 1}

)

²

NTF z = −z⁻ . Comparing the noise transfer function with first-order

modulator, we know that there is an increased attenuation of quantization noise at low frequencies. The magnitude of the noise transfer function is given by

( )

^{2 2sin 2} Calculate the total quantization noise power over the band of interest, we obtain

2 4 1 5

The maximum signal power ²

s M2

P = , where M is the peak amplitude of the full-scale sin wave. And the maximum in band signal-to-quantization-noise ratio(SQNR) is given by

( )

⁵

We can see from equation (2.16) that doubling the OSR improves the SQNR for a second-order sigma-delta modulator by 15 dB.

2.3.2 Nonlinear effects

The dynamic behavior of the second-order sigma-delta modulator with a 1-bit quantizer is more complex than those of the first-order sigma-delta modulator. From the analysis in [5], we realize that the quantizer’s gain is in fact signal-dependent.

Figure 2-6 shows an example of the quantizer transfer curve(QTC) to illustrate the nonlinear effect of the second-order sigma-delta modulator. The quantizer is based on the cubic approximation, v k y k y= ₁ + ₃ ³. We can use this model to estimate the harmonic distortion induced by the signal-dependent quantizer’s gain.

Figure 2-6 An empirical-determined quantizer transfer curve

For a small low-frequency sin-wave which has amplitude A , the local average of the output follows the input, and thus the local average of the quantizer input is also a low-frequency sin-wave which has an amplitude of A k₁. The amplitude of the third harmonic induced by the QTC is ^{k A k}₃

(

₁

)

^{3 4}. The third harmonic distortion is When the input is large, the distortion is severe.

2.3.3 Alternative second-order sigma-delta modulator

1

Several alternative structures are available to perform a second-order sigma-delta modulator. In design these structures, the designer should take care to avoid delay-free loops and do a robust design against the unavoidable non-ideal effects such as finite amplifier gain, mismatch of the passive component, etc. Here, we introduce the Boser-Wooley modulator[25], the Silva-Steensgaard structure, and the Error-Feedback structure.

The first one which we will introduce is the Boser-Wooley modulator shown in Figure 2-7. The structure contains two delaying integrators. The using of the delaying integrator allows the amplifier to settle independently of each other. According to the linear analysis, the STF is

Figure 2-7 The Boser-Wooley modulator

Second, we will introduce the Silva-Steensgaard structure shown in Figure 2-8.

The features of this circuit are the direct feedforward path from the input to the quantizer and the single feedback path. According to the linear analysis, the STF and NTF is proofed to be the same as before. The structure has a significant advantage that the loop filter does not need to process the signal and reduces the requirement of

a1 a2

linearity.

Figure 2-8 Silva-Steensgaard structure

The third one is the Error-feedback structure. The structure shown on Figure 2-9 looks simple and attractive. However, it is impractical for analog sigma-delta modulator. The quantization error is obtained in analog form by subtracting the quantizer’s input from the quantizer’s output. And then the quantization error is fed into the filterH_f . The output of the z-domain representation is

( ) ( ) ( )

_f

( )

V z =E z +U z +H E z (2.24) From equation (2.20), ^{Hf = −}

(

^{1 z−1}

)

^{2 − =1 z−2 −2z−1} is needed such that

( ) (

^{1 1}

)

²

NTF z = −z⁻ is obtained.

Figure 2-9 Error-Feedback structure

Z^-1 Z^-1

1

1

2

Y V Q

Z^-1 Z^-1

Q -2

Y

E

( )

z =−2z⁻¹ +z⁻² H_f

U

U V

2.4 Considerations of analog circuit design for sigma-delta modulators

2.4.1 Introduction

Both the fundamentals of the first-order and second-order sigma-delta modulators have been introduced in the preceding two sections. Now, we are concerned on the practical design considerations. In the Section 2.4.2, we discuss the architectural design concepts. In the Section 2.4.3, the non-idealities at the circuit level are taken into account. In the last section, the analog components that affect the performance of the system are presented.

2.4.2 Architectural design considerations

The architectures of the sigma-delta modulators can be divided into two categories: single-stage modulators and cascaded modulators. Single-stage modulators such as those presented in Sections 2.2 and 2.3 are more tolerant of circuit non-idealities than the cascaded ones. In the thesis, we adopt the single-stage architecture in our design for the following reasons.

1. Single-stage modulators are more tolerant on gain errors that result from capacitor mismatch in switched-capacitor integrators.

2. Single-stage modulators are also tolerant of the integrator leakage that results from the finite DC gain of amplifier.

3. The single-stage modulators are simple and suitable for the design of low power modulators.

Another issue is how to choose an appropriate OSR for the modulator. The use of a higher OSR generally increases the unit-gain bandwidth and slew rate of the amplifier. A higher OSR also have larger power consumption. However, a larger OSR can reduce the chip area of the modulator by the reduction of the sampling and load capacitors. The choice of the OSR is a trade off between power consumption and chip area.

2.4.3 Circuit level non-idealities

Both the single-stage and cascaded modulators are sensitive to circuit

non-idealities at their inputs. As a result, operational amplifiers with a large DC gain and capacitors with a low voltage-coefficient is required to implement the first integrator. The integrator transfer function will differ from the ideal one due to the nonzero switch resistance, finite bandwidth, and finite gain. These non-ideal transfer functions are given separately. For finite gain A,

( ) ( ) ( ( ) )

For finite amplifier bandwidth, B(in hertz),

( ) (

1 2

)

¹

( )

¹ 2

(

1 2

)

For nonzero switch resistance, R , _on

( ) (

1 2

)

^{1 / 4 1}

From equations (2.21), (2.22), and (2.23), we know that finite amplifier gain and incomplete linear settling cause gain error. Fortunately, the gain error has little effect on the performance of a single-loop modulator. The other non-idealities are the voltage-dependent capacitors, signal-dependent switch charge injection, and nonlinear amplifier DC transfer function.

In order to eliminate the distortion of the sigma-delta modulator, the designer should take into account all the non-idealities discussed above. The best way to deal with the non-idealities is to have a good quantitative understanding of these causes and effects.

2.4.4 Modulator component design considerations

A feedback DAC and a comparator are the two important components in the closed-loop modulator. In this section, we will introduce these two component and their design considerations.

The DAC controls the mapping between the analog and digital domains. Hence, the accuracy of the feedback DAC influences the performance of the sigma-delta modulator. There are three non-idealities caused by 1-bit DACs used in sigma-delta modulators:

1. Reference non-idealities: the output of the DAC is the product of the digital input

and the reference voltage. Time-domain multiplication results in a convolution in the frequency-domain. Therefore, signals on the reference with spectral components near the sticks of the output bit stream will cause these sticks to be modulated and convolved. The sticks will be transferred down to the frequencies near DC, known as idle tones.

2. Charge-taking non-idealities: the instant when the amount of charge is delivered to the integrator by the DAC must be identical for the clock cycle. If it is not, it will cause unwanted signals on the reference.

3. Charge-delivery non-idealities: if the charge stored on the feedback capacitor in the DAC is not fully delivered to the integrator each clock cycle, a gain error can occur.

Next, we will consider the design of the comparator. The non-idealities of the comparator can be reduced by the noise-shaping function of the loop. But there are still some design issues for the designer to take into account. The most important one is the metastability of the comparator. Another issue should be concerned is the hysteresis of the comparator. Hysteresis in the comparator makes the present output depending on the previous output. On the other hand, the comparator has memory on it’s output. This memory can create unwanted system poles that may causes errors in the signal and noise transfer functions.

2.5 Summary

The sampling rate of Nyquist A/D converters is only twice of the signal band.

However, it is difficult to achieve high resolution A/D conversion due to requirements of accurate anti-aliasing filters. The oversampling technique is a good approach to achieve high resolution A/D converters. The sigma-delta modulator is the most used architecture in the oversampling A/D converters. For the area of sensors, a low power high resolution A/D converter is necessary. The sigma-delta modulators which combined with the front-end circuits for sensors are preferred because it can reduce the power consumption. In order to achieve a higher resolution, the non-linear effects due to the imperfection of the circuits should be taken into account. Another important issue is the tonal behavior which can degrade the SNR should also be taken into consideration. Some practical solutions that can reduce the non-linear phenomenon described in the previous sections should be added into the circuit-level

implementation.

Chapter 3

The Proposed

Low-Voltage Low-Power Sigma-Delta Modulator for Humidity Sensors

3.1 Introduction

In this chapter, the structure of the proposed sigma-delta modulator is presented.

We introduce the proposed first-order sigma-delta modulator for humidity sensors in Section 3.2. In Section 3.3, the proposed second-order sigma-delta modulator is introduced. The oversampling ratio and the effect of finite-gain amplifier are simulated by MATLAB. In Section 3.4, the tonal behavior of both first-order and second-order sigma-delta modulators are discussed. The methods to reduce the tonal behavior are also presented.

3.2 The First-Order Sigma-Delta Modulator

3.2.1 Circuit Architecture

Figure 3-1 shows the structure utilizing a sigma-delta technique for humidity

sensors[16][17][18]. Based on the sigma-delta technique, the first-order sigma-delta modulator detects the capacitance change and provides the digital readout with good accuracy. The structure consists of a SC integrator, a comparator, and a simple 1-bit feedback DAC.

Figure 3-1 The first-order sigma-delta modulator

In the proposed circuit, C₁ is the sensor capacitor, C₂ is the reference capacitor, and C_R is used for the feedback DAC.The basic idea of the proposed sigma-delta modulator is based on the two types of parasitic insensitive integrators shown in Figure 3-2. The parasitic insensitive integrator is a critical component in high-accuracy switched-capacitor integrated circuits. The first one shown in Figure 3-2(a) is a noninverting SC integrator. The transfer function is found to be

( ) ( )

The second one shown in Figure 3-2(b) is a delay-free integrator. It has the transfer function as

By combining the two types of SC integrators[2][3], we can implement a front-end circuit which can detect the capacitance difference of the sensor. So in our design, a capacitance-to-voltage converter is not needed. The power consumption in our design is reduced comparing to other approaches.

quantizer

(a)

(b)

Figure 3-2 (a) Noninverting SC integrator (b) Delay-free SC integrator

In order to understand the operation of the proposed circuit, how the circuit works at each phase is shown in Figure 3-3 and 3-4. Figure 3-3 illustrates the operation when output y=1 at each phase. Figure 3-4 illustrates the operation when output y=0 at each phase.

φ1 φ1

φ2 φ2

C1

C

²

Vout φ1

φ1 φ2 φ2

C1

C

²

Vout Vin

Vin

Figure 3-3 Operation when output y=1

At phase 2φ , total charge transferring into integrator capacitor C_f causes

( )

^{1 REF 2 REF R REF}

From the same mechanism when y=0 as shown in Figure 3-4, the output voltage of the integrator is given by number of the cycles when y=0. Combine both equations (3.3) and (3.4)and base on the concept of the sigma-delta technique, we obtain the relation between input and

Cf

output as follows:

Figure 3-4 Operation when y=0

From equation (3.5) derived above, ∆C is the difference between sensor capacitor and reference capacitor. After K clock cycles, the circuit provides digital output according to the capacitance change.

3.2.2 Determine OSR and finite gain of the operational amplifier

As discussed in Section 2.4.2, choosing an appropriate OSR is important in the

quantizer

design of sigma-delta modulator. In this section, our goal is to determine an OSR for the system to achieve 10-bit resolution. The analysis is done by the MATLAB simulation based on the z-domain linear model. We construct the system in SIMULINK as shown in Figure 3-5. By changing different OSR of the simulated system, we obtain the result in Table 3-1. Table 3-1 shows the relationship between OSR and peak SNR. We know that doubling OSR increases peak SNR approximately by 9dB. The outcome is the same as shown in section 2.2.2. According to Table 3-1, we choose OSR >128 to meet our requirement.

Figure 3-5 Z-domain linear model by MATLAB simulation

OSR SNR ENOB

By replacing the ideal integrator by a leaky integrator due to the finite gain of the amplifier, we analyze the effect of leaky integrator and obtain the minimum requirement of the DC gain of the amplifier. We choose OSR to be 256 in this analysis.

The simulation result from SIMULINK is shown in Figure 3-6. It shows the obtained SNR versus the amplifier gains in the proposed structure. The minimum gain requirement for amplifier is 40dB to ensure over 70dB SNR of the first-order modulator. The gain requirement is only determined by the noise shaping consideration. If the distortion of the circuit should be taken into consideration, a higher amplifier gain should be achieved to ensure a better distortion performance.

1

Figure 3-6 SNR versus amplifier gain

3.2.3 SNR Prediction

In this section, we derive the mathematical equation to predict the SNR accurately. The derivation utilizes the linear model shown in Figure 3-7. The model includes the integrator leakage. This means that the factor β is less than 1. ∆Cis the capacitance change of the sensor, E is the quantization noise, and Y is the output of the modulator.

Figure 3-7 Linear model of the proposed structure

Figure 3-7 Linear model of the proposed structure

在文檔中 應用於溼度感測器之低電壓低功率三角積分調變器 (頁 13-0)