Implementation of Integrators

4.3.1 Low Voltage Low Power Operational Amplifier

The amplifier is the main building block of the sigma-delta modulator. It determines the total power consumption of the modulator. According to the comparison in [21], a single-stage amplifier is more power efficient than two-stage amplifier. So the current-mirror amplifier proposed in [21] is preferred, and all transistors are operated in weak inversion to meet the ultra low power requirement.

The minimum gain requirement for the amplifier is 40dB to ensure 10-bit resolution from Section 3.3.2. The architecture of the current mirror amplifier is shown in Figure 4-5. The B factor is the current gain from the diode-connected transistor to the transistor connected to the output node. Transistors M3a and M4a are added to enhance the DC gain without extra power consumption. The unit-gain bandwidth of the proposed topology is derived as

1 The above equation shows that unit-gain bandwidth will be multiplied by B. The DC gain of the current mirror amplifier is obtain by

(

)

The parameter k is between 0 and 1, and k should be appropriately determined to

m D

g I

maintain a safe phase margin. In our design, the current mirror amplifier has DC gain of 60dB and unit-gain bandwidth of 68 kHz. The simulation result in different corner is shown in Figure 4-6.

Figure 4-5 Proposed low power operational amplifier

Figure 4-6 Frequency response in different cases

4.3.2 Bias Circuit in Weak Inversion

The disadvantage of analog blocks operating in weak inversion is the high sensitivity to temperature variation. In order to reduce the effect of temperature variation, the bias circuit shown in Figure 4-7 generates a constant current, IREF, irrelative to temperature. The bias circuit is composed of a PTAT current source and a VEB referenced current source. The PTAT current source, I1, is formed by transistors M1, M2, M3, M4, and R1.The PTAT current source, I1, is given by

current source I₂ is given by

2 2

VEB

I = R . (4.9)

Since the temperature coefficient of I₁ is positive, and the temperature coefficient of I2 is negative, the reference current, I_REF , can be temperature independent by appropriately adjusting K₁ and K₂. The bias circuit consumes less power than many other bias circuits used for analog circuits operating in weak inversion. In our design, all transistors are operating in weak inversion, and the transistor Q1 is the lateral BJT. Many bias circuits, such as in [13] and [15], are designed in strong inversion which consumes more power. The simulation result in Figure 4-8 shows that the maximum reference current variation is 6nA when temperature varies from 0 to 100.

Figure 4-7 Bias circuit

M1 M2

Figure 4-8 I_REF versus Temperature

4.3.3 Switch Consideration

In switch-capacitor circuits, a MOS switch is a most often used components. The MOS switch nonidealities includes a nonzero and nonlinear on-resistance, clock feedthrough, channel charge injection, sampled noise, and leakage current. We consider clock feedthrough and channel-charge injection. The two factors may produce idle tones in sigma-delta modulators. When the switch is turned off, the channel charges are released and removed through MOS source and drain terminal.

The charges inject into the integrating capacitor and affect the accuracy of the integrator.

The simplest way to reduce the effect of the charge injection is to use complementary switches. However, the technique is inefficient due to the mismatch of the n-MOS and p-MOS devices. The matching between the channel charges of the n-MOS and p-MOS devices is poor and signal dependent. In our design, we adopt the n-MOS switch with two compensating dummy switches, M2 and M3, shown in Figure 4-9[20]. In order to force the channel charges to flow equally into the source and drain terminal, clock phases with short transition time is used. The size of dummy switches is set to be half of the switch M1.

Figure 4-9 Switch with dummy

4.3.4 Voltage Multiplier

In order to guarantee an adequately low switch resistance in a low voltage switched-capacitor circuits, the output voltage of the clock used to drive the switches can be boost higher than supply voltage. Therefore, the voltage multiplier technique is implemented. It doubles the output voltage of each clock phase. Figure 4-10 shows a voltage boosted clock driver used in our design. C1 and C2 are charged to Vdd via the cross-coupled NMOS M1 and M2. When the input clock, CK, goes high, the output voltage, CKsw, is boosted to 2Vdd. However, the output can not actually reach 2Vdd

φ φ φ

M1

M2 ^M3

due to charge sharing with parasitic capacitance. C2 must be large enough to boost the gates of many MOS transistors to reduce the impact of charge sharing. To decrease the potential for latch-up, the bulk of the PMOS M3 is tied to an on-chip voltage doubler.

The bulk of the PMOS switch is biased by the circuit shown in Figure 4-11 [6]. The simulation result in combined with clock generator shown in Section 4.5.

Figure 4-10 Voltage boosted clock driver

Figure 4-11 Voltage doubler

4.3.5 SC Integrator with Correlated double sampling

In order to reduce the effect of finite amplifier gain, noise, and offset voltage, the correlated double sampling (CDS) technique is used [20]. Figure 4-12 is the structure of the integrator with CDS. The capacitor CH is to sample the error voltage when φ1 is high. For a non-ideal integrator, the output in the time domain can be represented as

( ) ( ) (

)

out in out OS

V n = −k Vα n +βV n− +γV . (4.10) Here, α denotes the gain of the non-ideal integrator; β is the new pole location; while γ

Vdd

M1 M2

Vbulk

M3 CK

C1 C₂

CKsw

Vdd

CK

Vbulk

is the suppression factor of the offset voltage VOS. In the proposed CDS integrator, the parameters in (4.10) is given as follows[19]:

1 proposed sigma-delta modulator to eliminate the non-linear effects.

Figure 4-12 Switch-capacitor integrator with CDS